1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 if (!ap->tar_valid || tar != ap->tar_value) {
115 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
116 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
117 if (retval != ERROR_OK)
120 ap->tar_valid = true;
125 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
127 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
128 if (retval != ERROR_OK) {
129 ap->tar_valid = false;
133 retval = dap_run(ap->dap);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
139 ap->tar_value = *tar;
140 ap->tar_valid = true;
144 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
146 switch (ap->csw_value & CSW_ADDRINC_MASK) {
147 case CSW_ADDRINC_SINGLE:
148 switch (ap->csw_value & CSW_SIZE_MASK) {
156 case CSW_ADDRINC_PACKED:
162 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
164 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
169 uint32_t inc = mem_ap_get_tar_increment(ap);
170 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
171 ap->tar_valid = false;
173 ap->tar_value += inc;
177 * Queue transactions setting up transfer parameters for the
178 * currently selected MEM-AP.
180 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
181 * initiate data reads or writes using memory or peripheral addresses.
182 * If the CSW is configured for it, the TAR may be automatically
183 * incremented after each transfer.
185 * @param ap The MEM-AP.
186 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
187 * matches the cached value, the register is not changed.
188 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
189 * matches the cached address, the register is not changed.
191 * @return ERROR_OK if the transaction was properly queued, else a fault code.
193 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
196 retval = mem_ap_setup_csw(ap, csw);
197 if (retval != ERROR_OK)
199 retval = mem_ap_setup_tar(ap, tar);
200 if (retval != ERROR_OK)
206 * Asynchronous (queued) read of a word from memory or a system register.
208 * @param ap The MEM-AP to access.
209 * @param address Address of the 32-bit word to read; it must be
210 * readable by the currently selected MEM-AP.
211 * @param value points to where the word will be stored when the
212 * transaction queue is flushed (assuming no errors).
214 * @return ERROR_OK for success. Otherwise a fault code.
216 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when reading several consecutive addresses.
224 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
225 address & 0xFFFFFFF0);
226 if (retval != ERROR_OK)
229 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
233 * Synchronous read of a word from memory or a system register.
234 * As a side effect, this flushes any queued transactions.
236 * @param ap The MEM-AP to access.
237 * @param address Address of the 32-bit word to read; it must be
238 * readable by the currently selected MEM-AP.
239 * @param value points to where the result will be stored.
241 * @return ERROR_OK for success; *value holds the result.
242 * Otherwise a fault code.
244 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
249 retval = mem_ap_read_u32(ap, address, value);
250 if (retval != ERROR_OK)
253 return dap_run(ap->dap);
257 * Asynchronous (queued) write of a word to memory or a system register.
259 * @param ap The MEM-AP to access.
260 * @param address Address to be written; it must be writable by
261 * the currently selected MEM-AP.
262 * @param value Word that will be written to the address when transaction
263 * queue is flushed (assuming no errors).
265 * @return ERROR_OK for success. Otherwise a fault code.
267 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
272 /* Use banked addressing (REG_BDx) to avoid some link traffic
273 * (updating TAR) when writing several consecutive addresses.
275 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
276 address & 0xFFFFFFF0);
277 if (retval != ERROR_OK)
280 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
285 * Synchronous write of a word to memory or a system register.
286 * As a side effect, this flushes any queued transactions.
288 * @param ap The MEM-AP to access.
289 * @param address Address to be written; it must be writable by
290 * the currently selected MEM-AP.
291 * @param value Word that will be written.
293 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
295 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
298 int retval = mem_ap_write_u32(ap, address, value);
300 if (retval != ERROR_OK)
303 return dap_run(ap->dap);
307 * Synchronous write of a block of memory, using a specific access size.
309 * @param ap The MEM-AP to access.
310 * @param buffer The data buffer to write. No particular alignment is assumed.
311 * @param size Which access size to use, in bytes. 1, 2 or 4.
312 * @param count The number of writes to do (in size units, not bytes).
313 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
314 * @param addrinc Whether the target address should be increased for each write or not. This
315 * should normally be true, except when writing to e.g. a FIFO.
316 * @return ERROR_OK on success, otherwise an error code.
318 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
319 uint32_t address, bool addrinc)
321 struct adiv5_dap *dap = ap->dap;
322 size_t nbytes = size * count;
323 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
328 /* TI BE-32 Quirks mode:
329 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
330 * size write address bytes written in order
331 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
332 * 2 TAR ^ 2 (val >> 8), (val)
334 * For example, if you attempt to write a single byte to address 0, the processor
335 * will actually write a byte to address 3.
337 * To make writes of size < 4 work as expected, we xor a value with the address before
338 * setting the TAP, and we set the TAP after every transfer rather then relying on
339 * address increment. */
342 csw_size = CSW_32BIT;
344 } else if (size == 2) {
345 csw_size = CSW_16BIT;
346 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
347 } else if (size == 1) {
349 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
351 return ERROR_TARGET_UNALIGNED_ACCESS;
354 if (ap->unaligned_access_bad && (address % size != 0))
355 return ERROR_TARGET_UNALIGNED_ACCESS;
358 uint32_t this_size = size;
360 /* Select packed transfer if possible */
361 if (addrinc && ap->packed_transfers && nbytes >= 4
362 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
364 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
366 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
369 if (retval != ERROR_OK)
372 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
373 if (retval != ERROR_OK)
376 /* How many source bytes each transfer will consume, and their location in the DRW,
377 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
378 uint32_t outvalue = 0;
379 if (dap->ti_be_32_quirks) {
382 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
383 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
384 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
385 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
389 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
398 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
399 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
402 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
405 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
411 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
412 if (retval != ERROR_OK)
415 mem_ap_update_tar_cache(ap);
418 /* REVISIT: Might want to have a queued version of this function that does not run. */
419 if (retval == ERROR_OK)
420 retval = dap_run(dap);
422 if (retval != ERROR_OK) {
424 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
425 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
427 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
434 * Synchronous read of a block of memory, using a specific access size.
436 * @param ap The MEM-AP to access.
437 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
438 * @param size Which access size to use, in bytes. 1, 2 or 4.
439 * @param count The number of reads to do (in size units, not bytes).
440 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
441 * @param addrinc Whether the target address should be increased after each read or not. This
442 * should normally be true, except when reading from e.g. a FIFO.
443 * @return ERROR_OK on success, otherwise an error code.
445 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
446 uint32_t adr, bool addrinc)
448 struct adiv5_dap *dap = ap->dap;
449 size_t nbytes = size * count;
450 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
452 uint32_t address = adr;
455 /* TI BE-32 Quirks mode:
456 * Reads on big-endian TMS570 behave strangely differently than writes.
457 * They read from the physical address requested, but with DRW byte-reversed.
458 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
459 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
463 csw_size = CSW_32BIT;
465 csw_size = CSW_16BIT;
469 return ERROR_TARGET_UNALIGNED_ACCESS;
471 if (ap->unaligned_access_bad && (adr % size != 0))
472 return ERROR_TARGET_UNALIGNED_ACCESS;
474 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
475 * over-allocation if packed transfers are going to be used, but determining the real need at
476 * this point would be messy. */
477 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
478 uint32_t *read_ptr = read_buf;
479 if (read_buf == NULL) {
480 LOG_ERROR("Failed to allocate read buffer");
484 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
485 * useful bytes it contains, and their location in the word, depends on the type of transfer
488 uint32_t this_size = size;
490 /* Select packed transfer if possible */
491 if (addrinc && ap->packed_transfers && nbytes >= 4
492 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
494 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
496 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
498 if (retval != ERROR_OK)
501 retval = mem_ap_setup_tar(ap, address);
502 if (retval != ERROR_OK)
505 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
506 if (retval != ERROR_OK)
510 address += this_size;
512 mem_ap_update_tar_cache(ap);
515 if (retval == ERROR_OK)
516 retval = dap_run(dap);
520 nbytes = size * count;
523 /* If something failed, read TAR to find out how much data was successfully read, so we can
524 * at least give the caller what we have. */
525 if (retval != ERROR_OK) {
527 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
528 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
529 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
530 if (nbytes > tar - address)
531 nbytes = tar - address;
533 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
538 /* Replay loop to populate caller's buffer from the correct word and byte lane */
540 uint32_t this_size = size;
542 if (addrinc && ap->packed_transfers && nbytes >= 4
543 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
547 if (dap->ti_be_32_quirks) {
550 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
551 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
554 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
557 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
562 *buffer++ = *read_ptr >> 8 * (address++ & 3);
563 *buffer++ = *read_ptr >> 8 * (address++ & 3);
566 *buffer++ = *read_ptr >> 8 * (address++ & 3);
569 *buffer++ = *read_ptr >> 8 * (address++ & 3);
581 int mem_ap_read_buf(struct adiv5_ap *ap,
582 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
584 return mem_ap_read(ap, buffer, size, count, address, true);
587 int mem_ap_write_buf(struct adiv5_ap *ap,
588 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
590 return mem_ap_write(ap, buffer, size, count, address, true);
593 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
594 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 return mem_ap_read(ap, buffer, size, count, address, false);
599 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
600 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 return mem_ap_write(ap, buffer, size, count, address, false);
605 /*--------------------------------------------------------------------------*/
608 #define DAP_POWER_DOMAIN_TIMEOUT (10)
610 /* FIXME don't import ... just initialize as
611 * part of DAP transport setup
613 extern const struct dap_ops jtag_dp_ops;
615 /*--------------------------------------------------------------------------*/
620 struct adiv5_dap *dap_init(void)
622 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
624 /* Set up with safe defaults */
625 for (i = 0; i <= 255; i++) {
626 dap->ap[i].dap = dap;
627 dap->ap[i].ap_num = i;
628 /* memaccess_tck max is 255 */
629 dap->ap[i].memaccess_tck = 255;
630 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
631 dap->ap[i].tar_autoincr_block = (1<<10);
633 INIT_LIST_HEAD(&dap->cmd_journal);
638 * Invalidate cached DP select and cached TAR and CSW of all APs
640 void dap_invalidate_cache(struct adiv5_dap *dap)
642 dap->select = DP_SELECT_INVALID;
643 dap->last_read = NULL;
646 for (i = 0; i <= 255; i++) {
647 /* force csw and tar write on the next mem-ap access */
648 dap->ap[i].tar_valid = false;
649 dap->ap[i].csw_value = 0;
654 * Initialize a DAP. This sets up the power domains, prepares the DP
655 * for further use and activates overrun checking.
657 * @param dap The DAP being initialized.
659 int dap_dp_init(struct adiv5_dap *dap)
664 /* JTAG-DP or SWJ-DP, in JTAG mode
665 * ... for SWD mode this is patched as part
667 * FIXME: This should already be setup by the respective transport specific DAP creation.
670 dap->ops = &jtag_dp_ops;
672 dap_invalidate_cache(dap);
674 for (size_t i = 0; i < 30; i++) {
675 /* DP initialization */
677 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
678 if (retval == ERROR_OK)
682 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
683 if (retval != ERROR_OK)
686 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
687 if (retval != ERROR_OK)
690 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
691 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
692 if (retval != ERROR_OK)
695 /* Check that we have debug power domains activated */
696 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
697 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
698 CDBGPWRUPACK, CDBGPWRUPACK,
699 DAP_POWER_DOMAIN_TIMEOUT);
700 if (retval != ERROR_OK)
703 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
704 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
705 CSYSPWRUPACK, CSYSPWRUPACK,
706 DAP_POWER_DOMAIN_TIMEOUT);
707 if (retval != ERROR_OK)
710 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
711 if (retval != ERROR_OK)
714 /* With debug power on we can activate OVERRUN checking */
715 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
716 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
717 if (retval != ERROR_OK)
719 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
720 if (retval != ERROR_OK)
723 retval = dap_run(dap);
724 if (retval != ERROR_OK)
731 * Initialize a DAP. This sets up the power domains, prepares the DP
732 * for further use, and arranges to use AP #0 for all AP operations
733 * until dap_ap-select() changes that policy.
735 * @param ap The MEM-AP being initialized.
737 int mem_ap_init(struct adiv5_ap *ap)
739 /* check that we support packed transfers */
742 struct adiv5_dap *dap = ap->dap;
744 ap->tar_valid = false;
745 ap->csw_value = 0; /* force csw and tar write */
746 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
747 if (retval != ERROR_OK)
750 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
751 if (retval != ERROR_OK)
754 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
755 if (retval != ERROR_OK)
758 retval = dap_run(dap);
759 if (retval != ERROR_OK)
762 if (csw & CSW_ADDRINC_PACKED)
763 ap->packed_transfers = true;
765 ap->packed_transfers = false;
767 /* Packed transfers on TI BE-32 processors do not work correctly in
769 if (dap->ti_be_32_quirks)
770 ap->packed_transfers = false;
772 LOG_DEBUG("MEM_AP Packed Transfers: %s",
773 ap->packed_transfers ? "enabled" : "disabled");
775 /* The ARM ADI spec leaves implementation-defined whether unaligned
776 * memory accesses work, only work partially, or cause a sticky error.
777 * On TI BE-32 processors, reads seem to return garbage in some bytes
778 * and unaligned writes seem to cause a sticky error.
779 * TODO: it would be nice to have a way to detect whether unaligned
780 * operations are supported on other processors. */
781 ap->unaligned_access_bad = dap->ti_be_32_quirks;
783 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
784 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
789 /* CID interpretation -- see ARM IHI 0029B section 3
790 * and ARM IHI 0031A table 13-3.
792 static const char *class_description[16] = {
793 "Reserved", "ROM table", "Reserved", "Reserved",
794 "Reserved", "Reserved", "Reserved", "Reserved",
795 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
796 "Reserved", "OptimoDE DESS",
797 "Generic IP component", "PrimeCell or System component"
800 static bool is_dap_cid_ok(uint32_t cid)
802 return (cid & 0xffff0fff) == 0xb105000d;
806 * This function checks the ID for each access port to find the requested Access Port type
808 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
812 /* Maximum AP number is 255 since the SELECT register is 8 bits */
813 for (ap_num = 0; ap_num <= 255; ap_num++) {
815 /* read the IDR register of the Access Port */
818 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
819 if (retval != ERROR_OK)
822 retval = dap_run(dap);
826 * 27-24 : JEDEC bank (0x4 for ARM)
827 * 23-17 : JEDEC code (0x3B for ARM)
828 * 16-13 : Class (0b1000=Mem-AP)
830 * 7-4 : AP Variant (non-zero for JTAG-AP)
831 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
834 /* Reading register for a non-existant AP should not cause an error,
835 * but just to be sure, try to continue searching if an error does happen.
837 if ((retval == ERROR_OK) && /* Register read success */
838 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
839 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
841 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
842 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
843 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
844 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
845 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
848 *ap_out = &dap->ap[ap_num];
853 LOG_DEBUG("No %s found",
854 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
855 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
856 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
857 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
861 int dap_get_debugbase(struct adiv5_ap *ap,
862 uint32_t *dbgbase, uint32_t *apid)
864 struct adiv5_dap *dap = ap->dap;
867 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
868 if (retval != ERROR_OK)
870 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
871 if (retval != ERROR_OK)
873 retval = dap_run(dap);
874 if (retval != ERROR_OK)
880 int dap_lookup_cs_component(struct adiv5_ap *ap,
881 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
883 uint32_t romentry, entry_offset = 0, component_base, devtype;
889 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
890 entry_offset, &romentry);
891 if (retval != ERROR_OK)
894 component_base = (dbgbase & 0xFFFFF000)
895 + (romentry & 0xFFFFF000);
897 if (romentry & 0x1) {
899 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
900 if (retval != ERROR_OK) {
901 LOG_ERROR("Can't read component with base address 0x%" PRIx32
902 ", the corresponding core might be turned off", component_base);
905 if (((c_cid1 >> 4) & 0x0f) == 1) {
906 retval = dap_lookup_cs_component(ap, component_base,
908 if (retval == ERROR_OK)
910 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
914 retval = mem_ap_read_atomic_u32(ap,
915 (component_base & 0xfffff000) | 0xfcc,
917 if (retval != ERROR_OK)
919 if ((devtype & 0xff) == type) {
921 *addr = component_base;
928 } while (romentry > 0);
931 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
936 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
938 assert((component_base & 0xFFF) == 0);
939 assert(ap != NULL && cid != NULL && pid != NULL);
941 uint32_t cid0, cid1, cid2, cid3;
942 uint32_t pid0, pid1, pid2, pid3, pid4;
945 /* IDs are in last 4K section */
946 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
947 if (retval != ERROR_OK)
949 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
950 if (retval != ERROR_OK)
952 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
953 if (retval != ERROR_OK)
955 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
956 if (retval != ERROR_OK)
958 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
959 if (retval != ERROR_OK)
961 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
962 if (retval != ERROR_OK)
964 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
965 if (retval != ERROR_OK)
967 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
968 if (retval != ERROR_OK)
970 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
971 if (retval != ERROR_OK)
974 retval = dap_run(ap->dap);
975 if (retval != ERROR_OK)
978 *cid = (cid3 & 0xff) << 24
979 | (cid2 & 0xff) << 16
982 *pid = (uint64_t)(pid4 & 0xff) << 32
983 | (pid3 & 0xff) << 24
984 | (pid2 & 0xff) << 16
991 /* The designer identity code is encoded as:
992 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
993 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
994 * a legacy ASCII Identity Code.
995 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
996 * JEP106 is a standard available from jedec.org
999 /* Part number interpretations are from Cortex
1000 * core specs, the CoreSight components TRM
1001 * (ARM DDI 0314H), CoreSight System Design
1002 * Guide (ARM DGI 0012D) and ETM specs; also
1003 * from chip observation (e.g. TI SDTI).
1006 /* The legacy code only used the part number field to identify CoreSight peripherals.
1007 * This meant that the same part number from two different manufacturers looked the same.
1008 * It is desirable for all future additions to identify with both part number and JEP106.
1009 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1012 #define ANY_ID 0x1000
1014 #define ARM_ID 0x4BB
1016 static const struct {
1017 uint16_t designer_id;
1021 } dap_partnums[] = {
1022 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1023 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1024 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1025 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1026 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1027 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1028 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1029 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1030 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1031 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1032 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1033 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1034 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1035 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1036 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1037 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1038 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1039 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1040 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1041 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1042 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1043 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1044 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1045 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1046 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1047 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1048 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1049 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1050 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1051 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1052 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1053 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1054 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1055 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1056 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1057 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1058 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1059 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1060 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1061 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1062 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1063 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1064 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1065 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1066 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1067 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1068 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1069 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1070 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1071 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1072 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1073 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1074 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1075 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1076 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1077 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1078 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1079 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1080 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1081 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1082 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1083 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1084 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1085 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1086 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1087 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1088 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1089 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1090 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1091 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1092 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1093 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1094 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1095 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1096 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1097 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1098 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1099 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1100 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1101 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1102 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1103 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1104 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1105 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1106 /* legacy comment: 0x113: what? */
1107 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1108 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1111 static int dap_rom_display(struct command_context *cmd_ctx,
1112 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1120 command_print(cmd_ctx, "\tTables too deep");
1125 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1127 uint32_t base_addr = dbgbase & 0xFFFFF000;
1128 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1130 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1131 if (retval != ERROR_OK) {
1132 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1133 return ERROR_OK; /* Don't abort recursion */
1136 if (!is_dap_cid_ok(cid)) {
1137 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1138 return ERROR_OK; /* Don't abort recursion */
1141 /* component may take multiple 4K pages */
1142 uint32_t size = (pid >> 36) & 0xf;
1144 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1146 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1148 uint8_t class = (cid >> 12) & 0xf;
1149 uint16_t part_num = pid & 0xfff;
1150 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1152 if (designer_id & 0x80) {
1154 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1155 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1157 /* Legacy ASCII ID, clear invalid bits */
1158 designer_id &= 0x7f;
1159 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1160 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1163 /* default values to be overwritten upon finding a match */
1164 const char *type = "Unrecognized";
1165 const char *full = "";
1167 /* search dap_partnums[] array for a match */
1168 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1170 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1173 if (dap_partnums[entry].part_num != part_num)
1176 type = dap_partnums[entry].type;
1177 full = dap_partnums[entry].full;
1181 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1182 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1184 if (class == 1) { /* ROM Table */
1186 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1187 if (retval != ERROR_OK)
1191 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1193 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1195 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1196 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1198 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1199 if (retval != ERROR_OK)
1201 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1202 tabs, entry_offset, romentry);
1203 if (romentry & 0x01) {
1205 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1206 if (retval != ERROR_OK)
1208 } else if (romentry != 0) {
1209 command_print(cmd_ctx, "\t\tComponent not present");
1211 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1215 } else if (class == 9) { /* CoreSight component */
1216 const char *major = "Reserved", *subtype = "Reserved";
1219 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1220 if (retval != ERROR_OK)
1222 unsigned minor = (devtype >> 4) & 0x0f;
1223 switch (devtype & 0x0f) {
1225 major = "Miscellaneous";
1231 subtype = "Validation component";
1236 major = "Trace Sink";
1253 major = "Trace Link";
1259 subtype = "Funnel, router";
1265 subtype = "FIFO, buffer";
1270 major = "Trace Source";
1276 subtype = "Processor";
1282 subtype = "Engine/Coprocessor";
1288 subtype = "Software";
1293 major = "Debug Control";
1299 subtype = "Trigger Matrix";
1302 subtype = "Debug Auth";
1305 subtype = "Power Requestor";
1310 major = "Debug Logic";
1316 subtype = "Processor";
1322 subtype = "Engine/Coprocessor";
1333 major = "Perfomance Monitor";
1339 subtype = "Processor";
1345 subtype = "Engine/Coprocessor";
1356 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1357 (uint8_t)(devtype & 0xff),
1359 /* REVISIT also show 0xfc8 DevId */
1365 static int dap_info_command(struct command_context *cmd_ctx,
1366 struct adiv5_ap *ap)
1369 uint32_t dbgbase, apid;
1372 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1373 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1374 if (retval != ERROR_OK)
1377 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1379 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1383 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1384 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1385 command_print(cmd_ctx, "\tType is JTAG-AP");
1387 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1388 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1390 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1391 command_print(cmd_ctx, "\tType is MEM-AP APB");
1393 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1394 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1397 command_print(cmd_ctx, "\tUnknown AP type");
1401 /* NOTE: a MEM-AP may have a single CoreSight component that's
1402 * not a ROM table ... or have no such components at all.
1404 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1406 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1408 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1409 command_print(cmd_ctx, "\tNo ROM table present");
1412 command_print(cmd_ctx, "\tValid ROM table present");
1414 command_print(cmd_ctx, "\tROM table in legacy format");
1416 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1423 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1425 struct adiv5_private_config *pc;
1430 /* check if argv[0] is for us */
1431 arg = Jim_GetString(goi->argv[0], NULL);
1432 if (strcmp(arg, "-ap-num"))
1433 return JIM_CONTINUE;
1435 e = Jim_GetOpt_String(goi, &arg, NULL);
1439 if (goi->argc == 0) {
1440 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
1444 e = Jim_GetOpt_Wide(goi, &ap_num);
1448 if (target->private_config == NULL) {
1449 pc = calloc(1, sizeof(struct adiv5_private_config));
1450 target->private_config = pc;
1451 pc->ap_num = ap_num;
1458 COMMAND_HANDLER(handle_dap_info_command)
1460 struct target *target = get_current_target(CMD_CTX);
1461 struct arm *arm = target_to_arm(target);
1462 struct adiv5_dap *dap = arm->dap;
1470 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1472 return ERROR_COMMAND_SYNTAX_ERROR;
1475 return ERROR_COMMAND_SYNTAX_ERROR;
1478 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1481 COMMAND_HANDLER(dap_baseaddr_command)
1483 struct target *target = get_current_target(CMD_CTX);
1484 struct arm *arm = target_to_arm(target);
1485 struct adiv5_dap *dap = arm->dap;
1487 uint32_t apsel, baseaddr;
1495 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1496 /* AP address is in bits 31:24 of DP_SELECT */
1498 return ERROR_COMMAND_SYNTAX_ERROR;
1501 return ERROR_COMMAND_SYNTAX_ERROR;
1504 /* NOTE: assumes we're talking to a MEM-AP, which
1505 * has a base address. There are other kinds of AP,
1506 * though they're not common for now. This should
1507 * use the ID register to verify it's a MEM-AP.
1509 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1510 if (retval != ERROR_OK)
1512 retval = dap_run(dap);
1513 if (retval != ERROR_OK)
1516 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1521 COMMAND_HANDLER(dap_memaccess_command)
1523 struct target *target = get_current_target(CMD_CTX);
1524 struct arm *arm = target_to_arm(target);
1525 struct adiv5_dap *dap = arm->dap;
1527 uint32_t memaccess_tck;
1531 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1534 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1537 return ERROR_COMMAND_SYNTAX_ERROR;
1539 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1541 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1542 dap->ap[dap->apsel].memaccess_tck);
1547 COMMAND_HANDLER(dap_apsel_command)
1549 struct target *target = get_current_target(CMD_CTX);
1550 struct arm *arm = target_to_arm(target);
1551 struct adiv5_dap *dap = arm->dap;
1553 uint32_t apsel, apid;
1561 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1562 /* AP address is in bits 31:24 of DP_SELECT */
1564 return ERROR_COMMAND_SYNTAX_ERROR;
1567 return ERROR_COMMAND_SYNTAX_ERROR;
1572 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1573 if (retval != ERROR_OK)
1575 retval = dap_run(dap);
1576 if (retval != ERROR_OK)
1579 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1585 COMMAND_HANDLER(dap_apcsw_command)
1587 struct target *target = get_current_target(CMD_CTX);
1588 struct arm *arm = target_to_arm(target);
1589 struct adiv5_dap *dap = arm->dap;
1591 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1595 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1596 (dap->apsel), apcsw);
1599 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1600 /* AP address is in bits 31:24 of DP_SELECT */
1602 return ERROR_COMMAND_SYNTAX_ERROR;
1606 apcsw &= ~CSW_SPROT;
1609 return ERROR_COMMAND_SYNTAX_ERROR;
1611 dap->ap[dap->apsel].csw_default = apcsw;
1618 COMMAND_HANDLER(dap_apid_command)
1620 struct target *target = get_current_target(CMD_CTX);
1621 struct arm *arm = target_to_arm(target);
1622 struct adiv5_dap *dap = arm->dap;
1624 uint32_t apsel, apid;
1632 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1633 /* AP address is in bits 31:24 of DP_SELECT */
1635 return ERROR_COMMAND_SYNTAX_ERROR;
1638 return ERROR_COMMAND_SYNTAX_ERROR;
1641 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1642 if (retval != ERROR_OK)
1644 retval = dap_run(dap);
1645 if (retval != ERROR_OK)
1648 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1653 COMMAND_HANDLER(dap_apreg_command)
1655 struct target *target = get_current_target(CMD_CTX);
1656 struct arm *arm = target_to_arm(target);
1657 struct adiv5_dap *dap = arm->dap;
1659 uint32_t apsel, reg, value;
1662 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1663 return ERROR_COMMAND_SYNTAX_ERROR;
1665 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1666 /* AP address is in bits 31:24 of DP_SELECT */
1668 return ERROR_COMMAND_SYNTAX_ERROR;
1670 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1671 if (reg >= 256 || (reg & 3))
1672 return ERROR_COMMAND_SYNTAX_ERROR;
1674 if (CMD_ARGC == 3) {
1675 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1676 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1678 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1680 if (retval == ERROR_OK)
1681 retval = dap_run(dap);
1683 if (retval != ERROR_OK)
1687 command_print(CMD_CTX, "0x%08" PRIx32, value);
1692 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1694 struct target *target = get_current_target(CMD_CTX);
1695 struct arm *arm = target_to_arm(target);
1696 struct adiv5_dap *dap = arm->dap;
1698 uint32_t enable = dap->ti_be_32_quirks;
1704 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1706 return ERROR_COMMAND_SYNTAX_ERROR;
1709 return ERROR_COMMAND_SYNTAX_ERROR;
1711 dap->ti_be_32_quirks = enable;
1712 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1713 enable ? "enabled" : "disabled");
1718 static const struct command_registration dap_commands[] = {
1721 .handler = handle_dap_info_command,
1722 .mode = COMMAND_EXEC,
1723 .help = "display ROM table for MEM-AP "
1724 "(default currently selected AP)",
1725 .usage = "[ap_num]",
1729 .handler = dap_apsel_command,
1730 .mode = COMMAND_EXEC,
1731 .help = "Set the currently selected AP (default 0) "
1732 "and display the result",
1733 .usage = "[ap_num]",
1737 .handler = dap_apcsw_command,
1738 .mode = COMMAND_EXEC,
1739 .help = "Set csw access bit ",
1745 .handler = dap_apid_command,
1746 .mode = COMMAND_EXEC,
1747 .help = "return ID register from AP "
1748 "(default currently selected AP)",
1749 .usage = "[ap_num]",
1753 .handler = dap_apreg_command,
1754 .mode = COMMAND_EXEC,
1755 .help = "read/write a register from AP "
1756 "(reg is byte address of a word register, like 0 4 8...)",
1757 .usage = "ap_num reg [value]",
1761 .handler = dap_baseaddr_command,
1762 .mode = COMMAND_EXEC,
1763 .help = "return debug base address from MEM-AP "
1764 "(default currently selected AP)",
1765 .usage = "[ap_num]",
1768 .name = "memaccess",
1769 .handler = dap_memaccess_command,
1770 .mode = COMMAND_EXEC,
1771 .help = "set/get number of extra tck for MEM-AP memory "
1772 "bus access [0-255]",
1773 .usage = "[cycles]",
1776 .name = "ti_be_32_quirks",
1777 .handler = dap_ti_be_32_quirks_command,
1778 .mode = COMMAND_CONFIG,
1779 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1780 .usage = "[enable]",
1782 COMMAND_REGISTRATION_DONE
1785 const struct command_registration dap_command_handlers[] = {
1788 .mode = COMMAND_EXEC,
1789 .help = "DAP command group",
1791 .chain = dap_commands,
1793 COMMAND_REGISTRATION_DONE