1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
107 if (new_ap != dap->ap_current)
109 dap->ap_current = new_ap;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
149 dap->ap_csw_value = csw;
151 if (tar != dap->ap_tar_value)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
157 dap->ap_tar_value = tar;
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
258 int retval = mem_ap_write_u32(dap, address, value);
260 if (retval != ERROR_OK)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 const uint8_t* pBuffer = buffer;
282 /* if we have an unaligned access - reorder data */
285 for (writecount = 0; writecount < count; writecount++)
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
291 for (i = 0; i < 4; i++)
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
297 pBuffer += sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
308 /* handle unaligned data at 4k boundary */
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
316 for (writecount = 0; writecount < blocksize; writecount++)
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
324 if ((retval = dap_run(dap)) == ERROR_OK)
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 const uint8_t *buffer, int count, uint32_t address)
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
360 if (wcount < blocksize)
363 /* handle unaligned data at 4k boundary */
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
370 writecount = blocksize;
374 nbytes = MIN((writecount << 1), 4);
378 retval = mem_ap_write_buf_u16(dap, buffer,
380 if (retval != ERROR_OK)
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
388 address += nbytes >> 1;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
395 for (i = 0; i < nbytes; i++)
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
408 if ((retval = dap_run(dap)) != ERROR_OK)
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
420 } while (writecount);
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
429 int retval = ERROR_OK;
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 const uint8_t *buffer, int count, uint32_t address)
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
473 if (wcount < blocksize)
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
479 writecount = blocksize;
483 nbytes = MIN(writecount, 4);
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
503 for (i = 0; i < nbytes; i++)
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
516 if ((retval = dap_run(dap)) != ERROR_OK)
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
526 writecount -= nbytes;
528 } while (writecount);
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
537 int retval = ERROR_OK;
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
597 if (wcount < blocksize)
600 /* handle unaligned data at 4k boundary */
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
606 if (retval != ERROR_OK)
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
630 if (retval != ERROR_OK)
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
640 if (retval != ERROR_OK)
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
660 /* if we have an unaligned access - reorder data */
663 for (readcount = 0; readcount < count; readcount++)
667 memcpy(&data, pBuffer, sizeof(uint32_t));
669 for (i = 0; i < 4; i++)
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
704 /* handle unaligned data at 4k boundary */
707 readcount = blocksize;
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
714 if ((retval = dap_run(dap)) != ERROR_OK)
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
720 nbytes = MIN((readcount << 1), 4);
722 for (i = 0; i < nbytes; i++)
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
729 readcount -= (nbytes >> 1);
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
749 int retval = ERROR_OK;
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
769 for (i = 0; i < 2; i++)
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
811 if (wcount < blocksize)
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
817 readcount = blocksize;
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
824 if ((retval = dap_run(dap)) != ERROR_OK)
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
830 nbytes = MIN(readcount, 4);
832 for (i = 0; i < nbytes; i++)
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
859 int retval = ERROR_OK;
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
885 /*--------------------------------------------------------------------*/
886 /* Wrapping function with selection of AP */
887 /*--------------------------------------------------------------------*/
888 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
889 uint32_t address, uint32_t *value)
891 dap_ap_select(swjdp, ap);
892 return mem_ap_read_u32(swjdp, address, value);
895 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
896 uint32_t address, uint32_t value)
898 dap_ap_select(swjdp, ap);
899 return mem_ap_write_u32(swjdp, address, value);
902 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
903 uint32_t address, uint32_t *value)
905 dap_ap_select(swjdp, ap);
906 return mem_ap_read_atomic_u32(swjdp, address, value);
909 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
910 uint32_t address, uint32_t value)
912 dap_ap_select(swjdp, ap);
913 return mem_ap_write_atomic_u32(swjdp, address, value);
916 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
917 uint8_t *buffer, int count, uint32_t address)
919 dap_ap_select(swjdp, ap);
920 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
923 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
924 uint8_t *buffer, int count, uint32_t address)
926 dap_ap_select(swjdp, ap);
927 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
930 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
931 uint8_t *buffer, int count, uint32_t address)
933 dap_ap_select(swjdp, ap);
934 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
937 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
938 const uint8_t *buffer, int count, uint32_t address)
940 dap_ap_select(swjdp, ap);
941 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
944 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
945 const uint8_t *buffer, int count, uint32_t address)
947 dap_ap_select(swjdp, ap);
948 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
951 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
952 const uint8_t *buffer, int count, uint32_t address)
954 dap_ap_select(swjdp, ap);
955 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
959 /*--------------------------------------------------------------------------*/
962 /* FIXME don't import ... just initialize as
963 * part of DAP transport setup
965 extern const struct dap_ops jtag_dp_ops;
967 /*--------------------------------------------------------------------------*/
970 * Initialize a DAP. This sets up the power domains, prepares the DP
971 * for further use, and arranges to use AP #0 for all AP operations
972 * until dap_ap-select() changes that policy.
974 * @param dap The DAP being initialized.
976 * @todo Rename this. We also need an initialization scheme which account
977 * for SWD transports not just JTAG; that will need to address differences
978 * in layering. (JTAG is useful without any debug target; but not SWD.)
979 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
981 int ahbap_debugport_init(struct adiv5_dap *dap)
989 /* JTAG-DP or SWJ-DP, in JTAG mode
990 * ... for SWD mode this is patched as part
994 dap->ops = &jtag_dp_ops;
996 /* Default MEM-AP setup.
998 * REVISIT AP #0 may be an inappropriate default for this.
999 * Should we probe, or take a hint from the caller?
1000 * Presumably we can ignore the possibility of multiple APs.
1002 dap->ap_current = !0;
1003 dap_ap_select(dap, 0);
1005 /* DP initialization */
1007 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1008 if (retval != ERROR_OK)
1011 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1012 if (retval != ERROR_OK)
1015 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1016 if (retval != ERROR_OK)
1019 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1020 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1021 if (retval != ERROR_OK)
1024 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1025 if (retval != ERROR_OK)
1027 if ((retval = dap_run(dap)) != ERROR_OK)
1030 /* Check that we have debug power domains activated */
1031 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1033 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1034 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1035 if (retval != ERROR_OK)
1037 if ((retval = dap_run(dap)) != ERROR_OK)
1042 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1044 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1045 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1046 if (retval != ERROR_OK)
1048 if ((retval = dap_run(dap)) != ERROR_OK)
1053 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1054 if (retval != ERROR_OK)
1056 /* With debug power on we can activate OVERRUN checking */
1057 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1058 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1059 if (retval != ERROR_OK)
1061 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1062 if (retval != ERROR_OK)
1068 /* CID interpretation -- see ARM IHI 0029B section 3
1069 * and ARM IHI 0031A table 13-3.
1071 static const char *class_description[16] ={
1072 "Reserved", "ROM table", "Reserved", "Reserved",
1073 "Reserved", "Reserved", "Reserved", "Reserved",
1074 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1075 "Reserved", "OptimoDE DESS",
1076 "Generic IP component", "PrimeCell or System component"
1080 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1082 return cid3 == 0xb1 && cid2 == 0x05
1083 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1090 uint32_t correct_dbgbase;
1093 { 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" },
1094 { 0x80040000, 0x04770002, 0x3b95c02f, 0x80000000, "omap4430" },
1097 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1098 uint32_t *out_dbgbase, uint32_t *out_apid)
1103 uint32_t dbgbase, apid, idcode;
1105 /* AP address is in bits 31:24 of DP_SELECT */
1107 return ERROR_INVALID_ARGUMENTS;
1109 ap_old = dap->ap_current;
1110 dap_ap_select(dap, ap);
1112 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1113 if (retval != ERROR_OK)
1115 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1116 if (retval != ERROR_OK)
1118 retval = dap_run(dap);
1119 if (retval != ERROR_OK)
1122 /* Excavate the device ID code */
1123 struct jtag_tap *tap = dap->jtag_info->tap;
1124 while (tap != NULL) {
1125 if (tap->hasidcode) {
1126 idcode = tap->idcode;
1129 tap = tap->next_tap;
1131 if (tap == NULL || !tap->hasidcode)
1134 /* Some CPUs are messed up, so fixup if needed. */
1135 for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
1136 if (broken_cpus[i].dbgbase == dbgbase &&
1137 broken_cpus[i].apid == apid &&
1138 broken_cpus[i].idcode == idcode) {
1139 LOG_WARNING("Found broken CPU (%s), trying to fixup "
1140 "ROM Table location from 0x%08x to 0x%08x",
1141 broken_cpus[i].model, dbgbase,
1142 broken_cpus[i].correct_dbgbase);
1143 dbgbase = broken_cpus[i].correct_dbgbase;
1147 dap_ap_select(dap, ap_old);
1149 /* The asignment happens only here to prevent modification of these
1150 * values before they are certain. */
1151 *out_dbgbase = dbgbase;
1157 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1158 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1161 uint32_t romentry, entry_offset = 0, component_base, devtype;
1162 int retval = ERROR_FAIL;
1165 return ERROR_INVALID_ARGUMENTS;
1167 ap_old = dap->ap_current;
1168 dap_ap_select(dap, ap);
1172 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1173 entry_offset, &romentry);
1174 if (retval != ERROR_OK)
1177 component_base = (dbgbase & 0xFFFFF000)
1178 + (romentry & 0xFFFFF000);
1180 if (romentry & 0x1) {
1181 retval = mem_ap_read_atomic_u32(dap,
1182 (component_base & 0xfffff000) | 0xfcc,
1184 if ((devtype & 0xff) == type) {
1185 *addr = component_base;
1191 } while (romentry > 0);
1193 dap_ap_select(dap, ap_old);
1198 static int dap_info_command(struct command_context *cmd_ctx,
1199 struct adiv5_dap *dap, int ap)
1202 uint32_t dbgbase, apid;
1203 int romtable_present = 0;
1207 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1208 if (retval != ERROR_OK)
1211 ap_old = dap->ap_current;
1212 dap_ap_select(dap, ap);
1214 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1215 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1216 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1222 command_print(cmd_ctx, "\tType is JTAG-AP");
1225 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1228 command_print(cmd_ctx, "\tType is MEM-AP APB");
1231 command_print(cmd_ctx, "\tUnknown AP type");
1235 /* NOTE: a MEM-AP may have a single CoreSight component that's
1236 * not a ROM table ... or have no such components at all.
1239 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1244 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1247 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1248 if (romtable_present)
1250 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1251 uint16_t entry_offset;
1253 /* bit 16 of apid indicates a memory access port */
1255 command_print(cmd_ctx, "\tValid ROM table present");
1257 command_print(cmd_ctx, "\tROM table in legacy format");
1259 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1260 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1261 if (retval != ERROR_OK)
1263 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1264 if (retval != ERROR_OK)
1266 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1267 if (retval != ERROR_OK)
1269 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1270 if (retval != ERROR_OK)
1272 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1273 if (retval != ERROR_OK)
1275 retval = dap_run(dap);
1276 if (retval != ERROR_OK)
1279 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1280 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1284 (unsigned) cid3, (unsigned)cid2,
1285 (unsigned) cid1, (unsigned) cid0);
1287 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1289 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1290 "Dedicated debug bus.");
1292 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1296 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1297 if (retval != ERROR_OK)
1299 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1302 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1303 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1304 uint32_t component_base;
1308 component_base = (dbgbase & 0xFFFFF000)
1309 + (romentry & 0xFFFFF000);
1311 /* IDs are in last 4K section */
1314 retval = mem_ap_read_atomic_u32(dap,
1315 component_base + 0xFE0, &c_pid0);
1316 if (retval != ERROR_OK)
1319 retval = mem_ap_read_atomic_u32(dap,
1320 component_base + 0xFE4, &c_pid1);
1321 if (retval != ERROR_OK)
1324 retval = mem_ap_read_atomic_u32(dap,
1325 component_base + 0xFE8, &c_pid2);
1326 if (retval != ERROR_OK)
1329 retval = mem_ap_read_atomic_u32(dap,
1330 component_base + 0xFEC, &c_pid3);
1331 if (retval != ERROR_OK)
1334 retval = mem_ap_read_atomic_u32(dap,
1335 component_base + 0xFD0, &c_pid4);
1336 if (retval != ERROR_OK)
1340 retval = mem_ap_read_atomic_u32(dap,
1341 component_base + 0xFF0, &c_cid0);
1342 if (retval != ERROR_OK)
1345 retval = mem_ap_read_atomic_u32(dap,
1346 component_base + 0xFF4, &c_cid1);
1347 if (retval != ERROR_OK)
1350 retval = mem_ap_read_atomic_u32(dap,
1351 component_base + 0xFF8, &c_cid2);
1352 if (retval != ERROR_OK)
1355 retval = mem_ap_read_atomic_u32(dap,
1356 component_base + 0xFFC, &c_cid3);
1357 if (retval != ERROR_OK)
1362 command_print(cmd_ctx,
1363 "\t\tComponent base address 0x%" PRIx32
1364 ", start address 0x%" PRIx32,
1366 /* component may take multiple 4K pages */
1367 component_base - 0x1000*(c_pid4 >> 4));
1368 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1369 (int) (c_cid1 >> 4) & 0xf,
1370 /* See ARM IHI 0029B Table 3-3 */
1371 class_description[(c_cid1 >> 4) & 0xf]);
1373 /* CoreSight component? */
1374 if (((c_cid1 >> 4) & 0x0f) == 9) {
1377 char *major = "Reserved", *subtype = "Reserved";
1379 retval = mem_ap_read_atomic_u32(dap,
1380 (component_base & 0xfffff000) | 0xfcc,
1382 if (retval != ERROR_OK)
1384 minor = (devtype >> 4) & 0x0f;
1385 switch (devtype & 0x0f) {
1387 major = "Miscellaneous";
1393 subtype = "Validation component";
1398 major = "Trace Sink";
1412 major = "Trace Link";
1418 subtype = "Funnel, router";
1424 subtype = "FIFO, buffer";
1429 major = "Trace Source";
1435 subtype = "Processor";
1441 subtype = "Engine/Coprocessor";
1449 major = "Debug Control";
1455 subtype = "Trigger Matrix";
1458 subtype = "Debug Auth";
1463 major = "Debug Logic";
1469 subtype = "Processor";
1475 subtype = "Engine/Coprocessor";
1480 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1481 (unsigned) (devtype & 0xff),
1483 /* REVISIT also show 0xfc8 DevId */
1486 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1487 command_print(cmd_ctx,
1496 command_print(cmd_ctx,
1497 "\t\tPeripheral ID[4..0] = hex "
1498 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1499 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1500 (int) c_pid1, (int) c_pid0);
1502 /* Part number interpretations are from Cortex
1503 * core specs, the CoreSight components TRM
1504 * (ARM DDI 0314H), CoreSight System Design
1505 * Guide (ARM DGI 0012D) and ETM specs; also
1506 * from chip observation (e.g. TI SDTI).
1508 part_num = (c_pid0 & 0xff);
1509 part_num |= (c_pid1 & 0x0f) << 8;
1512 type = "Cortex-M3 NVIC";
1513 full = "(Interrupt Controller)";
1516 type = "Cortex-M3 ITM";
1517 full = "(Instrumentation Trace Module)";
1520 type = "Cortex-M3 DWT";
1521 full = "(Data Watchpoint and Trace)";
1524 type = "Cortex-M3 FBP";
1525 full = "(Flash Patch and Breakpoint)";
1528 type = "CoreSight ETM11";
1529 full = "(Embedded Trace)";
1531 // case 0x113: what?
1532 case 0x120: /* from OMAP3 memmap */
1534 full = "(System Debug Trace Interface)";
1536 case 0x343: /* from OMAP3 memmap */
1541 type = "Coresight CTI";
1542 full = "(Cross Trigger)";
1545 type = "Coresight ETB";
1546 full = "(Trace Buffer)";
1549 type = "Coresight CSTF";
1550 full = "(Trace Funnel)";
1553 type = "CoreSight ETM9";
1554 full = "(Embedded Trace)";
1557 type = "Coresight TPIU";
1558 full = "(Trace Port Interface Unit)";
1561 type = "Cortex-A8 ETM";
1562 full = "(Embedded Trace)";
1565 type = "Cortex-A8 CTI";
1566 full = "(Cross Trigger)";
1569 type = "Cortex-M3 TPIU";
1570 full = "(Trace Port Interface Unit)";
1573 type = "Cortex-M3 ETM";
1574 full = "(Embedded Trace)";
1577 type = "Cortex-R4 ETM";
1578 full = "(Embedded Trace)";
1581 type = "Cortex-A8 Debug";
1582 full = "(Debug Unit)";
1585 type = "-*- unrecognized -*-";
1589 command_print(cmd_ctx, "\t\tPart is %s %s",
1595 command_print(cmd_ctx, "\t\tComponent not present");
1597 command_print(cmd_ctx, "\t\tEnd of ROM table");
1600 } while (romentry > 0);
1604 command_print(cmd_ctx, "\tNo ROM table present");
1606 dap_ap_select(dap, ap_old);
1611 COMMAND_HANDLER(handle_dap_info_command)
1613 struct target *target = get_current_target(CMD_CTX);
1614 struct arm *arm = target_to_arm(target);
1615 struct adiv5_dap *dap = arm->dap;
1623 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1626 return ERROR_COMMAND_SYNTAX_ERROR;
1629 return dap_info_command(CMD_CTX, dap, apsel);
1632 COMMAND_HANDLER(dap_baseaddr_command)
1634 struct target *target = get_current_target(CMD_CTX);
1635 struct arm *arm = target_to_arm(target);
1636 struct adiv5_dap *dap = arm->dap;
1638 uint32_t apsel, baseaddr;
1646 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1647 /* AP address is in bits 31:24 of DP_SELECT */
1649 return ERROR_INVALID_ARGUMENTS;
1652 return ERROR_COMMAND_SYNTAX_ERROR;
1655 dap_ap_select(dap, apsel);
1657 /* NOTE: assumes we're talking to a MEM-AP, which
1658 * has a base address. There are other kinds of AP,
1659 * though they're not common for now. This should
1660 * use the ID register to verify it's a MEM-AP.
1662 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1663 if (retval != ERROR_OK)
1665 retval = dap_run(dap);
1666 if (retval != ERROR_OK)
1669 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1674 COMMAND_HANDLER(dap_memaccess_command)
1676 struct target *target = get_current_target(CMD_CTX);
1677 struct arm *arm = target_to_arm(target);
1678 struct adiv5_dap *dap = arm->dap;
1680 uint32_t memaccess_tck;
1684 memaccess_tck = dap->memaccess_tck;
1687 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1690 return ERROR_COMMAND_SYNTAX_ERROR;
1692 dap->memaccess_tck = memaccess_tck;
1694 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1695 dap->memaccess_tck);
1700 COMMAND_HANDLER(dap_apsel_command)
1702 struct target *target = get_current_target(CMD_CTX);
1703 struct arm *arm = target_to_arm(target);
1704 struct adiv5_dap *dap = arm->dap;
1706 uint32_t apsel, apid;
1714 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1715 /* AP address is in bits 31:24 of DP_SELECT */
1717 return ERROR_INVALID_ARGUMENTS;
1720 return ERROR_COMMAND_SYNTAX_ERROR;
1724 dap_ap_select(dap, apsel);
1726 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1727 if (retval != ERROR_OK)
1729 retval = dap_run(dap);
1730 if (retval != ERROR_OK)
1733 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1739 COMMAND_HANDLER(dap_apid_command)
1741 struct target *target = get_current_target(CMD_CTX);
1742 struct arm *arm = target_to_arm(target);
1743 struct adiv5_dap *dap = arm->dap;
1745 uint32_t apsel, apid;
1753 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1754 /* AP address is in bits 31:24 of DP_SELECT */
1756 return ERROR_INVALID_ARGUMENTS;
1759 return ERROR_COMMAND_SYNTAX_ERROR;
1762 dap_ap_select(dap, apsel);
1764 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1765 if (retval != ERROR_OK)
1767 retval = dap_run(dap);
1768 if (retval != ERROR_OK)
1771 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1776 static const struct command_registration dap_commands[] = {
1779 .handler = handle_dap_info_command,
1780 .mode = COMMAND_EXEC,
1781 .help = "display ROM table for MEM-AP "
1782 "(default currently selected AP)",
1783 .usage = "[ap_num]",
1787 .handler = dap_apsel_command,
1788 .mode = COMMAND_EXEC,
1789 .help = "Set the currently selected AP (default 0) "
1790 "and display the result",
1791 .usage = "[ap_num]",
1795 .handler = dap_apid_command,
1796 .mode = COMMAND_EXEC,
1797 .help = "return ID register from AP "
1798 "(default currently selected AP)",
1799 .usage = "[ap_num]",
1803 .handler = dap_baseaddr_command,
1804 .mode = COMMAND_EXEC,
1805 .help = "return debug base address from MEM-AP "
1806 "(default currently selected AP)",
1807 .usage = "[ap_num]",
1810 .name = "memaccess",
1811 .handler = dap_memaccess_command,
1812 .mode = COMMAND_EXEC,
1813 .help = "set/get number of extra tck for MEM-AP memory "
1814 "bus access [0-255]",
1815 .usage = "[cycles]",
1817 COMMAND_REGISTRATION_DONE
1820 const struct command_registration dap_command_handlers[] = {
1823 .mode = COMMAND_EXEC,
1824 .help = "DAP command group",
1825 .chain = dap_commands,
1827 COMMAND_REGISTRATION_DONE