1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
105 uint32_t select_apsel = (apsel << 24) & 0xFF000000;
107 if (select_apsel != dap->apsel)
109 dap->apsel = select_apsel;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
149 dap->ap_csw_value = csw;
151 if (tar != dap->ap_tar_value)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
157 dap->ap_tar_value = tar;
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
258 int retval = mem_ap_write_u32(dap, address, value);
260 if (retval != ERROR_OK)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 uint8_t* pBuffer = buffer;
282 /* if we have an unaligned access - reorder data */
285 for (writecount = 0; writecount < count; writecount++)
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
291 for (i = 0; i < 4; i++)
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
297 pBuffer += sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
308 /* handle unaligned data at 4k boundary */
312 dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
314 for (writecount = 0; writecount < blocksize; writecount++)
316 retval = dap_queue_ap_write(dap, AP_REG_DRW,
317 *(uint32_t *) (buffer + 4 * writecount));
318 if (retval != ERROR_OK)
322 if (dap_run(dap) == ERROR_OK)
324 wcount = wcount - blocksize;
325 address = address + 4 * blocksize;
326 buffer = buffer + 4 * blocksize;
335 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
336 /* REVISIT return the *actual* fault code */
337 return ERROR_JTAG_DEVICE_ERROR;
344 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
345 uint8_t *buffer, int count, uint32_t address)
347 int retval = ERROR_OK;
348 int wcount, blocksize, writecount, i;
356 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
357 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
359 if (wcount < blocksize)
362 /* handle unaligned data at 4k boundary */
366 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
367 writecount = blocksize;
371 nbytes = MIN((writecount << 1), 4);
375 if (mem_ap_write_buf_u16(dap, buffer,
376 nbytes, address) != ERROR_OK)
378 LOG_WARNING("Block write error address "
379 "0x%" PRIx32 ", count 0x%x",
381 return ERROR_JTAG_DEVICE_ERROR;
384 address += nbytes >> 1;
389 memcpy(&outvalue, buffer, sizeof(uint32_t));
391 for (i = 0; i < nbytes; i++)
393 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
398 memcpy(&outvalue, buffer, sizeof(uint32_t));
399 retval = dap_queue_ap_write(dap,
400 AP_REG_DRW, outvalue);
401 if (retval != ERROR_OK)
404 if (dap_run(dap) != ERROR_OK)
406 LOG_WARNING("Block write error address "
407 "0x%" PRIx32 ", count 0x%x",
409 /* REVISIT return *actual* fault code */
410 return ERROR_JTAG_DEVICE_ERROR;
414 buffer += nbytes >> 1;
415 writecount -= nbytes >> 1;
417 } while (writecount);
424 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
426 int retval = ERROR_OK;
429 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
433 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
435 memcpy(&svalue, buffer, sizeof(uint16_t));
436 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
437 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
438 if (retval != ERROR_OK)
441 retval = dap_run(dap);
442 if (retval != ERROR_OK)
453 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
454 uint8_t *buffer, int count, uint32_t address)
456 int retval = ERROR_OK;
457 int wcount, blocksize, writecount, i;
465 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
466 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
468 if (wcount < blocksize)
471 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
472 writecount = blocksize;
476 nbytes = MIN(writecount, 4);
480 if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
482 LOG_WARNING("Block write error address "
483 "0x%" PRIx32 ", count 0x%x",
485 return ERROR_JTAG_DEVICE_ERROR;
493 memcpy(&outvalue, buffer, sizeof(uint32_t));
495 for (i = 0; i < nbytes; i++)
497 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
502 memcpy(&outvalue, buffer, sizeof(uint32_t));
503 retval = dap_queue_ap_write(dap,
504 AP_REG_DRW, outvalue);
505 if (retval != ERROR_OK)
508 if (dap_run(dap) != ERROR_OK)
510 LOG_WARNING("Block write error address "
511 "0x%" PRIx32 ", count 0x%x",
513 /* REVISIT return *actual* fault code */
514 return ERROR_JTAG_DEVICE_ERROR;
519 writecount -= nbytes;
521 } while (writecount);
528 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
530 int retval = ERROR_OK;
533 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
537 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
538 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
539 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
540 if (retval != ERROR_OK)
543 retval = dap_run(dap);
544 if (retval != ERROR_OK)
555 /* FIXME don't import ... this is a temporary workaround for the
556 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
558 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
559 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
560 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
563 * Synchronously read a block of 32-bit words into a buffer
564 * @param dap The DAP connected to the MEM-AP.
565 * @param buffer where the words will be stored (in host byte order).
566 * @param count How many words to read.
567 * @param address Memory address from which to read words; all the
568 * words must be readable by the currently selected MEM-AP.
570 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
571 int count, uint32_t address)
573 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
574 uint32_t adr = address;
575 uint8_t* pBuffer = buffer;
582 /* Adjust to read blocks within boundaries aligned to the
583 * TAR autoincrement size (at least 2^10). Autoincrement
584 * mode avoids an extra per-word roundtrip to update TAR.
586 blocksize = max_tar_block_size(dap->tar_autoincr_block,
588 if (wcount < blocksize)
591 /* handle unaligned data at 4k boundary */
595 dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
598 /* FIXME remove these three calls to adi_jtag_dp_scan(),
599 * so this routine becomes transport-neutral. Be careful
600 * not to cause performance problems with JTAG; would it
601 * suffice to loop over dap_queue_ap_read(), or would that
602 * be slower when JTAG is the chosen transport?
605 /* Scan out first read */
606 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
607 DPAP_READ, 0, NULL, NULL);
608 if (retval != ERROR_OK)
610 for (readcount = 0; readcount < blocksize - 1; readcount++)
612 /* Scan out next read; scan in posted value for the
613 * previous one. Assumes read is acked "OK/FAULT",
614 * and CTRL_STAT says that meant "OK".
616 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
617 DPAP_READ, 0, buffer + 4 * readcount,
619 if (retval != ERROR_OK)
623 /* Scan in last posted value; RDBUFF has no other effect,
624 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
626 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
627 DPAP_READ, 0, buffer + 4 * readcount,
629 if (retval != ERROR_OK)
632 retval = dap_run(dap);
633 if (retval != ERROR_OK)
641 LOG_WARNING("Block read error address 0x%" PRIx32, address);
644 wcount = wcount - blocksize;
645 address += 4 * blocksize;
646 buffer += 4 * blocksize;
649 /* if we have an unaligned access - reorder data */
652 for (readcount = 0; readcount < count; readcount++)
656 memcpy(&data, pBuffer, sizeof(uint32_t));
658 for (i = 0; i < 4; i++)
660 *((uint8_t*)pBuffer) =
661 (data >> 8 * (adr & 0x3));
671 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
672 uint8_t *buffer, int count, uint32_t address)
675 int retval = ERROR_OK;
676 int wcount, blocksize, readcount, i;
684 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
685 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
686 if (wcount < blocksize)
689 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
691 /* handle unaligned data at 4k boundary */
694 readcount = blocksize;
698 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
699 if (dap_run(dap) != ERROR_OK)
701 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
702 /* REVISIT return the *actual* fault code */
703 return ERROR_JTAG_DEVICE_ERROR;
706 nbytes = MIN((readcount << 1), 4);
708 for (i = 0; i < nbytes; i++)
710 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
715 readcount -= (nbytes >> 1);
724 * Synchronously read a block of 16-bit halfwords into a buffer
725 * @param dap The DAP connected to the MEM-AP.
726 * @param buffer where the halfwords will be stored (in host byte order).
727 * @param count How many halfwords to read.
728 * @param address Memory address from which to read words; all the
729 * words must be readable by the currently selected MEM-AP.
731 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
732 int count, uint32_t address)
735 int retval = ERROR_OK;
738 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
742 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
743 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
744 if (retval != ERROR_OK)
747 retval = dap_run(dap);
748 if (retval != ERROR_OK)
753 for (i = 0; i < 2; i++)
755 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
762 uint16_t svalue = (invalue >> 8 * (address & 0x3));
763 memcpy(buffer, &svalue, sizeof(uint16_t));
773 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
774 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
776 * The solution is to arrange for a large out/in scan in this loop and
777 * and convert data afterwards.
779 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
780 uint8_t *buffer, int count, uint32_t address)
783 int retval = ERROR_OK;
784 int wcount, blocksize, readcount, i;
792 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
793 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
795 if (wcount < blocksize)
798 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
799 readcount = blocksize;
803 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
804 if (dap_run(dap) != ERROR_OK)
806 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
807 /* REVISIT return the *actual* fault code */
808 return ERROR_JTAG_DEVICE_ERROR;
811 nbytes = MIN(readcount, 4);
813 for (i = 0; i < nbytes; i++)
815 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
829 * Synchronously read a block of bytes into a buffer
830 * @param dap The DAP connected to the MEM-AP.
831 * @param buffer where the bytes will be stored.
832 * @param count How many bytes to read.
833 * @param address Memory address from which to read data; all the
834 * data must be readable by the currently selected MEM-AP.
836 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
837 int count, uint32_t address)
840 int retval = ERROR_OK;
843 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
847 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
848 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
849 retval = dap_run(dap);
850 if (retval != ERROR_OK)
853 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
862 /*--------------------------------------------------------------------------*/
865 /* FIXME don't import ... just initialize as
866 * part of DAP transport setup
868 extern const struct dap_ops jtag_dp_ops;
870 /*--------------------------------------------------------------------------*/
873 * Initialize a DAP. This sets up the power domains, prepares the DP
874 * for further use, and arranges to use AP #0 for all AP operations
875 * until dap_ap-select() changes that policy.
877 * @param dap The DAP being initialized.
879 * @todo Rename this. We also need an initialization scheme which account
880 * for SWD transports not just JTAG; that will need to address differences
881 * in layering. (JTAG is useful without any debug target; but not SWD.)
882 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
884 int ahbap_debugport_init(struct adiv5_dap *dap)
886 uint32_t idreg, romaddr, dummy;
893 /* JTAG-DP or SWJ-DP, in JTAG mode */
894 dap->ops = &jtag_dp_ops;
896 /* Default MEM-AP setup.
898 * REVISIT AP #0 may be an inappropriate default for this.
899 * Should we probe, or take a hint from the caller?
900 * Presumably we can ignore the possibility of multiple APs.
903 dap_ap_select(dap, 0);
905 /* DP initialization */
907 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
908 if (retval != ERROR_OK)
911 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
912 if (retval != ERROR_OK)
915 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
916 if (retval != ERROR_OK)
919 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
920 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
921 if (retval != ERROR_OK)
924 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
925 if (retval != ERROR_OK)
927 if ((retval = dap_run(dap)) != ERROR_OK)
930 /* Check that we have debug power domains activated */
931 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
933 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
934 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
935 if (retval != ERROR_OK)
937 if ((retval = dap_run(dap)) != ERROR_OK)
942 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
944 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
945 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
946 if (retval != ERROR_OK)
948 if ((retval = dap_run(dap)) != ERROR_OK)
953 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
954 if (retval != ERROR_OK)
956 /* With debug power on we can activate OVERRUN checking */
957 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
958 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
959 if (retval != ERROR_OK)
961 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
962 if (retval != ERROR_OK)
966 * REVISIT this isn't actually *initializing* anything in an AP,
967 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
968 * Should it? If the ROM address is valid, is this the right
969 * place to scan the table and do any topology detection?
971 retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
972 retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
974 if ((retval = dap_run(dap)) != ERROR_OK)
977 LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
978 ", Debug ROM Address 0x%" PRIx32,
979 dap->apsel, idreg, romaddr);
984 /* CID interpretation -- see ARM IHI 0029B section 3
985 * and ARM IHI 0031A table 13-3.
987 static const char *class_description[16] ={
988 "Reserved", "ROM table", "Reserved", "Reserved",
989 "Reserved", "Reserved", "Reserved", "Reserved",
990 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
991 "Reserved", "OptimoDE DESS",
992 "Generic IP component", "PrimeCell or System component"
996 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
998 return cid3 == 0xb1 && cid2 == 0x05
999 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1002 static int dap_info_command(struct command_context *cmd_ctx,
1003 struct adiv5_dap *dap, int apsel)
1006 uint32_t dbgbase, apid;
1007 int romtable_present = 0;
1011 /* AP address is in bits 31:24 of DP_SELECT */
1013 return ERROR_INVALID_ARGUMENTS;
1015 apselold = dap->apsel;
1016 dap_ap_select(dap, apsel);
1017 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1018 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1019 retval = dap_run(dap);
1020 if (retval != ERROR_OK)
1023 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1024 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1025 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1031 command_print(cmd_ctx, "\tType is JTAG-AP");
1034 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1037 command_print(cmd_ctx, "\tType is MEM-AP APB");
1040 command_print(cmd_ctx, "\tUnknown AP type");
1044 /* NOTE: a MEM-AP may have a single CoreSight component that's
1045 * not a ROM table ... or have no such components at all.
1048 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1053 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1056 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1057 if (romtable_present)
1059 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1060 uint16_t entry_offset;
1062 /* bit 16 of apid indicates a memory access port */
1064 command_print(cmd_ctx, "\tValid ROM table present");
1066 command_print(cmd_ctx, "\tROM table in legacy format");
1068 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1069 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1070 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1071 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1072 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1073 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1074 retval = dap_run(dap);
1075 if (retval != ERROR_OK)
1078 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1079 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1080 ", CID2 0x%2.2" PRIx32
1081 ", CID1 0x%2.2" PRIx32
1082 ", CID0 0x%2.2" PRIx32,
1083 cid3, cid2, cid1, cid0);
1085 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1087 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1088 "Dedicated debug bus.");
1090 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1094 mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1095 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1098 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1099 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1100 uint32_t component_start, component_base;
1104 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1105 + (int)(romentry & 0xFFFFF000));
1106 mem_ap_read_atomic_u32(dap,
1107 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1108 mem_ap_read_atomic_u32(dap,
1109 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1110 mem_ap_read_atomic_u32(dap,
1111 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1112 mem_ap_read_atomic_u32(dap,
1113 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1114 mem_ap_read_atomic_u32(dap,
1115 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1116 mem_ap_read_atomic_u32(dap,
1117 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1118 mem_ap_read_atomic_u32(dap,
1119 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1120 mem_ap_read_atomic_u32(dap,
1121 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1122 mem_ap_read_atomic_u32(dap,
1123 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1124 component_start = component_base - 0x1000*(c_pid4 >> 4);
1126 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1127 ", start address 0x%" PRIx32,
1128 component_base, component_start);
1129 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1130 (int) (c_cid1 >> 4) & 0xf,
1131 /* See ARM IHI 0029B Table 3-3 */
1132 class_description[(c_cid1 >> 4) & 0xf]);
1134 /* CoreSight component? */
1135 if (((c_cid1 >> 4) & 0x0f) == 9) {
1138 char *major = "Reserved", *subtype = "Reserved";
1140 mem_ap_read_atomic_u32(dap,
1141 (component_base & 0xfffff000) | 0xfcc,
1143 minor = (devtype >> 4) & 0x0f;
1144 switch (devtype & 0x0f) {
1146 major = "Miscellaneous";
1152 subtype = "Validation component";
1157 major = "Trace Sink";
1171 major = "Trace Link";
1177 subtype = "Funnel, router";
1183 subtype = "FIFO, buffer";
1188 major = "Trace Source";
1194 subtype = "Processor";
1200 subtype = "Engine/Coprocessor";
1208 major = "Debug Control";
1214 subtype = "Trigger Matrix";
1217 subtype = "Debug Auth";
1222 major = "Debug Logic";
1228 subtype = "Processor";
1234 subtype = "Engine/Coprocessor";
1239 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1240 (unsigned) (devtype & 0xff),
1242 /* REVISIT also show 0xfc8 DevId */
1245 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1246 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1247 ", CID2 0x%2.2" PRIx32
1248 ", CID1 0x%2.2" PRIx32
1249 ", CID0 0x%2.2" PRIx32,
1250 c_cid3, c_cid2, c_cid1, c_cid0);
1251 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1252 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1254 (int) c_pid3, (int) c_pid2,
1255 (int) c_pid1, (int) c_pid0);
1257 /* Part number interpretations are from Cortex
1258 * core specs, the CoreSight components TRM
1259 * (ARM DDI 0314H), and ETM specs; also from
1260 * chip observation (e.g. TI SDTI).
1262 part_num = c_pid0 & 0xff;
1263 part_num |= (c_pid1 & 0x0f) << 8;
1266 type = "Cortex-M3 NVIC";
1267 full = "(Interrupt Controller)";
1270 type = "Cortex-M3 ITM";
1271 full = "(Instrumentation Trace Module)";
1274 type = "Cortex-M3 DWT";
1275 full = "(Data Watchpoint and Trace)";
1278 type = "Cortex-M3 FBP";
1279 full = "(Flash Patch and Breakpoint)";
1282 type = "CoreSight ETM11";
1283 full = "(Embedded Trace)";
1285 // case 0x113: what?
1286 case 0x120: /* from OMAP3 memmap */
1288 full = "(System Debug Trace Interface)";
1290 case 0x343: /* from OMAP3 memmap */
1295 type = "Coresight CTI";
1296 full = "(Cross Trigger)";
1299 type = "Coresight ETB";
1300 full = "(Trace Buffer)";
1303 type = "Coresight CSTF";
1304 full = "(Trace Funnel)";
1307 type = "CoreSight ETM9";
1308 full = "(Embedded Trace)";
1311 type = "Coresight TPIU";
1312 full = "(Trace Port Interface Unit)";
1315 type = "Cortex-A8 ETM";
1316 full = "(Embedded Trace)";
1319 type = "Cortex-A8 CTI";
1320 full = "(Cross Trigger)";
1323 type = "Cortex-M3 TPIU";
1324 full = "(Trace Port Interface Unit)";
1327 type = "Cortex-M3 ETM";
1328 full = "(Embedded Trace)";
1331 type = "Cortex-A8 Debug";
1332 full = "(Debug Unit)";
1335 type = "-*- unrecognized -*-";
1339 command_print(cmd_ctx, "\t\tPart is %s %s",
1345 command_print(cmd_ctx, "\t\tComponent not present");
1347 command_print(cmd_ctx, "\t\tEnd of ROM table");
1350 } while (romentry > 0);
1354 command_print(cmd_ctx, "\tNo ROM table present");
1356 dap_ap_select(dap, apselold);
1361 COMMAND_HANDLER(handle_dap_info_command)
1363 struct target *target = get_current_target(CMD_CTX);
1364 struct arm *arm = target_to_arm(target);
1365 struct adiv5_dap *dap = arm->dap;
1373 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1376 return ERROR_COMMAND_SYNTAX_ERROR;
1379 return dap_info_command(CMD_CTX, dap, apsel);
1382 COMMAND_HANDLER(dap_baseaddr_command)
1384 struct target *target = get_current_target(CMD_CTX);
1385 struct arm *arm = target_to_arm(target);
1386 struct adiv5_dap *dap = arm->dap;
1388 uint32_t apsel, apselsave, baseaddr;
1391 apselsave = dap->apsel;
1397 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1398 /* AP address is in bits 31:24 of DP_SELECT */
1400 return ERROR_INVALID_ARGUMENTS;
1403 return ERROR_COMMAND_SYNTAX_ERROR;
1406 if (apselsave != apsel)
1407 dap_ap_select(dap, apsel);
1409 /* NOTE: assumes we're talking to a MEM-AP, which
1410 * has a base address. There are other kinds of AP,
1411 * though they're not common for now. This should
1412 * use the ID register to verify it's a MEM-AP.
1414 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1415 retval = dap_run(dap);
1416 if (retval != ERROR_OK)
1419 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1421 if (apselsave != apsel)
1422 dap_ap_select(dap, apselsave);
1427 COMMAND_HANDLER(dap_memaccess_command)
1429 struct target *target = get_current_target(CMD_CTX);
1430 struct arm *arm = target_to_arm(target);
1431 struct adiv5_dap *dap = arm->dap;
1433 uint32_t memaccess_tck;
1437 memaccess_tck = dap->memaccess_tck;
1440 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1445 dap->memaccess_tck = memaccess_tck;
1447 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1448 dap->memaccess_tck);
1453 COMMAND_HANDLER(dap_apsel_command)
1455 struct target *target = get_current_target(CMD_CTX);
1456 struct arm *arm = target_to_arm(target);
1457 struct adiv5_dap *dap = arm->dap;
1459 uint32_t apsel, apid;
1467 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1468 /* AP address is in bits 31:24 of DP_SELECT */
1470 return ERROR_INVALID_ARGUMENTS;
1473 return ERROR_COMMAND_SYNTAX_ERROR;
1476 dap_ap_select(dap, apsel);
1477 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1478 retval = dap_run(dap);
1479 if (retval != ERROR_OK)
1482 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1488 COMMAND_HANDLER(dap_apid_command)
1490 struct target *target = get_current_target(CMD_CTX);
1491 struct arm *arm = target_to_arm(target);
1492 struct adiv5_dap *dap = arm->dap;
1494 uint32_t apsel, apselsave, apid;
1497 apselsave = dap->apsel;
1503 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1504 /* AP address is in bits 31:24 of DP_SELECT */
1506 return ERROR_INVALID_ARGUMENTS;
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1512 if (apselsave != apsel)
1513 dap_ap_select(dap, apsel);
1515 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1516 retval = dap_run(dap);
1517 if (retval != ERROR_OK)
1520 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1521 if (apselsave != apsel)
1522 dap_ap_select(dap, apselsave);
1527 static const struct command_registration dap_commands[] = {
1530 .handler = handle_dap_info_command,
1531 .mode = COMMAND_EXEC,
1532 .help = "display ROM table for MEM-AP "
1533 "(default currently selected AP)",
1534 .usage = "[ap_num]",
1538 .handler = dap_apsel_command,
1539 .mode = COMMAND_EXEC,
1540 .help = "Set the currently selected AP (default 0) "
1541 "and display the result",
1542 .usage = "[ap_num]",
1546 .handler = dap_apid_command,
1547 .mode = COMMAND_EXEC,
1548 .help = "return ID register from AP "
1549 "(default currently selected AP)",
1550 .usage = "[ap_num]",
1554 .handler = dap_baseaddr_command,
1555 .mode = COMMAND_EXEC,
1556 .help = "return debug base address from MEM-AP "
1557 "(default currently selected AP)",
1558 .usage = "[ap_num]",
1561 .name = "memaccess",
1562 .handler = dap_memaccess_command,
1563 .mode = COMMAND_EXEC,
1564 .help = "set/get number of extra tck for MEM-AP memory "
1565 "bus access [0-255]",
1566 .usage = "[cycles]",
1568 COMMAND_REGISTRATION_DONE
1571 const struct command_registration dap_command_handlers[] = {
1574 .mode = COMMAND_EXEC,
1575 .help = "DAP command group",
1576 .chain = dap_commands,
1578 COMMAND_REGISTRATION_DONE