git.sur5r.net Git - openocd/blob - src/target/arm_adi_v5.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         int retval;
 299
 300         if (size == 4)
 301                 csw_size = CSW_32BIT;
 302         else if (size == 2)
 303                 csw_size = CSW_16BIT;
 304         else if (size == 1)
 305                 csw_size = CSW_8BIT;
 306         else
 307                 return ERROR_TARGET_UNALIGNED_ACCESS;
 308
 309         retval = dap_setup_accessport_tar(dap, address);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         while (nbytes > 0) {
 314                 uint32_t this_size = size;
 315
 316                 /* Select packed transfer if possible */
 317                 if (addrinc && dap->packed_transfers && nbytes >= 4
 318                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 319                         this_size = 4;
 320                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 321                 } else {
 322                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 323                 }
 324
 325                 if (retval != ERROR_OK)
 326                         break;
 327
 328                 /* How many source bytes each transfer will consume, and their location in the DRW,
 329                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 330                 uint32_t outvalue = 0;
 331                 switch (this_size) {
 332                 case 4:
 333                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 334                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 335                 case 2:
 336                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 337                 case 1:
 338                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 339                 }
 340
 341                 nbytes -= this_size;
 342
 343                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 344                 if (retval != ERROR_OK)
 345                         break;
 346
 347                 /* Rewrite TAR if it wrapped */
 348                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 349                         retval = dap_setup_accessport_tar(dap, address);
 350                         if (retval != ERROR_OK)
 351                                 break;
 352                 }
 353         }
 354
 355         /* REVISIT: Might want to have a queued version of this function that does not run. */
 356         if (retval == ERROR_OK)
 357                 retval = dap_run(dap);
 358
 359         if (retval != ERROR_OK) {
 360                 uint32_t tar;
 361                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 362                                 && dap_run(dap) == ERROR_OK)
 363                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 364                 else
 365                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 366         }
 367
 368         return retval;
 369 }
 370
 371 /**
 372  * Synchronous read of a block of memory, using a specific access size.
 373  *
 374  * @param dap The DAP connected to the MEM-AP.
 375  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 376  * @param size Which access size to use, in bytes. 1, 2 or 4.
 377  * @param count The number of reads to do (in size units, not bytes).
 378  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 379  * @param addrinc Whether the target address should be increased after each read or not. This
 380  *  should normally be true, except when reading from e.g. a FIFO.
 381  * @return ERROR_OK on success, otherwise an error code.
 382  */
 383 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 384                 uint32_t adr, bool addrinc)
 385 {
 386         size_t nbytes = size * count;
 387         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 388         uint32_t csw_size;
 389         uint32_t address = adr;
 390         int retval;
 391
 392         if (size == 4)
 393                 csw_size = CSW_32BIT;
 394         else if (size == 2)
 395                 csw_size = CSW_16BIT;
 396         else if (size == 1)
 397                 csw_size = CSW_8BIT;
 398         else
 399                 return ERROR_TARGET_UNALIGNED_ACCESS;
 400
 401         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 402          * over-allocation if packed transfers are going to be used, but determining the real need at
 403          * this point would be messy. */
 404         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 405         uint32_t *read_ptr = read_buf;
 406         if (read_buf == NULL) {
 407                 LOG_ERROR("Failed to allocate read buffer");
 408                 return ERROR_FAIL;
 409         }
 410
 411         retval = dap_setup_accessport_tar(dap, address);
 412         if (retval != ERROR_OK)
 413                 return retval;
 414
 415         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 416          * useful bytes it contains, and their location in the word, depends on the type of transfer
 417          * and alignment. */
 418         while (nbytes > 0) {
 419                 uint32_t this_size = size;
 420
 421                 /* Select packed transfer if possible */
 422                 if (addrinc && dap->packed_transfers && nbytes >= 4
 423                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 424                         this_size = 4;
 425                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 426                 } else {
 427                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 428                 }
 429                 if (retval != ERROR_OK)
 430                         break;
 431
 432                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 433                 if (retval != ERROR_OK)
 434                         break;
 435
 436                 nbytes -= this_size;
 437                 address += this_size;
 438
 439                 /* Rewrite TAR if it wrapped */
 440                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 441                         retval = dap_setup_accessport_tar(dap, address);
 442                         if (retval != ERROR_OK)
 443                                 break;
 444                 }
 445         }
 446
 447         if (retval == ERROR_OK)
 448                 retval = dap_run(dap);
 449
 450         /* Restore state */
 451         address = adr;
 452         nbytes = size * count;
 453         read_ptr = read_buf;
 454
 455         /* If something failed, read TAR to find out how much data was successfully read, so we can
 456          * at least give the caller what we have. */
 457         if (retval != ERROR_OK) {
 458                 uint32_t tar;
 459                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 460                                 && dap_run(dap) == ERROR_OK) {
 461                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 462                         if (nbytes > tar - address)
 463                                 nbytes = tar - address;
 464                 } else {
 465                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 466                         nbytes = 0;
 467                 }
 468         }
 469
 470         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 471         while (nbytes > 0) {
 472                 uint32_t this_size = size;
 473
 474                 if (addrinc && dap->packed_transfers && nbytes >= 4
 475                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 476                         this_size = 4;
 477                 }
 478
 479                 switch (this_size) {
 480                 case 4:
 481                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 482                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 483                 case 2:
 484                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 485                 case 1:
 486                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 487                 }
 488
 489                 read_ptr++;
 490                 nbytes -= this_size;
 491         }
 492
 493         free(read_buf);
 494         return retval;
 495 }
 496
 497 /*--------------------------------------------------------------------*/
 498 /*          Wrapping function with selection of AP                    */
 499 /*--------------------------------------------------------------------*/
 500 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 501                 uint32_t address, uint32_t *value)
 502 {
 503         dap_ap_select(swjdp, ap);
 504         return mem_ap_read_u32(swjdp, address, value);
 505 }
 506
 507 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 508                 uint32_t address, uint32_t value)
 509 {
 510         dap_ap_select(swjdp, ap);
 511         return mem_ap_write_u32(swjdp, address, value);
 512 }
 513
 514 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 515                 uint32_t address, uint32_t *value)
 516 {
 517         dap_ap_select(swjdp, ap);
 518         return mem_ap_read_atomic_u32(swjdp, address, value);
 519 }
 520
 521 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 522                 uint32_t address, uint32_t value)
 523 {
 524         dap_ap_select(swjdp, ap);
 525         return mem_ap_write_atomic_u32(swjdp, address, value);
 526 }
 527
 528 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 529                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 530 {
 531         dap_ap_select(swjdp, ap);
 532         return mem_ap_read(swjdp, buffer, size, count, address, true);
 533 }
 534
 535 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 536                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 537 {
 538         dap_ap_select(swjdp, ap);
 539         return mem_ap_write(swjdp, buffer, size, count, address, true);
 540 }
 541
 542 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 543                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 544 {
 545         dap_ap_select(swjdp, ap);
 546         return mem_ap_read(swjdp, buffer, size, count, address, false);
 547 }
 548
 549 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 550                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 551 {
 552         dap_ap_select(swjdp, ap);
 553         return mem_ap_write(swjdp, buffer, size, count, address, false);
 554 }
 555
 556 #define MDM_REG_STAT            0x00
 557 #define MDM_REG_CTRL            0x04
 558 #define MDM_REG_ID              0xfc
 559
 560 #define MDM_STAT_FMEACK         (1<<0)
 561 #define MDM_STAT_FREADY         (1<<1)
 562 #define MDM_STAT_SYSSEC         (1<<2)
 563 #define MDM_STAT_SYSRES         (1<<3)
 564 #define MDM_STAT_FMEEN          (1<<5)
 565 #define MDM_STAT_BACKDOOREN     (1<<6)
 566 #define MDM_STAT_LPEN           (1<<7)
 567 #define MDM_STAT_VLPEN          (1<<8)
 568 #define MDM_STAT_LLSMODEXIT     (1<<9)
 569 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 570 #define MDM_STAT_CORE_HALTED    (1<<16)
 571 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 572 #define MDM_STAT_CORESLEEPING   (1<<18)
 573
 574 #define MEM_CTRL_FMEIP          (1<<0)
 575 #define MEM_CTRL_DBG_DIS        (1<<1)
 576 #define MEM_CTRL_DBG_REQ        (1<<2)
 577 #define MEM_CTRL_SYS_RES_REQ    (1<<3)
 578 #define MEM_CTRL_CORE_HOLD_RES  (1<<4)
 579 #define MEM_CTRL_VLLSX_DBG_REQ  (1<<5)
 580 #define MEM_CTRL_VLLSX_DBG_ACK  (1<<6)
 581 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
 582
 583 #define MDM_ACCESS_TIMEOUT      3000 /* ms */
 584
 585 /**
 586  *
 587  */
 588 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
 589 {
 590         uint32_t val;
 591         int retval;
 592         int timeout = 0;
 593         enum reset_types jtag_reset_config = jtag_get_reset_config();
 594
 595         dap_ap_select(dap, 1);
 596
 597         /* first check mdm-ap id register */
 598         retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
 599         if (retval != ERROR_OK)
 600                 return retval;
 601         dap_run(dap);
 602
 603         if (val != 0x001C0000) {
 604                 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
 605                 dap_ap_select(dap, 0);
 606                 return ERROR_FAIL;
 607         }
 608
 609         /* read and parse status register
 610          * it's important that the device is out of
 611          * reset here
 612          */
 613         while (1) {
 614                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 615                         LOG_DEBUG("MDMAP : flash ready timeout");
 616                         return ERROR_FAIL;
 617                 }
 618                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 619                 if (retval != ERROR_OK)
 620                         return retval;
 621                 dap_run(dap);
 622
 623                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 624                 if (val & MDM_STAT_FREADY)
 625                         break;
 626                 alive_sleep(1);
 627         }
 628
 629         if ((val & MDM_STAT_SYSSEC)) {
 630                 LOG_DEBUG("MDMAP: system is secured, masserase needed");
 631
 632                 if (!(val & MDM_STAT_FMEEN))
 633                         LOG_DEBUG("MDMAP: masserase is disabled");
 634                 else {
 635                         /* we need to assert reset */
 636                         if (jtag_reset_config & RESET_HAS_SRST) {
 637                                 /* default to asserting srst */
 638                                 adapter_assert_reset();
 639                         } else {
 640                                 LOG_DEBUG("SRST not configured");
 641                                 dap_ap_select(dap, 0);
 642                                 return ERROR_FAIL;
 643                         }
 644                         timeout = 0;
 645                         while (1) {
 646                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 647                                         LOG_DEBUG("MDMAP : flash ready timeout");
 648                                         return ERROR_FAIL;
 649                                 }
 650                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
 651                                 if (retval != ERROR_OK)
 652                                         return retval;
 653                                 dap_run(dap);
 654                                 /* read status register and wait for ready */
 655                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 656                                 if (retval != ERROR_OK)
 657                                         return retval;
 658                                 dap_run(dap);
 659                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 660
 661                                 if ((val & 1))
 662                                         break;
 663                                 alive_sleep(1);
 664                         }
 665                         timeout = 0;
 666                         while (1) {
 667                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 668                                         LOG_DEBUG("MDMAP : flash ready timeout");
 669                                         return ERROR_FAIL;
 670                                 }
 671                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
 672                                 if (retval != ERROR_OK)
 673                                         return retval;
 674                                 dap_run(dap);
 675                                 /* read status register */
 676                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 677                                 if (retval != ERROR_OK)
 678                                         return retval;
 679                                 dap_run(dap);
 680                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 681                                 /* read control register and wait for ready */
 682                                 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
 683                                 if (retval != ERROR_OK)
 684                                         return retval;
 685                                 dap_run(dap);
 686                                 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
 687
 688                                 if (val == 0x00)
 689                                         break;
 690                                 alive_sleep(1);
 691                         }
 692                 }
 693         }
 694
 695         dap_ap_select(dap, 0);
 696
 697         return ERROR_OK;
 698 }
 699
 700 /** */
 701 struct dap_syssec_filter {
 702         /** */
 703         uint32_t idcode;
 704         /** */
 705         int (*dap_init)(struct adiv5_dap *dap);
 706 };
 707
 708 /** */
 709 static struct dap_syssec_filter dap_syssec_filter_data[] = {
 710         { 0x4BA00477, dap_syssec_kinetis_mdmap }
 711 };
 712
 713 /**
 714  *
 715  */
 716 int dap_syssec(struct adiv5_dap *dap)
 717 {
 718         unsigned int i;
 719         struct jtag_tap *tap;
 720
 721         for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
 722                 tap = dap->jtag_info->tap;
 723
 724                 while (tap != NULL) {
 725                         if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
 726                                 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
 727                                 dap_syssec_filter_data[i].dap_init(dap);
 728                         }
 729                         tap = tap->next_tap;
 730                 }
 731         }
 732
 733         return ERROR_OK;
 734 }
 735
 736 /*--------------------------------------------------------------------------*/
 737
 738
 739 /* FIXME don't import ... just initialize as
 740  * part of DAP transport setup
 741 */
 742 extern const struct dap_ops jtag_dp_ops;
 743
 744 /*--------------------------------------------------------------------------*/
 745
 746 /**
 747  * Initialize a DAP.  This sets up the power domains, prepares the DP
 748  * for further use, and arranges to use AP #0 for all AP operations
 749  * until dap_ap-select() changes that policy.
 750  *
 751  * @param dap The DAP being initialized.
 752  *
 753  * @todo Rename this.  We also need an initialization scheme which account
 754  * for SWD transports not just JTAG; that will need to address differences
 755  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 756  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 757  */
 758 int ahbap_debugport_init(struct adiv5_dap *dap)
 759 {
 760         uint32_t ctrlstat;
 761         int cnt = 0;
 762         int retval;
 763
 764         LOG_DEBUG(" ");
 765
 766         /* JTAG-DP or SWJ-DP, in JTAG mode
 767          * ... for SWD mode this is patched as part
 768          * of link switchover
 769          */
 770         if (!dap->ops)
 771                 dap->ops = &jtag_dp_ops;
 772
 773         /* Default MEM-AP setup.
 774          *
 775          * REVISIT AP #0 may be an inappropriate default for this.
 776          * Should we probe, or take a hint from the caller?
 777          * Presumably we can ignore the possibility of multiple APs.
 778          */
 779         dap->ap_current = !0;
 780         dap_ap_select(dap, 0);
 781
 782         /* DP initialization */
 783
 784         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 785         if (retval != ERROR_OK)
 786                 return retval;
 787
 788         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 789         if (retval != ERROR_OK)
 790                 return retval;
 791
 792         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 793         if (retval != ERROR_OK)
 794                 return retval;
 795
 796         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 797         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 798         if (retval != ERROR_OK)
 799                 return retval;
 800
 801         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 802         if (retval != ERROR_OK)
 803                 return retval;
 804         retval = dap_run(dap);
 805         if (retval != ERROR_OK)
 806                 return retval;
 807
 808         /* Check that we have debug power domains activated */
 809         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
 810                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 811                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 812                 if (retval != ERROR_OK)
 813                         return retval;
 814                 retval = dap_run(dap);
 815                 if (retval != ERROR_OK)
 816                         return retval;
 817                 alive_sleep(10);
 818         }
 819
 820         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
 821                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 822                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 823                 if (retval != ERROR_OK)
 824                         return retval;
 825                 retval = dap_run(dap);
 826                 if (retval != ERROR_OK)
 827                         return retval;
 828                 alive_sleep(10);
 829         }
 830
 831         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 832         if (retval != ERROR_OK)
 833                 return retval;
 834         /* With debug power on we can activate OVERRUN checking */
 835         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 836         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 837         if (retval != ERROR_OK)
 838                 return retval;
 839         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 840         if (retval != ERROR_OK)
 841                 return retval;
 842
 843         dap_syssec(dap);
 844
 845         /* check that we support packed transfers */
 846         uint32_t csw;
 847
 848         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 849         if (retval != ERROR_OK)
 850                 return retval;
 851
 852         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 853         if (retval != ERROR_OK)
 854                 return retval;
 855
 856         retval = dap_run(dap);
 857         if (retval != ERROR_OK)
 858                 return retval;
 859
 860         if (csw & CSW_ADDRINC_PACKED)
 861                 dap->packed_transfers = true;
 862         else
 863                 dap->packed_transfers = false;
 864
 865         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 866                         dap->packed_transfers ? "enabled" : "disabled");
 867
 868         return ERROR_OK;
 869 }
 870
 871 /* CID interpretation -- see ARM IHI 0029B section 3
 872  * and ARM IHI 0031A table 13-3.
 873  */
 874 static const char *class_description[16] = {
 875         "Reserved", "ROM table", "Reserved", "Reserved",
 876         "Reserved", "Reserved", "Reserved", "Reserved",
 877         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 878         "Reserved", "OptimoDE DESS",
 879         "Generic IP component", "PrimeCell or System component"
 880 };
 881
 882 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 883 {
 884         return cid3 == 0xb1 && cid2 == 0x05
 885                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 886 }
 887
 888 /*
 889  * This function checks the ID for each access port to find the requested Access Port type
 890  */
 891 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 892 {
 893         int ap;
 894
 895         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 896         for (ap = 0; ap <= 255; ap++) {
 897
 898                 /* read the IDR register of the Access Port */
 899                 uint32_t id_val = 0;
 900                 dap_ap_select(dap, ap);
 901
 902                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 903                 if (retval != ERROR_OK)
 904                         return retval;
 905
 906                 retval = dap_run(dap);
 907
 908                 /* IDR bits:
 909                  * 31-28 : Revision
 910                  * 27-24 : JEDEC bank (0x4 for ARM)
 911                  * 23-17 : JEDEC code (0x3B for ARM)
 912                  * 16    : Mem-AP
 913                  * 15-8  : Reserved
 914                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 915                  */
 916
 917                 /* Reading register for a non-existant AP should not cause an error,
 918                  * but just to be sure, try to continue searching if an error does happen.
 919                  */
 920                 if ((retval == ERROR_OK) &&                  /* Register read success */
 921                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 922                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 923
 924                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 925                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 926                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 927                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 928                                                 ap, id_val);
 929
 930                         *ap_num_out = ap;
 931                         return ERROR_OK;
 932                 }
 933         }
 934
 935         LOG_DEBUG("No %s found",
 936                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 937                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 938                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 939         return ERROR_FAIL;
 940 }
 941
 942 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 943                         uint32_t *out_dbgbase, uint32_t *out_apid)
 944 {
 945         uint32_t ap_old;
 946         int retval;
 947         uint32_t dbgbase, apid;
 948
 949         /* AP address is in bits 31:24 of DP_SELECT */
 950         if (ap >= 256)
 951                 return ERROR_COMMAND_SYNTAX_ERROR;
 952
 953         ap_old = dap->ap_current;
 954         dap_ap_select(dap, ap);
 955
 956         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
 957         if (retval != ERROR_OK)
 958                 return retval;
 959         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
 960         if (retval != ERROR_OK)
 961                 return retval;
 962         retval = dap_run(dap);
 963         if (retval != ERROR_OK)
 964                 return retval;
 965
 966         /* Excavate the device ID code */
 967         struct jtag_tap *tap = dap->jtag_info->tap;
 968         while (tap != NULL) {
 969                 if (tap->hasidcode)
 970                         break;
 971                 tap = tap->next_tap;
 972         }
 973         if (tap == NULL || !tap->hasidcode)
 974                 return ERROR_OK;
 975
 976         dap_ap_select(dap, ap_old);
 977
 978         /* The asignment happens only here to prevent modification of these
 979          * values before they are certain. */
 980         *out_dbgbase = dbgbase;
 981         *out_apid = apid;
 982
 983         return ERROR_OK;
 984 }
 985
 986 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 987                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
 988 {
 989         uint32_t ap_old;
 990         uint32_t romentry, entry_offset = 0, component_base, devtype;
 991         int retval = ERROR_FAIL;
 992
 993         if (ap >= 256)
 994                 return ERROR_COMMAND_SYNTAX_ERROR;
 995
 996         ap_old = dap->ap_current;
 997         dap_ap_select(dap, ap);
 998
 999         do {
1000                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1001                                                 entry_offset, &romentry);
1002                 if (retval != ERROR_OK)
1003                         return retval;
1004
1005                 component_base = (dbgbase & 0xFFFFF000)
1006                         + (romentry & 0xFFFFF000);
1007
1008                 if (romentry & 0x1) {
1009                         retval = mem_ap_read_atomic_u32(dap,
1010                                         (component_base & 0xfffff000) | 0xfcc,
1011                                         &devtype);
1012                         if (retval != ERROR_OK)
1013                                 return retval;
1014                         if ((devtype & 0xff) == type) {
1015                                 *addr = component_base;
1016                                 retval = ERROR_OK;
1017                                 break;
1018                         }
1019                 }
1020                 entry_offset += 4;
1021         } while (romentry > 0);
1022
1023         dap_ap_select(dap, ap_old);
1024
1025         return retval;
1026 }
1027
1028 static int dap_rom_display(struct command_context *cmd_ctx,
1029                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
1030 {
1031         int retval;
1032         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1033         uint16_t entry_offset;
1034         int i;
1035         char tabs[16 + 1];
1036
1037         if (depth > 16) {
1038                 command_print(cmd_ctx, "\tTables too deep");
1039                 return ERROR_FAIL;
1040         }
1041
1042         for (i = 0; i < depth; ++i)
1043                 tabs[i] = '\t';
1044         tabs[i] = '\0';
1045
1046         /* bit 16 of apid indicates a memory access port */
1047         if (dbgbase & 0x02)
1048                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
1049         else
1050                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
1051
1052         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1053         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1054         if (retval != ERROR_OK)
1055                 return retval;
1056         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1057         if (retval != ERROR_OK)
1058                 return retval;
1059         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1060         if (retval != ERROR_OK)
1061                 return retval;
1062         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1063         if (retval != ERROR_OK)
1064                 return retval;
1065         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1066         if (retval != ERROR_OK)
1067                 return retval;
1068         retval = dap_run(dap);
1069         if (retval != ERROR_OK)
1070                 return retval;
1071
1072         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1073                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1074                                 ", CID2 0x%02x"
1075                                 ", CID1 0x%02x"
1076                                 ", CID0 0x%02x",
1077                                 tabs,
1078                                 (unsigned)cid3, (unsigned)cid2,
1079                                 (unsigned)cid1, (unsigned)cid0);
1080         if (memtype & 0x01)
1081                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1082         else
1083                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1084
1085         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1086         for (entry_offset = 0; ; entry_offset += 4) {
1087                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1088                 if (retval != ERROR_OK)
1089                         return retval;
1090                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1091                                 tabs, entry_offset, romentry);
1092                 if (romentry & 0x01) {
1093                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1094                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1095                         uint32_t component_base;
1096                         unsigned part_num;
1097                         char *type, *full;
1098
1099                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1100
1101                         /* IDs are in last 4K section */
1102                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1103                         if (retval != ERROR_OK) {
1104                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1105                                               ", the corresponding core might be turned off", tabs, component_base);
1106                                 continue;
1107                         }
1108                         c_pid0 &= 0xff;
1109                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1110                         if (retval != ERROR_OK)
1111                                 return retval;
1112                         c_pid1 &= 0xff;
1113                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1114                         if (retval != ERROR_OK)
1115                                 return retval;
1116                         c_pid2 &= 0xff;
1117                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1118                         if (retval != ERROR_OK)
1119                                 return retval;
1120                         c_pid3 &= 0xff;
1121                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1122                         if (retval != ERROR_OK)
1123                                 return retval;
1124                         c_pid4 &= 0xff;
1125
1126                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1127                         if (retval != ERROR_OK)
1128                                 return retval;
1129                         c_cid0 &= 0xff;
1130                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1131                         if (retval != ERROR_OK)
1132                                 return retval;
1133                         c_cid1 &= 0xff;
1134                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1135                         if (retval != ERROR_OK)
1136                                 return retval;
1137                         c_cid2 &= 0xff;
1138                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1139                         if (retval != ERROR_OK)
1140                                 return retval;
1141                         c_cid3 &= 0xff;
1142
1143                         command_print(cmd_ctx, "\t%s\tComponent base address 0x%" PRIx32 ", "
1144                                       "start address 0x%" PRIx32, tabs, component_base,
1145                                       /* component may take multiple 4K pages */
1146                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1147                         command_print(cmd_ctx, "\t%s\tComponent class is 0x%x, %s",
1148                                         tabs, (c_cid1 >> 4) & 0xf,
1149                                         /* See ARM IHI 0029B Table 3-3 */
1150                                         class_description[(c_cid1 >> 4) & 0xf]);
1151
1152                         /* CoreSight component? */
1153                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1154                                 uint32_t devtype;
1155                                 unsigned minor;
1156                                 char *major = "Reserved", *subtype = "Reserved";
1157
1158                                 retval = mem_ap_read_atomic_u32(dap,
1159                                                 (component_base & 0xfffff000) | 0xfcc,
1160                                                 &devtype);
1161                                 if (retval != ERROR_OK)
1162                                         return retval;
1163                                 minor = (devtype >> 4) & 0x0f;
1164                                 switch (devtype & 0x0f) {
1165                                 case 0:
1166                                         major = "Miscellaneous";
1167                                         switch (minor) {
1168                                         case 0:
1169                                                 subtype = "other";
1170                                                 break;
1171                                         case 4:
1172                                                 subtype = "Validation component";
1173                                                 break;
1174                                         }
1175                                         break;
1176                                 case 1:
1177                                         major = "Trace Sink";
1178                                         switch (minor) {
1179                                         case 0:
1180                                                 subtype = "other";
1181                                                 break;
1182                                         case 1:
1183                                                 subtype = "Port";
1184                                                 break;
1185                                         case 2:
1186                                                 subtype = "Buffer";
1187                                                 break;
1188                                         }
1189                                         break;
1190                                 case 2:
1191                                         major = "Trace Link";
1192                                         switch (minor) {
1193                                         case 0:
1194                                                 subtype = "other";
1195                                                 break;
1196                                         case 1:
1197                                                 subtype = "Funnel, router";
1198                                                 break;
1199                                         case 2:
1200                                                 subtype = "Filter";
1201                                                 break;
1202                                         case 3:
1203                                                 subtype = "FIFO, buffer";
1204                                                 break;
1205                                         }
1206                                         break;
1207                                 case 3:
1208                                         major = "Trace Source";
1209                                         switch (minor) {
1210                                         case 0:
1211                                                 subtype = "other";
1212                                                 break;
1213                                         case 1:
1214                                                 subtype = "Processor";
1215                                                 break;
1216                                         case 2:
1217                                                 subtype = "DSP";
1218                                                 break;
1219                                         case 3:
1220                                                 subtype = "Engine/Coprocessor";
1221                                                 break;
1222                                         case 4:
1223                                                 subtype = "Bus";
1224                                                 break;
1225                                         }
1226                                         break;
1227                                 case 4:
1228                                         major = "Debug Control";
1229                                         switch (minor) {
1230                                         case 0:
1231                                                 subtype = "other";
1232                                                 break;
1233                                         case 1:
1234                                                 subtype = "Trigger Matrix";
1235                                                 break;
1236                                         case 2:
1237                                                 subtype = "Debug Auth";
1238                                                 break;
1239                                         }
1240                                         break;
1241                                 case 5:
1242                                         major = "Debug Logic";
1243                                         switch (minor) {
1244                                         case 0:
1245                                                 subtype = "other";
1246                                                 break;
1247                                         case 1:
1248                                                 subtype = "Processor";
1249                                                 break;
1250                                         case 2:
1251                                                 subtype = "DSP";
1252                                                 break;
1253                                         case 3:
1254                                                 subtype = "Engine/Coprocessor";
1255                                                 break;
1256                                         }
1257                                         break;
1258                                 }
1259                                 command_print(cmd_ctx, "\t%s\tType is 0x%02x, %s, %s",
1260                                                 tabs, devtype & 0xff,
1261                                                 major, subtype);
1262                                 /* REVISIT also show 0xfc8 DevId */
1263                         }
1264
1265                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1266                                 command_print(cmd_ctx,
1267                                                 "\t%s\tCID3 0%02x"
1268                                                 ", CID2 0%02x"
1269                                                 ", CID1 0%02x"
1270                                                 ", CID0 0%02x",
1271                                                 tabs,
1272                                                 (int)c_cid3,
1273                                                 (int)c_cid2,
1274                                                 (int)c_cid1,
1275                                                 (int)c_cid0);
1276                         command_print(cmd_ctx,
1277                                 "\t%s\tPeripheral ID[4..0] = hex "
1278                                 "%02x %02x %02x %02x %02x", tabs,
1279                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1280                                 (int)c_pid1, (int)c_pid0);
1281
1282                         /* Part number interpretations are from Cortex
1283                          * core specs, the CoreSight components TRM
1284                          * (ARM DDI 0314H), CoreSight System Design
1285                          * Guide (ARM DGI 0012D) and ETM specs; also
1286                          * from chip observation (e.g. TI SDTI).
1287                          */
1288                         part_num = (c_pid0 & 0xff);
1289                         part_num |= (c_pid1 & 0x0f) << 8;
1290                         switch (part_num) {
1291                         case 0x000:
1292                                 type = "Cortex-M3 NVIC";
1293                                 full = "(Interrupt Controller)";
1294                                 break;
1295                         case 0x001:
1296                                 type = "Cortex-M3 ITM";
1297                                 full = "(Instrumentation Trace Module)";
1298                                 break;
1299                         case 0x002:
1300                                 type = "Cortex-M3 DWT";
1301                                 full = "(Data Watchpoint and Trace)";
1302                                 break;
1303                         case 0x003:
1304                                 type = "Cortex-M3 FBP";
1305                                 full = "(Flash Patch and Breakpoint)";
1306                                 break;
1307                         case 0x00c:
1308                                 type = "Cortex-M4 SCS";
1309                                 full = "(System Control Space)";
1310                                 break;
1311                         case 0x00d:
1312                                 type = "CoreSight ETM11";
1313                                 full = "(Embedded Trace)";
1314                                 break;
1315                         /* case 0x113: what? */
1316                         case 0x120:             /* from OMAP3 memmap */
1317                                 type = "TI SDTI";
1318                                 full = "(System Debug Trace Interface)";
1319                                 break;
1320                         case 0x343:             /* from OMAP3 memmap */
1321                                 type = "TI DAPCTL";
1322                                 full = "";
1323                                 break;
1324                         case 0x906:
1325                                 type = "Coresight CTI";
1326                                 full = "(Cross Trigger)";
1327                                 break;
1328                         case 0x907:
1329                                 type = "Coresight ETB";
1330                                 full = "(Trace Buffer)";
1331                                 break;
1332                         case 0x908:
1333                                 type = "Coresight CSTF";
1334                                 full = "(Trace Funnel)";
1335                                 break;
1336                         case 0x910:
1337                                 type = "CoreSight ETM9";
1338                                 full = "(Embedded Trace)";
1339                                 break;
1340                         case 0x912:
1341                                 type = "Coresight TPIU";
1342                                 full = "(Trace Port Interface Unit)";
1343                                 break;
1344                         case 0x913:
1345                                 type = "Coresight ITM";
1346                                 full = "(Instrumentation Trace Macrocell)";
1347                                 break;
1348                         case 0x921:
1349                                 type = "Cortex-A8 ETM";
1350                                 full = "(Embedded Trace)";
1351                                 break;
1352                         case 0x922:
1353                                 type = "Cortex-A8 CTI";
1354                                 full = "(Cross Trigger)";
1355                                 break;
1356                         case 0x923:
1357                                 type = "Cortex-M3 TPIU";
1358                                 full = "(Trace Port Interface Unit)";
1359                                 break;
1360                         case 0x924:
1361                                 type = "Cortex-M3 ETM";
1362                                 full = "(Embedded Trace)";
1363                                 break;
1364                         case 0x925:
1365                                 type = "Cortex-M4 ETM";
1366                                 full = "(Embedded Trace)";
1367                                 break;
1368                         case 0x930:
1369                                 type = "Cortex-R4 ETM";
1370                                 full = "(Embedded Trace)";
1371                                 break;
1372                         case 0x9a1:
1373                                 type = "Cortex-M4 TPUI";
1374                                 full = "(Trace Port Interface Unit)";
1375                                 break;
1376                         case 0xc08:
1377                                 type = "Cortex-A8 Debug";
1378                                 full = "(Debug Unit)";
1379                                 break;
1380                         case 0xc09:
1381                                 type = "Cortex-A9 Debug";
1382                                 full = "(Debug Unit)";
1383                                 break;
1384                         default:
1385                                 type = "-*- unrecognized -*-";
1386                                 full = "";
1387                                 break;
1388                         }
1389                         command_print(cmd_ctx, "\t%s\tPart is %s %s",
1390                                         tabs, type, full);
1391
1392                         /* ROM Table? */
1393                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1394                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1395                                 if (retval != ERROR_OK)
1396                                         return retval;
1397                         }
1398                 } else {
1399                         if (romentry)
1400                                 command_print(cmd_ctx, "\t%s\tComponent not present", tabs);
1401                         else
1402                                 break;
1403                 }
1404         }
1405         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1406         return ERROR_OK;
1407 }
1408
1409 static int dap_info_command(struct command_context *cmd_ctx,
1410                 struct adiv5_dap *dap, int ap)
1411 {
1412         int retval;
1413         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1414         int romtable_present = 0;
1415         uint8_t mem_ap;
1416         uint32_t ap_old;
1417
1418         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1419         if (retval != ERROR_OK)
1420                 return retval;
1421
1422         ap_old = dap->ap_current;
1423         dap_ap_select(dap, ap);
1424
1425         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1426         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1427         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1428         if (apid) {
1429                 switch (apid&0x0F) {
1430                         case 0:
1431                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1432                                 break;
1433                         case 1:
1434                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1435                                 break;
1436                         case 2:
1437                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1438                                 break;
1439                         default:
1440                                 command_print(cmd_ctx, "\tUnknown AP type");
1441                                 break;
1442                 }
1443
1444                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1445                  * not a ROM table ... or have no such components at all.
1446                  */
1447                 if (mem_ap)
1448                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1449         } else
1450                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1451
1452         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1453         if (romtable_present) {
1454                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1455         } else
1456                 command_print(cmd_ctx, "\tNo ROM table present");
1457         dap_ap_select(dap, ap_old);
1458
1459         return ERROR_OK;
1460 }
1461
1462 COMMAND_HANDLER(handle_dap_info_command)
1463 {
1464         struct target *target = get_current_target(CMD_CTX);
1465         struct arm *arm = target_to_arm(target);
1466         struct adiv5_dap *dap = arm->dap;
1467         uint32_t apsel;
1468
1469         switch (CMD_ARGC) {
1470         case 0:
1471                 apsel = dap->apsel;
1472                 break;
1473         case 1:
1474                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1475                 break;
1476         default:
1477                 return ERROR_COMMAND_SYNTAX_ERROR;
1478         }
1479
1480         return dap_info_command(CMD_CTX, dap, apsel);
1481 }
1482
1483 COMMAND_HANDLER(dap_baseaddr_command)
1484 {
1485         struct target *target = get_current_target(CMD_CTX);
1486         struct arm *arm = target_to_arm(target);
1487         struct adiv5_dap *dap = arm->dap;
1488
1489         uint32_t apsel, baseaddr;
1490         int retval;
1491
1492         switch (CMD_ARGC) {
1493         case 0:
1494                 apsel = dap->apsel;
1495                 break;
1496         case 1:
1497                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1498                 /* AP address is in bits 31:24 of DP_SELECT */
1499                 if (apsel >= 256)
1500                         return ERROR_COMMAND_SYNTAX_ERROR;
1501                 break;
1502         default:
1503                 return ERROR_COMMAND_SYNTAX_ERROR;
1504         }
1505
1506         dap_ap_select(dap, apsel);
1507
1508         /* NOTE:  assumes we're talking to a MEM-AP, which
1509          * has a base address.  There are other kinds of AP,
1510          * though they're not common for now.  This should
1511          * use the ID register to verify it's a MEM-AP.
1512          */
1513         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1514         if (retval != ERROR_OK)
1515                 return retval;
1516         retval = dap_run(dap);
1517         if (retval != ERROR_OK)
1518                 return retval;
1519
1520         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1521
1522         return retval;
1523 }
1524
1525 COMMAND_HANDLER(dap_memaccess_command)
1526 {
1527         struct target *target = get_current_target(CMD_CTX);
1528         struct arm *arm = target_to_arm(target);
1529         struct adiv5_dap *dap = arm->dap;
1530
1531         uint32_t memaccess_tck;
1532
1533         switch (CMD_ARGC) {
1534         case 0:
1535                 memaccess_tck = dap->memaccess_tck;
1536                 break;
1537         case 1:
1538                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1539                 break;
1540         default:
1541                 return ERROR_COMMAND_SYNTAX_ERROR;
1542         }
1543         dap->memaccess_tck = memaccess_tck;
1544
1545         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1546                         dap->memaccess_tck);
1547
1548         return ERROR_OK;
1549 }
1550
1551 COMMAND_HANDLER(dap_apsel_command)
1552 {
1553         struct target *target = get_current_target(CMD_CTX);
1554         struct arm *arm = target_to_arm(target);
1555         struct adiv5_dap *dap = arm->dap;
1556
1557         uint32_t apsel, apid;
1558         int retval;
1559
1560         switch (CMD_ARGC) {
1561         case 0:
1562                 apsel = 0;
1563                 break;
1564         case 1:
1565                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1566                 /* AP address is in bits 31:24 of DP_SELECT */
1567                 if (apsel >= 256)
1568                         return ERROR_COMMAND_SYNTAX_ERROR;
1569                 break;
1570         default:
1571                 return ERROR_COMMAND_SYNTAX_ERROR;
1572         }
1573
1574         dap->apsel = apsel;
1575         dap_ap_select(dap, apsel);
1576
1577         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1578         if (retval != ERROR_OK)
1579                 return retval;
1580         retval = dap_run(dap);
1581         if (retval != ERROR_OK)
1582                 return retval;
1583
1584         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1585                         apsel, apid);
1586
1587         return retval;
1588 }
1589
1590 COMMAND_HANDLER(dap_apcsw_command)
1591 {
1592         struct target *target = get_current_target(CMD_CTX);
1593         struct arm *arm = target_to_arm(target);
1594         struct adiv5_dap *dap = arm->dap;
1595
1596         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1597
1598         switch (CMD_ARGC) {
1599         case 0:
1600                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1601                         (dap->apsel), apcsw);
1602                 break;
1603         case 1:
1604                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1605                 /* AP address is in bits 31:24 of DP_SELECT */
1606                 if (sprot > 1)
1607                         return ERROR_COMMAND_SYNTAX_ERROR;
1608                 if (sprot)
1609                         apcsw |= CSW_SPROT;
1610                 else
1611                         apcsw &= ~CSW_SPROT;
1612                 break;
1613         default:
1614                 return ERROR_COMMAND_SYNTAX_ERROR;
1615         }
1616         dap->apcsw[dap->apsel] = apcsw;
1617
1618         return 0;
1619 }
1620
1621
1622
1623 COMMAND_HANDLER(dap_apid_command)
1624 {
1625         struct target *target = get_current_target(CMD_CTX);
1626         struct arm *arm = target_to_arm(target);
1627         struct adiv5_dap *dap = arm->dap;
1628
1629         uint32_t apsel, apid;
1630         int retval;
1631
1632         switch (CMD_ARGC) {
1633         case 0:
1634                 apsel = dap->apsel;
1635                 break;
1636         case 1:
1637                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1638                 /* AP address is in bits 31:24 of DP_SELECT */
1639                 if (apsel >= 256)
1640                         return ERROR_COMMAND_SYNTAX_ERROR;
1641                 break;
1642         default:
1643                 return ERROR_COMMAND_SYNTAX_ERROR;
1644         }
1645
1646         dap_ap_select(dap, apsel);
1647
1648         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1649         if (retval != ERROR_OK)
1650                 return retval;
1651         retval = dap_run(dap);
1652         if (retval != ERROR_OK)
1653                 return retval;
1654
1655         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1656
1657         return retval;
1658 }
1659
1660 static const struct command_registration dap_commands[] = {
1661         {
1662                 .name = "info",
1663                 .handler = handle_dap_info_command,
1664                 .mode = COMMAND_EXEC,
1665                 .help = "display ROM table for MEM-AP "
1666                         "(default currently selected AP)",
1667                 .usage = "[ap_num]",
1668         },
1669         {
1670                 .name = "apsel",
1671                 .handler = dap_apsel_command,
1672                 .mode = COMMAND_EXEC,
1673                 .help = "Set the currently selected AP (default 0) "
1674                         "and display the result",
1675                 .usage = "[ap_num]",
1676         },
1677         {
1678                 .name = "apcsw",
1679                 .handler = dap_apcsw_command,
1680                 .mode = COMMAND_EXEC,
1681                 .help = "Set csw access bit ",
1682                 .usage = "[sprot]",
1683         },
1684
1685         {
1686                 .name = "apid",
1687                 .handler = dap_apid_command,
1688                 .mode = COMMAND_EXEC,
1689                 .help = "return ID register from AP "
1690                         "(default currently selected AP)",
1691                 .usage = "[ap_num]",
1692         },
1693         {
1694                 .name = "baseaddr",
1695                 .handler = dap_baseaddr_command,
1696                 .mode = COMMAND_EXEC,
1697                 .help = "return debug base address from MEM-AP "
1698                         "(default currently selected AP)",
1699                 .usage = "[ap_num]",
1700         },
1701         {
1702                 .name = "memaccess",
1703                 .handler = dap_memaccess_command,
1704                 .mode = COMMAND_EXEC,
1705                 .help = "set/get number of extra tck for MEM-AP memory "
1706                         "bus access [0-255]",
1707                 .usage = "[cycles]",
1708         },
1709         COMMAND_REGISTRATION_DONE
1710 };
1711
1712 const struct command_registration dap_command_handlers[] = {
1713         {
1714                 .name = "dap",
1715                 .mode = COMMAND_EXEC,
1716                 .help = "DAP command group",
1717                 .usage = "",
1718                 .chain = dap_commands,
1719         },
1720         COMMAND_REGISTRATION_DONE
1721 };