1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
30 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
32 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
33 * Cortex-M3(tm) TRM, ARM DDI 0337C *
35 ***************************************************************************/
41 #include "replacements.h"
43 #include "arm_adi_v5.h"
46 #include "time_support.h"
51 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
52 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
53 * result checking until swjdp_end_transaction()
54 * This must be done before using or deallocating any return variables.
55 * swjdp->trans_mode == TRANS_MODE_ATOMIC
56 * All reads and writes to the AHB bus are checked for valid completion, and return values
57 * are immediatley available.
60 /***************************************************************************
62 * DPACC and APACC scanchain access through JTAG-DP *
64 ***************************************************************************/
66 /* Scan out and in from target ordered u8 buffers */
67 int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
69 scan_field_t fields[2];
72 jtag_add_end_state(TAP_IDLE);
73 arm_jtag_set_instr(jtag_info, instr, NULL);
75 fields[0].tap = jtag_info->tap;
76 fields[0].num_bits = 3;
77 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
78 fields[0].out_value = &out_addr_buf;
80 fields[0].in_value = ack;
83 fields[0].in_handler = NULL;
86 fields[1].tap = jtag_info->tap;
87 fields[1].num_bits = 32;
88 fields[1].out_value = outvalue;
90 fields[1].in_value = invalue;
91 fields[1].in_handler = NULL;
96 jtag_add_dr_scan(2, fields, TAP_INVALID);
101 /* Scan out and in from host ordered u32 variables */
102 int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
104 scan_field_t fields[2];
108 jtag_add_end_state(TAP_IDLE);
109 arm_jtag_set_instr(jtag_info, instr, NULL);
111 fields[0].tap = jtag_info->tap;
112 fields[0].num_bits = 3;
113 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
114 fields[0].out_value = &out_addr_buf;
116 fields[0].in_value = ack;
119 fields[0].in_handler = NULL;
122 fields[1].tap = jtag_info->tap;
123 fields[1].num_bits = 32;
124 buf_set_u32(out_value_buf, 0, 32, outvalue);
125 fields[1].out_value = out_value_buf;
127 fields[1].in_value = NULL;
130 fields[1].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
131 fields[1].in_handler_priv = invalue;
135 fields[1].in_handler = NULL;
141 jtag_add_dr_scan(2, fields, TAP_INVALID);
146 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
147 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
149 adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
150 if ((RnW == DPAP_READ) && (invalue != NULL))
152 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
155 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
156 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
158 return swjdp_transaction_endcheck(swjdp);
164 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
166 adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
167 if ((RnW==DPAP_READ) && (invalue != NULL))
169 adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
172 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
173 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
175 return swjdp_transaction_endcheck(swjdp);
181 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
186 /* too expensive to call keep_alive() here */
189 /* Danger!!!! BROKEN!!!! */
190 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
191 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
192 R956 introduced the check on return value here and now Michael Schwingen reports
193 that this code no longer works....
195 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
197 if ((retval=jtag_execute_queue())!=ERROR_OK)
199 LOG_ERROR("BUG: Why does this fail the first time????");
201 /* Why??? second time it works??? */
204 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
205 if ((retval=jtag_execute_queue())!=ERROR_OK)
208 swjdp->ack = swjdp->ack & 0x7;
212 long long then=timeval_ms();
213 while (swjdp->ack != 2)
217 if ((timeval_ms()-then) > 1000)
219 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
220 return ERROR_JTAG_DEVICE_ERROR;
225 LOG_WARNING("Invalid ACK in SWJDP transaction");
226 return ERROR_JTAG_DEVICE_ERROR;
229 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
230 if ((retval=jtag_execute_queue())!=ERROR_OK)
232 swjdp->ack = swjdp->ack & 0x7;
236 /* common code path avoids fn to timeval_ms() */
239 /* Check for STICKYERR and STICKYORUN */
240 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
242 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
243 /* Check power to debug regions */
244 if ((ctrlstat & 0xf0000000) != 0xf0000000)
246 ahbap_debugport_init(swjdp);
250 u32 mem_ap_csw, mem_ap_tar;
252 /* Print information about last AHBAP access */
253 LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
254 if (ctrlstat & SSTICKYORUN)
255 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
257 if (ctrlstat & SSTICKYERR)
258 LOG_ERROR("SWJ-DP STICKY ERROR");
260 /* Clear Sticky Error Bits */
261 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
262 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
263 if ((retval=jtag_execute_queue())!=ERROR_OK)
266 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
268 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
269 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
270 if ((retval=jtag_execute_queue())!=ERROR_OK)
272 LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
275 if ((retval=jtag_execute_queue())!=ERROR_OK)
277 return ERROR_JTAG_DEVICE_ERROR;
283 /***************************************************************************
285 * DP and MEM-AP register access through APACC and DPACC *
287 ***************************************************************************/
289 int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
291 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
294 int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
296 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
299 int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
302 select = (apsel<<24) & 0xFF000000;
304 if (select != swjdp->apsel)
306 swjdp->apsel = select;
307 /* Switchin AP invalidates cached values */
308 swjdp->dp_select_value = -1;
309 swjdp->ap_csw_value = -1;
310 swjdp->ap_tar_value = -1;
316 int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
319 select = (ap_reg & 0x000000F0);
321 if (select != swjdp->dp_select_value)
323 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
324 swjdp->dp_select_value = select;
330 int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
332 dap_dp_bankselect(swjdp, reg_addr);
333 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
338 int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
340 dap_dp_bankselect(swjdp, reg_addr);
341 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
345 int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
349 buf_set_u32(out_value_buf, 0, 32, value);
350 dap_dp_bankselect(swjdp, reg_addr);
351 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
356 int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
358 dap_dp_bankselect(swjdp, reg_addr);
359 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
364 /***************************************************************************
366 * AHB-AP access to memory and system registers on AHB bus *
368 ***************************************************************************/
370 int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
372 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
373 if (csw != swjdp->ap_csw_value)
375 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
376 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
377 swjdp->ap_csw_value = csw;
379 if (tar != swjdp->ap_tar_value)
381 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
382 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
383 swjdp->ap_tar_value = tar;
385 if (csw & CSW_ADDRINC_MASK)
387 /* Do not cache TAR value when autoincrementing */
388 swjdp->ap_tar_value = -1;
393 /*****************************************************************************
395 * mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
397 * Read a u32 value from memory or system register *
398 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
399 * but with less overhead *
400 *****************************************************************************/
401 int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
403 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
405 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
406 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
411 int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
413 mem_ap_read_u32(swjdp, address, value);
415 return swjdp_transaction_endcheck(swjdp);
418 /*****************************************************************************
420 * mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
422 * Write a u32 value to memory or memory mapped register *
424 *****************************************************************************/
425 int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
427 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
429 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
430 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
435 int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
437 mem_ap_write_u32(swjdp, address, value);
439 return swjdp_transaction_endcheck(swjdp);
442 /*****************************************************************************
444 * mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
446 * Write a buffer in target order (little endian) *
448 *****************************************************************************/
449 int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
452 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
454 u8* pBuffer = buffer;
456 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
461 /* if we have an unaligned access - reorder data */
464 for (writecount = 0; writecount < count; writecount++)
467 outvalue = *((u32*)pBuffer);
469 for (i = 0; i < 4; i++ )
471 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
481 /* Adjust to write blocks within 4K aligned boundaries */
482 blocksize = (0x1000 - (0xFFF & address)) >> 2;
483 if (wcount < blocksize)
486 /* handle unaligned data at 4k boundary */
490 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
492 for (writecount = 0; writecount < blocksize; writecount++)
494 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
497 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
499 wcount = wcount - blocksize;
500 address = address + 4 * blocksize;
501 buffer = buffer + 4 * blocksize;
510 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
511 return ERROR_JTAG_DEVICE_ERROR;
518 int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
521 int retval = ERROR_OK;
522 int wcount, blocksize, writecount, i;
524 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
532 /* Adjust to read within 4K block boundaries */
533 blocksize = (0x1000 - (0xFFF & address)) >> 1;
535 if (wcount < blocksize)
538 /* handle unaligned data at 4k boundary */
542 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
543 writecount = blocksize;
547 nbytes = MIN((writecount << 1), 4);
551 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
553 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
554 return ERROR_JTAG_DEVICE_ERROR;
557 address += nbytes >> 1;
561 outvalue = *((u32*)buffer);
563 for (i = 0; i < nbytes; i++ )
565 *((u8*)buffer + (address & 0x3)) = outvalue;
570 outvalue = *((u32*)buffer);
571 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
572 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
574 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
575 return ERROR_JTAG_DEVICE_ERROR;
579 buffer += nbytes >> 1;
580 writecount -= nbytes >> 1;
582 } while (writecount);
589 int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
592 int retval = ERROR_OK;
595 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
597 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
601 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
602 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
603 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
604 retval = swjdp_transaction_endcheck(swjdp);
613 int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
616 int retval = ERROR_OK;
617 int wcount, blocksize, writecount, i;
619 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
627 /* Adjust to read within 4K block boundaries */
628 blocksize = (0x1000 - (0xFFF & address));
630 if (wcount < blocksize)
633 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
634 writecount = blocksize;
638 nbytes = MIN(writecount, 4);
642 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
644 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
645 return ERROR_JTAG_DEVICE_ERROR;
652 outvalue = *((u32*)buffer);
654 for (i = 0; i < nbytes; i++ )
656 *((u8*)buffer + (address & 0x3)) = outvalue;
661 outvalue = *((u32*)buffer);
662 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
663 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
665 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
666 return ERROR_JTAG_DEVICE_ERROR;
671 writecount -= nbytes;
673 } while (writecount);
680 int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
683 int retval = ERROR_OK;
686 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
688 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
692 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
693 outvalue = *((u8*)buffer) << 8 * (address & 0x3);
694 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
695 retval = swjdp_transaction_endcheck(swjdp);
704 /*********************************************************************************
706 * mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
708 * Read block fast in target order (little endian) into a buffer *
710 **********************************************************************************/
711 int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
713 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
715 u8* pBuffer = buffer;
717 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
724 /* Adjust to read within 4K block boundaries */
725 blocksize = (0x1000 - (0xFFF & address)) >> 2;
726 if (wcount < blocksize)
729 /* handle unaligned data at 4k boundary */
733 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
735 /* Scan out first read */
736 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
737 for (readcount = 0; readcount < blocksize - 1; readcount++)
739 /* Scan out read instruction and scan in previous value */
740 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
743 /* Scan in last value */
744 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
745 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
747 wcount = wcount - blocksize;
748 address += 4 * blocksize;
749 buffer += 4 * blocksize;
758 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
759 return ERROR_JTAG_DEVICE_ERROR;
763 /* if we have an unaligned access - reorder data */
766 for (readcount = 0; readcount < count; readcount++)
769 u32 data = *((u32*)pBuffer);
771 for (i = 0; i < 4; i++ )
773 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
783 int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
786 int retval = ERROR_OK;
787 int wcount, blocksize, readcount, i;
789 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
797 /* Adjust to read within 4K block boundaries */
798 blocksize = (0x1000 - (0xFFF & address)) >> 1;
799 if (wcount < blocksize)
802 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
804 /* handle unaligned data at 4k boundary */
807 readcount = blocksize;
811 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
812 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
814 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
815 return ERROR_JTAG_DEVICE_ERROR;
818 nbytes = MIN((readcount << 1), 4);
820 for (i = 0; i < nbytes; i++ )
822 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
827 readcount -= (nbytes >> 1);
835 int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
838 int retval = ERROR_OK;
841 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
843 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
847 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
848 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
849 retval = swjdp_transaction_endcheck(swjdp);
852 for (i = 0; i < 2; i++ )
854 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
861 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
871 int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
874 int retval = ERROR_OK;
875 int wcount, blocksize, readcount, i;
877 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
885 /* Adjust to read within 4K block boundaries */
886 blocksize = (0x1000 - (0xFFF & address));
888 if (wcount < blocksize)
891 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
892 readcount = blocksize;
896 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
897 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
899 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
900 return ERROR_JTAG_DEVICE_ERROR;
903 nbytes = MIN(readcount, 4);
905 for (i = 0; i < nbytes; i++ )
907 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
920 int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
923 int retval = ERROR_OK;
926 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
928 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
932 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
933 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
934 retval = swjdp_transaction_endcheck(swjdp);
935 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
944 int ahbap_debugport_init(swjdp_common_t *swjdp)
946 u32 idreg, romaddr, dummy;
954 swjdp->ap_csw_value = -1;
955 swjdp->ap_tar_value = -1;
956 swjdp->trans_mode = TRANS_MODE_ATOMIC;
957 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
958 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
959 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
961 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
963 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
964 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
965 if ((retval=jtag_execute_queue())!=ERROR_OK)
968 /* Check that we have debug power domains activated */
969 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
971 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
972 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
973 if ((retval=jtag_execute_queue())!=ERROR_OK)
978 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
980 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
981 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
982 if ((retval=jtag_execute_queue())!=ERROR_OK)
987 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
988 /* With debug power on we can activate OVERRUN checking */
989 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
990 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
991 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
993 dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
994 dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
996 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
1002 char * class_description[16] ={
1004 "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
1005 "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
1007 int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
1011 int romtable_present = 0;
1015 apselold = swjdp->apsel;
1016 dap_ap_select(swjdp, apsel);
1017 dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
1018 dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
1019 swjdp_transaction_endcheck(swjdp);
1020 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1021 mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
1022 command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
1028 command_print(cmd_ctx, "\tType is jtag-ap");
1031 command_print(cmd_ctx, "\tType is mem-ap AHB");
1034 command_print(cmd_ctx, "\tType is mem-ap APB");
1037 command_print(cmd_ctx, "\tUnknown AP-type");
1040 command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
1044 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1047 romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
1048 if (romtable_present)
1050 u32 cid0,cid1,cid2,cid3,memtype,romentry;
1052 /* bit 16 of apid indicates a memory access port */
1055 command_print(cmd_ctx, "\tValid ROM table present");
1059 command_print(cmd_ctx, "\tROM table in legacy format" );
1061 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1062 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
1063 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
1064 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
1065 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
1066 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
1067 swjdp_transaction_endcheck(swjdp);
1068 command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
1071 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1075 command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
1078 /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
1082 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
1083 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
1086 u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
1087 u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
1088 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
1089 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
1090 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
1091 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
1092 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
1093 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
1094 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
1095 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
1096 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
1097 component_start = component_base - 0x1000*(c_pid4>>4);
1098 command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
1099 command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
1100 command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
1101 command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
1102 /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
1107 command_print(cmd_ctx, "\t\tComponent not present");
1109 command_print(cmd_ctx, "\t\tEnd of ROM table");
1112 } while (romentry>0);
1116 command_print(cmd_ctx, "\tNo ROM table present");
1118 dap_ap_select(swjdp, apselold);