1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
30 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
32 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
33 * Cortex-M3(tm) TRM, ARM DDI 0337C *
35 ***************************************************************************/
41 #include "replacements.h"
43 #include "arm_adi_v5.h"
46 #include "time_support.h"
52 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
53 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
54 * result checking until swjdp_end_transaction()
55 * This must be done before using or deallocating any return variables.
56 * swjdp->trans_mode == TRANS_MODE_ATOMIC
57 * All reads and writes to the AHB bus are checked for valid completion, and return values
58 * are immediatley available.
61 /***************************************************************************
63 * DPACC and APACC scanchain access through JTAG-DP *
65 ***************************************************************************/
67 /* Scan out and in from target ordered u8 buffers */
68 int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
70 scan_field_t fields[2];
73 jtag_add_end_state(TAP_IDLE);
74 arm_jtag_set_instr(jtag_info, instr, NULL);
76 fields[0].tap = jtag_info->tap;
77 fields[0].num_bits = 3;
78 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
79 fields[0].out_value = &out_addr_buf;
81 fields[0].in_value = ack;
84 fields[0].in_handler = NULL;
87 fields[1].tap = jtag_info->tap;
88 fields[1].num_bits = 32;
89 fields[1].out_value = outvalue;
91 fields[1].in_value = invalue;
92 fields[1].in_handler = NULL;
97 jtag_add_dr_scan(2, fields, TAP_INVALID);
102 /* Scan out and in from host ordered u32 variables */
103 int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
105 scan_field_t fields[2];
109 jtag_add_end_state(TAP_IDLE);
110 arm_jtag_set_instr(jtag_info, instr, NULL);
112 fields[0].tap = jtag_info->tap;
113 fields[0].num_bits = 3;
114 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
115 fields[0].out_value = &out_addr_buf;
117 fields[0].in_value = ack;
120 fields[0].in_handler = NULL;
123 fields[1].tap = jtag_info->tap;
124 fields[1].num_bits = 32;
125 buf_set_u32(out_value_buf, 0, 32, outvalue);
126 fields[1].out_value = out_value_buf;
128 fields[1].in_value = NULL;
131 fields[1].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
132 fields[1].in_handler_priv = invalue;
136 fields[1].in_handler = NULL;
142 jtag_add_dr_scan(2, fields, TAP_INVALID);
147 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
148 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
150 adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
151 if ((RnW == DPAP_READ) && (invalue != NULL))
153 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
156 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
157 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
159 return swjdp_transaction_endcheck(swjdp);
165 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
167 adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
168 if ((RnW==DPAP_READ) && (invalue != NULL))
170 adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
173 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
174 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
176 return swjdp_transaction_endcheck(swjdp);
182 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
187 /* too expensive to call keep_alive() here */
190 /* Danger!!!! BROKEN!!!! */
191 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
192 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
193 R956 introduced the check on return value here and now Michael Schwingen reports
194 that this code no longer works....
196 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
198 if ((retval=jtag_execute_queue())!=ERROR_OK)
200 LOG_ERROR("BUG: Why does this fail the first time????");
202 /* Why??? second time it works??? */
205 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
206 if ((retval=jtag_execute_queue())!=ERROR_OK)
209 swjdp->ack = swjdp->ack & 0x7;
213 long long then=timeval_ms();
214 while (swjdp->ack != 2)
218 if ((timeval_ms()-then) > 1000)
220 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
221 return ERROR_JTAG_DEVICE_ERROR;
226 LOG_WARNING("Invalid ACK in SWJDP transaction");
227 return ERROR_JTAG_DEVICE_ERROR;
230 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
231 if ((retval=jtag_execute_queue())!=ERROR_OK)
233 swjdp->ack = swjdp->ack & 0x7;
237 /* common code path avoids fn to timeval_ms() */
240 /* Check for STICKYERR and STICKYORUN */
241 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
243 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
244 /* Check power to debug regions */
245 if ((ctrlstat & 0xf0000000) != 0xf0000000)
247 ahbap_debugport_init(swjdp);
251 u32 mem_ap_csw, mem_ap_tar;
253 /* Print information about last AHBAP access */
254 LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
255 if (ctrlstat & SSTICKYORUN)
256 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
258 if (ctrlstat & SSTICKYERR)
259 LOG_ERROR("SWJ-DP STICKY ERROR");
261 /* Clear Sticky Error Bits */
262 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
263 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
264 if ((retval=jtag_execute_queue())!=ERROR_OK)
267 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
269 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
270 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
271 if ((retval=jtag_execute_queue())!=ERROR_OK)
273 LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
276 if ((retval=jtag_execute_queue())!=ERROR_OK)
278 return ERROR_JTAG_DEVICE_ERROR;
284 /***************************************************************************
286 * DP and MEM-AP register access through APACC and DPACC *
288 ***************************************************************************/
290 int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
292 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
295 int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
297 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
300 int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
303 select = (apsel<<24) & 0xFF000000;
305 if (select != swjdp->apsel)
307 swjdp->apsel = select;
308 /* Switchin AP invalidates cached values */
309 swjdp->dp_select_value = -1;
310 swjdp->ap_csw_value = -1;
311 swjdp->ap_tar_value = -1;
317 int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
320 select = (ap_reg & 0x000000F0);
322 if (select != swjdp->dp_select_value)
324 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
325 swjdp->dp_select_value = select;
331 int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
333 dap_dp_bankselect(swjdp, reg_addr);
334 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
339 int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
341 dap_dp_bankselect(swjdp, reg_addr);
342 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
346 int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
350 buf_set_u32(out_value_buf, 0, 32, value);
351 dap_dp_bankselect(swjdp, reg_addr);
352 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
357 int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
359 dap_dp_bankselect(swjdp, reg_addr);
360 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
365 /***************************************************************************
367 * AHB-AP access to memory and system registers on AHB bus *
369 ***************************************************************************/
371 int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
373 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
374 if (csw != swjdp->ap_csw_value)
376 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
377 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
378 swjdp->ap_csw_value = csw;
380 if (tar != swjdp->ap_tar_value)
382 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
383 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
384 swjdp->ap_tar_value = tar;
386 if (csw & CSW_ADDRINC_MASK)
388 /* Do not cache TAR value when autoincrementing */
389 swjdp->ap_tar_value = -1;
394 /*****************************************************************************
396 * mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
398 * Read a u32 value from memory or system register *
399 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
400 * but with less overhead *
401 *****************************************************************************/
402 int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
404 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
406 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
407 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
412 int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
414 mem_ap_read_u32(swjdp, address, value);
416 return swjdp_transaction_endcheck(swjdp);
419 /*****************************************************************************
421 * mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
423 * Write a u32 value to memory or memory mapped register *
425 *****************************************************************************/
426 int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
428 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
430 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
431 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
436 int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
438 mem_ap_write_u32(swjdp, address, value);
440 return swjdp_transaction_endcheck(swjdp);
443 /*****************************************************************************
445 * mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
447 * Write a buffer in target order (little endian) *
449 *****************************************************************************/
450 int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
452 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
454 u8* pBuffer = buffer;
456 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
461 /* if we have an unaligned access - reorder data */
464 for (writecount = 0; writecount < count; writecount++)
468 memcpy(&outvalue, pBuffer, sizeof(u32));
470 for (i = 0; i < 4; i++ )
472 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
476 pBuffer += sizeof(u32);
482 /* Adjust to write blocks within 4K aligned boundaries */
483 blocksize = (0x1000 - (0xFFF & address)) >> 2;
484 if (wcount < blocksize)
487 /* handle unaligned data at 4k boundary */
491 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
493 for (writecount = 0; writecount < blocksize; writecount++)
495 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
498 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
500 wcount = wcount - blocksize;
501 address = address + 4 * blocksize;
502 buffer = buffer + 4 * blocksize;
511 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
512 return ERROR_JTAG_DEVICE_ERROR;
519 int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
521 int retval = ERROR_OK;
522 int wcount, blocksize, writecount, i;
524 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
532 /* Adjust to read within 4K block boundaries */
533 blocksize = (0x1000 - (0xFFF & address)) >> 1;
535 if (wcount < blocksize)
538 /* handle unaligned data at 4k boundary */
542 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
543 writecount = blocksize;
547 nbytes = MIN((writecount << 1), 4);
551 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
553 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
554 return ERROR_JTAG_DEVICE_ERROR;
557 address += nbytes >> 1;
562 memcpy(&outvalue, buffer, sizeof(u32));
564 for (i = 0; i < nbytes; i++ )
566 *((u8*)buffer + (address & 0x3)) = outvalue;
571 memcpy(&outvalue, buffer, sizeof(u32));
572 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
573 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
575 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
576 return ERROR_JTAG_DEVICE_ERROR;
580 buffer += nbytes >> 1;
581 writecount -= nbytes >> 1;
583 } while (writecount);
590 int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
592 int retval = ERROR_OK;
595 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
597 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
601 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
603 memcpy(&svalue, buffer, sizeof(u16));
604 u32 outvalue = (u32)svalue << 8 * (address & 0x3);
605 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
606 retval = swjdp_transaction_endcheck(swjdp);
615 int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
617 int retval = ERROR_OK;
618 int wcount, blocksize, writecount, i;
620 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
628 /* Adjust to read within 4K block boundaries */
629 blocksize = (0x1000 - (0xFFF & address));
631 if (wcount < blocksize)
634 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
635 writecount = blocksize;
639 nbytes = MIN(writecount, 4);
643 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
645 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
646 return ERROR_JTAG_DEVICE_ERROR;
654 memcpy(&outvalue, buffer, sizeof(u32));
656 for (i = 0; i < nbytes; i++ )
658 *((u8*)buffer + (address & 0x3)) = outvalue;
663 memcpy(&outvalue, buffer, sizeof(u32));
664 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
665 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
667 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
668 return ERROR_JTAG_DEVICE_ERROR;
673 writecount -= nbytes;
675 } while (writecount);
682 int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
684 int retval = ERROR_OK;
687 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
689 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
693 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
694 u32 outvalue = (u32)*buffer << 8 * (address & 0x3);
695 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
696 retval = swjdp_transaction_endcheck(swjdp);
705 /*********************************************************************************
707 * mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
709 * Read block fast in target order (little endian) into a buffer *
711 **********************************************************************************/
712 int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
714 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
716 u8* pBuffer = buffer;
718 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
725 /* Adjust to read within 4K block boundaries */
726 blocksize = (0x1000 - (0xFFF & address)) >> 2;
727 if (wcount < blocksize)
730 /* handle unaligned data at 4k boundary */
734 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
736 /* Scan out first read */
737 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
738 for (readcount = 0; readcount < blocksize - 1; readcount++)
740 /* Scan out read instruction and scan in previous value */
741 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
744 /* Scan in last value */
745 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
746 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
748 wcount = wcount - blocksize;
749 address += 4 * blocksize;
750 buffer += 4 * blocksize;
759 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
760 return ERROR_JTAG_DEVICE_ERROR;
764 /* if we have an unaligned access - reorder data */
767 for (readcount = 0; readcount < count; readcount++)
771 memcpy(&data, pBuffer, sizeof(u32));
773 for (i = 0; i < 4; i++ )
775 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
785 int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
788 int retval = ERROR_OK;
789 int wcount, blocksize, readcount, i;
791 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
799 /* Adjust to read within 4K block boundaries */
800 blocksize = (0x1000 - (0xFFF & address)) >> 1;
801 if (wcount < blocksize)
804 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
806 /* handle unaligned data at 4k boundary */
809 readcount = blocksize;
813 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
814 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
816 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
817 return ERROR_JTAG_DEVICE_ERROR;
820 nbytes = MIN((readcount << 1), 4);
822 for (i = 0; i < nbytes; i++ )
824 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
829 readcount -= (nbytes >> 1);
837 int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
840 int retval = ERROR_OK;
843 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
845 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
849 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
850 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
851 retval = swjdp_transaction_endcheck(swjdp);
854 for (i = 0; i < 2; i++ )
856 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
863 u16 svalue = (invalue >> 8 * (address & 0x3));
864 memcpy(buffer, &svalue, sizeof(u16));
874 int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
877 int retval = ERROR_OK;
878 int wcount, blocksize, readcount, i;
880 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
888 /* Adjust to read within 4K block boundaries */
889 blocksize = (0x1000 - (0xFFF & address));
891 if (wcount < blocksize)
894 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
895 readcount = blocksize;
899 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
900 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
902 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
903 return ERROR_JTAG_DEVICE_ERROR;
906 nbytes = MIN(readcount, 4);
908 for (i = 0; i < nbytes; i++ )
910 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
923 int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
926 int retval = ERROR_OK;
929 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
931 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
935 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
936 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
937 retval = swjdp_transaction_endcheck(swjdp);
938 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
947 int ahbap_debugport_init(swjdp_common_t *swjdp)
949 u32 idreg, romaddr, dummy;
957 swjdp->ap_csw_value = -1;
958 swjdp->ap_tar_value = -1;
959 swjdp->trans_mode = TRANS_MODE_ATOMIC;
960 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
961 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
962 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
964 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
966 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
967 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
968 if ((retval=jtag_execute_queue())!=ERROR_OK)
971 /* Check that we have debug power domains activated */
972 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
974 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
975 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
976 if ((retval=jtag_execute_queue())!=ERROR_OK)
981 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
983 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
984 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
985 if ((retval=jtag_execute_queue())!=ERROR_OK)
990 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
991 /* With debug power on we can activate OVERRUN checking */
992 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
993 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
994 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
996 dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
997 dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
999 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
1005 char * class_description[16] ={
1007 "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
1008 "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
1010 int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
1014 int romtable_present = 0;
1018 apselold = swjdp->apsel;
1019 dap_ap_select(swjdp, apsel);
1020 dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
1021 dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
1022 swjdp_transaction_endcheck(swjdp);
1023 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1024 mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
1025 command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
1031 command_print(cmd_ctx, "\tType is jtag-ap");
1034 command_print(cmd_ctx, "\tType is mem-ap AHB");
1037 command_print(cmd_ctx, "\tType is mem-ap APB");
1040 command_print(cmd_ctx, "\tUnknown AP-type");
1043 command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
1047 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1050 romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
1051 if (romtable_present)
1053 u32 cid0,cid1,cid2,cid3,memtype,romentry;
1055 /* bit 16 of apid indicates a memory access port */
1058 command_print(cmd_ctx, "\tValid ROM table present");
1062 command_print(cmd_ctx, "\tROM table in legacy format" );
1064 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1065 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
1066 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
1067 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
1068 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
1069 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
1070 swjdp_transaction_endcheck(swjdp);
1071 command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
1074 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1078 command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
1081 /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
1085 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
1086 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
1089 u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
1090 u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
1091 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
1092 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
1093 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
1094 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
1095 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
1096 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
1097 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
1098 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
1099 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
1100 component_start = component_base - 0x1000*(c_pid4>>4);
1101 command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
1102 command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
1103 command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
1104 command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
1105 /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
1110 command_print(cmd_ctx, "\t\tComponent not present");
1112 command_print(cmd_ctx, "\t\tEnd of ROM table");
1115 } while (romentry>0);
1119 command_print(cmd_ctx, "\tNo ROM table present");
1121 dap_ap_select(swjdp, apselold);