1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "arm_adi_v5.h"
73 #include <helper/time_support.h>
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
87 /***************************************************************************
89 * DPACC and APACC scanchain access through JTAG-DP *
91 ***************************************************************************/
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
112 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
113 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
115 struct arm_jtag *jtag_info = swjdp->jtag_info;
116 struct scan_field fields[2];
117 uint8_t out_addr_buf;
119 jtag_set_end_state(TAP_IDLE);
120 arm_jtag_set_instr(jtag_info, instr, NULL);
122 /* Scan out a read or write operation using some DP or AP register.
123 * For APACC access with any sticky error flag set, this is discarded.
125 fields[0].tap = jtag_info->tap;
126 fields[0].num_bits = 3;
127 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
128 fields[0].out_value = &out_addr_buf;
129 fields[0].in_value = ack;
131 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
132 * complete; data we write is discarded, data we read is unpredictable.
133 * When overrun detect is active, STICKYORUN is set.
136 fields[1].tap = jtag_info->tap;
137 fields[1].num_bits = 32;
138 fields[1].out_value = outvalue;
139 fields[1].in_value = invalue;
141 jtag_add_dr_scan(2, fields, jtag_get_end_state());
143 /* Add specified number of tck clocks after starting memory bus
144 * access, giving the hardware time to complete the access.
145 * They provide more time for the (MEM) AP to complete the read ...
146 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
148 if ((instr == JTAG_DP_APACC)
149 && ((reg_addr == AP_REG_DRW)
150 || ((reg_addr & 0xF0) == AP_REG_BD0))
151 && (swjdp->memaccess_tck != 0))
152 jtag_add_runtest(swjdp->memaccess_tck,
153 jtag_set_end_state(TAP_IDLE));
155 return jtag_get_error();
159 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
160 * This is exactly like adi_jtag_dp_scan(), except that endianness
161 * conversions are performed (so the types of invalue and outvalue
162 * must be different).
164 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
168 uint8_t out_value_buf[4];
171 buf_set_u32(out_value_buf, 0, 32, outvalue);
173 retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
174 out_value_buf, (uint8_t *)invalue, ack);
175 if (retval != ERROR_OK)
179 jtag_add_callback(arm_le_to_h_u32,
180 (jtag_callback_data_t) invalue);
186 * Utility to write AP registers.
188 static inline int adi_jtag_ap_write_check(struct swjdp_common *dap,
189 uint8_t reg_addr, uint8_t *outvalue)
191 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
192 outvalue, NULL, NULL);
195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
196 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
197 uint32_t outvalue, uint32_t *invalue)
201 /* Issue the read or write */
202 retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
203 RnW, outvalue, NULL, NULL);
204 if (retval != ERROR_OK)
207 /* For reads, collect posted value; RDBUFF has no other effect.
208 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
210 if ((RnW == DPAP_READ) && (invalue != NULL))
211 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
212 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
216 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
221 /* too expensive to call keep_alive() here */
224 /* Danger!!!! BROKEN!!!! */
225 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
226 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
227 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
228 R956 introduced the check on return value here and now Michael Schwingen reports
229 that this code no longer works....
231 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
235 LOG_ERROR("BUG: Why does this fail the first time????");
237 /* Why??? second time it works??? */
240 /* Post CTRL/STAT read; discard any previous posted read value
241 * but collect its ACK status.
243 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
244 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
245 if ((retval = jtag_execute_queue()) != ERROR_OK)
248 swjdp->ack = swjdp->ack & 0x7;
250 /* common code path avoids calling timeval_ms() */
251 if (swjdp->ack != JTAG_ACK_OK_FAULT)
253 long long then = timeval_ms();
255 while (swjdp->ack != JTAG_ACK_OK_FAULT)
257 if (swjdp->ack == JTAG_ACK_WAIT)
259 if ((timeval_ms()-then) > 1000)
261 /* NOTE: this would be a good spot
262 * to use JTAG_DP_ABORT.
264 LOG_WARNING("Timeout (1000ms) waiting "
266 "in JTAG-DP transaction");
267 return ERROR_JTAG_DEVICE_ERROR;
272 LOG_WARNING("Invalid ACK %#x "
273 "in JTAG-DP transaction",
275 return ERROR_JTAG_DEVICE_ERROR;
278 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
279 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
280 if ((retval = jtag_execute_queue()) != ERROR_OK)
282 swjdp->ack = swjdp->ack & 0x7;
286 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
288 /* Check for STICKYERR and STICKYORUN */
289 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
291 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
292 /* Check power to debug regions */
293 if ((ctrlstat & 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp);
297 uint32_t mem_ap_csw, mem_ap_tar;
299 /* Maybe print information about last intended
300 * MEM-AP access; but not if autoincrementing.
301 * *Real* CSW and TAR values are always shown.
303 if (swjdp->ap_tar_value != (uint32_t) -1)
304 LOG_DEBUG("MEM-AP Cached values: "
306 ", ap_csw 0x%" PRIx32
307 ", ap_tar 0x%" PRIx32,
308 swjdp->ap_bank_value,
310 swjdp->ap_tar_value);
312 if (ctrlstat & SSTICKYORUN)
313 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
314 "memaccess, or reduce jtag speed");
316 if (ctrlstat & SSTICKYERR)
317 LOG_ERROR("JTAG-DP STICKY ERROR");
319 /* Clear Sticky Error Bits */
320 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
321 DP_CTRL_STAT, DPAP_WRITE,
322 swjdp->dp_ctrl_stat | SSTICKYORUN
324 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
325 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
326 if ((retval = jtag_execute_queue()) != ERROR_OK)
329 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
331 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
332 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
333 if ((retval = jtag_execute_queue()) != ERROR_OK)
335 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
336 PRIx32, mem_ap_csw, mem_ap_tar);
339 if ((retval = jtag_execute_queue()) != ERROR_OK)
341 return ERROR_JTAG_DEVICE_ERROR;
347 /***************************************************************************
349 * DP and MEM-AP register access through APACC and DPACC *
351 ***************************************************************************/
353 static int dap_dp_write_reg(struct swjdp_common *swjdp,
354 uint32_t value, uint8_t reg_addr)
356 return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
357 reg_addr, DPAP_WRITE, value, NULL);
360 static int dap_dp_read_reg(struct swjdp_common *swjdp,
361 uint32_t *value, uint8_t reg_addr)
363 return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
364 reg_addr, DPAP_READ, 0, value);
368 * Select one of the APs connected to the specified DAP. The
369 * selection is implicitly used with future AP transactions.
370 * This is a NOP if the specified AP is already selected.
372 * @param swjdp The DAP
373 * @param apsel Number of the AP to (implicitly) use with further
374 * transactions. This normally identifies a MEM-AP.
376 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
378 uint32_t select = (apsel << 24) & 0xFF000000;
380 if (select != swjdp->apsel)
382 swjdp->apsel = select;
383 /* Switching AP invalidates cached values.
384 * Values MUST BE UPDATED BEFORE AP ACCESS.
386 swjdp->ap_bank_value = -1;
387 swjdp->ap_csw_value = -1;
388 swjdp->ap_tar_value = -1;
392 /** Select the AP register bank matching bits 7:4 of ap_reg. */
393 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
395 uint32_t select = (ap_reg & 0x000000F0);
397 if (select != swjdp->ap_bank_value)
399 swjdp->ap_bank_value = select;
400 select |= swjdp->apsel;
401 return dap_dp_write_reg(swjdp, select, DP_SELECT);
406 static int dap_ap_write_reg(struct swjdp_common *swjdp,
407 uint32_t reg_addr, uint8_t *out_value_buf)
411 retval = dap_ap_bankselect(swjdp, reg_addr);
412 if (retval != ERROR_OK)
415 return adi_jtag_ap_write_check(swjdp, reg_addr, out_value_buf);
419 * Asynchronous (queued) AP register write.
421 * @param swjdp The DAP whose currently selected AP will be written.
422 * @param reg_addr Eight bit AP register address.
423 * @param value Word to be written at reg_addr
425 * @return ERROR_OK if the transaction was properly queued, else a fault code.
427 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
428 uint32_t reg_addr, uint32_t value)
430 uint8_t out_value_buf[4];
432 buf_set_u32(out_value_buf, 0, 32, value);
433 return dap_ap_write_reg(swjdp,
434 reg_addr, out_value_buf);
438 * Asynchronous (queued) AP register eread.
440 * @param swjdp The DAP whose currently selected AP will be read.
441 * @param reg_addr Eight bit AP register address.
442 * @param value Points to where the 32-bit (little-endian) word will be stored.
444 * @return ERROR_OK if the transaction was properly queued, else a fault code.
446 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
447 uint32_t reg_addr, uint32_t *value)
451 retval = dap_ap_bankselect(swjdp, reg_addr);
452 if (retval != ERROR_OK)
455 return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
456 DPAP_READ, 0, value);
460 * Queue transactions setting up transfer parameters for the
461 * currently selected MEM-AP.
463 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
464 * initiate data reads or writes using memory or peripheral addresses.
465 * If the CSW is configured for it, the TAR may be automatically
466 * incremented after each transfer.
468 * @todo Rename to reflect it being specifically a MEM-AP function.
470 * @param swjdp The DAP connected to the MEM-AP.
471 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
472 * matches the cached value, the register is not changed.
473 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
474 * matches the cached address, the register is not changed.
476 * @return ERROR_OK if the transaction was properly queued, else a fault code.
478 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
482 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
483 if (csw != swjdp->ap_csw_value)
485 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
486 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
487 if (retval != ERROR_OK)
489 swjdp->ap_csw_value = csw;
491 if (tar != swjdp->ap_tar_value)
493 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
494 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
495 if (retval != ERROR_OK)
497 swjdp->ap_tar_value = tar;
499 /* Disable TAR cache when autoincrementing */
500 if (csw & CSW_ADDRINC_MASK)
501 swjdp->ap_tar_value = -1;
506 * Asynchronous (queued) read of a word from memory or a system register.
508 * @param swjdp The DAP connected to the MEM-AP performing the read.
509 * @param address Address of the 32-bit word to read; it must be
510 * readable by the currently selected MEM-AP.
511 * @param value points to where the word will be stored when the
512 * transaction queue is flushed (assuming no errors).
514 * @return ERROR_OK for success. Otherwise a fault code.
516 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
521 /* Use banked addressing (REG_BDx) to avoid some link traffic
522 * (updating TAR) when reading several consecutive addresses.
524 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
525 address & 0xFFFFFFF0);
526 if (retval != ERROR_OK)
529 return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
533 * Synchronous read of a word from memory or a system register.
534 * As a side effect, this flushes any queued transactions.
536 * @param swjdp The DAP connected to the MEM-AP performing the read.
537 * @param address Address of the 32-bit word to read; it must be
538 * readable by the currently selected MEM-AP.
539 * @param value points to where the result will be stored.
541 * @return ERROR_OK for success; *value holds the result.
542 * Otherwise a fault code.
544 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
549 retval = mem_ap_read_u32(swjdp, address, value);
550 if (retval != ERROR_OK)
553 return jtagdp_transaction_endcheck(swjdp);
557 * Asynchronous (queued) write of a word to memory or a system register.
559 * @param swjdp The DAP connected to the MEM-AP.
560 * @param address Address to be written; it must be writable by
561 * the currently selected MEM-AP.
562 * @param value Word that will be written to the address when transaction
563 * queue is flushed (assuming no errors).
565 * @return ERROR_OK for success. Otherwise a fault code.
567 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
572 /* Use banked addressing (REG_BDx) to avoid some link traffic
573 * (updating TAR) when writing several consecutive addresses.
575 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
576 address & 0xFFFFFFF0);
577 if (retval != ERROR_OK)
580 return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
585 * Synchronous write of a word to memory or a system register.
586 * As a side effect, this flushes any queued transactions.
588 * @param swjdp The DAP connected to the MEM-AP.
589 * @param address Address to be written; it must be writable by
590 * the currently selected MEM-AP.
591 * @param value Word that will be written.
593 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
595 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
598 int retval = mem_ap_write_u32(swjdp, address, value);
600 if (retval != ERROR_OK)
603 return jtagdp_transaction_endcheck(swjdp);
606 /*****************************************************************************
608 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
610 * Write a buffer in target order (little endian) *
612 *****************************************************************************/
613 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
615 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
616 uint32_t adr = address;
617 uint8_t* pBuffer = buffer;
622 /* if we have an unaligned access - reorder data */
625 for (writecount = 0; writecount < count; writecount++)
629 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
631 for (i = 0; i < 4; i++)
633 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
637 pBuffer += sizeof(uint32_t);
643 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
644 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
645 if (wcount < blocksize)
648 /* handle unaligned data at 4k boundary */
652 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
654 for (writecount = 0; writecount < blocksize; writecount++)
656 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
659 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
661 wcount = wcount - blocksize;
662 address = address + 4 * blocksize;
663 buffer = buffer + 4 * blocksize;
672 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
673 return ERROR_JTAG_DEVICE_ERROR;
680 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
681 uint8_t *buffer, int count, uint32_t address)
683 int retval = ERROR_OK;
684 int wcount, blocksize, writecount, i;
692 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
693 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
695 if (wcount < blocksize)
698 /* handle unaligned data at 4k boundary */
702 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
703 writecount = blocksize;
707 nbytes = MIN((writecount << 1), 4);
711 if (mem_ap_write_buf_u16(swjdp, buffer,
712 nbytes, address) != ERROR_OK)
714 LOG_WARNING("Block write error address "
715 "0x%" PRIx32 ", count 0x%x",
717 return ERROR_JTAG_DEVICE_ERROR;
720 address += nbytes >> 1;
725 memcpy(&outvalue, buffer, sizeof(uint32_t));
727 for (i = 0; i < nbytes; i++)
729 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
734 memcpy(&outvalue, buffer, sizeof(uint32_t));
735 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
736 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
738 LOG_WARNING("Block write error address "
739 "0x%" PRIx32 ", count 0x%x",
741 return ERROR_JTAG_DEVICE_ERROR;
745 buffer += nbytes >> 1;
746 writecount -= nbytes >> 1;
748 } while (writecount);
755 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
757 int retval = ERROR_OK;
760 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
764 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
766 memcpy(&svalue, buffer, sizeof(uint16_t));
767 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
768 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
769 retval = jtagdp_transaction_endcheck(swjdp);
778 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
779 uint8_t *buffer, int count, uint32_t address)
781 int retval = ERROR_OK;
782 int wcount, blocksize, writecount, i;
790 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
791 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
793 if (wcount < blocksize)
796 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
797 writecount = blocksize;
801 nbytes = MIN(writecount, 4);
805 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
807 LOG_WARNING("Block write error address "
808 "0x%" PRIx32 ", count 0x%x",
810 return ERROR_JTAG_DEVICE_ERROR;
818 memcpy(&outvalue, buffer, sizeof(uint32_t));
820 for (i = 0; i < nbytes; i++)
822 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
827 memcpy(&outvalue, buffer, sizeof(uint32_t));
828 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
829 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
831 LOG_WARNING("Block write error address "
832 "0x%" PRIx32 ", count 0x%x",
834 return ERROR_JTAG_DEVICE_ERROR;
839 writecount -= nbytes;
841 } while (writecount);
848 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
850 int retval = ERROR_OK;
853 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
857 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
858 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
859 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
860 retval = jtagdp_transaction_endcheck(swjdp);
870 * Synchronously read a block of 32-bit words into a buffer
871 * @param swjdp The DAP connected to the MEM-AP.
872 * @param buffer where the words will be stored (in host byte order).
873 * @param count How many words to read.
874 * @param address Memory address from which to read words; all the
875 * words must be readable by the currently selected MEM-AP.
877 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
878 int count, uint32_t address)
880 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
881 uint32_t adr = address;
882 uint8_t* pBuffer = buffer;
889 /* Adjust to read blocks within boundaries aligned to the
890 * TAR autoincrement size (at least 2^10). Autoincrement
891 * mode avoids an extra per-word roundtrip to update TAR.
893 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
895 if (wcount < blocksize)
898 /* handle unaligned data at 4k boundary */
902 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
905 /* Scan out first read */
906 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
907 DPAP_READ, 0, NULL, NULL);
908 for (readcount = 0; readcount < blocksize - 1; readcount++)
910 /* Scan out next read; scan in posted value for the
911 * previous one. Assumes read is acked "OK/FAULT",
912 * and CTRL_STAT says that meant "OK".
914 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
915 DPAP_READ, 0, buffer + 4 * readcount,
919 /* Scan in last posted value; RDBUFF has no other effect,
920 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
922 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
923 DPAP_READ, 0, buffer + 4 * readcount,
925 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
927 wcount = wcount - blocksize;
928 address += 4 * blocksize;
929 buffer += 4 * blocksize;
938 LOG_WARNING("Block read error address 0x%" PRIx32
939 ", count 0x%x", address, count);
940 return ERROR_JTAG_DEVICE_ERROR;
944 /* if we have an unaligned access - reorder data */
947 for (readcount = 0; readcount < count; readcount++)
951 memcpy(&data, pBuffer, sizeof(uint32_t));
953 for (i = 0; i < 4; i++)
955 *((uint8_t*)pBuffer) =
956 (data >> 8 * (adr & 0x3));
966 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
967 uint8_t *buffer, int count, uint32_t address)
970 int retval = ERROR_OK;
971 int wcount, blocksize, readcount, i;
979 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
980 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
981 if (wcount < blocksize)
984 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
986 /* handle unaligned data at 4k boundary */
989 readcount = blocksize;
993 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
994 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
996 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
997 return ERROR_JTAG_DEVICE_ERROR;
1000 nbytes = MIN((readcount << 1), 4);
1002 for (i = 0; i < nbytes; i++)
1004 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1009 readcount -= (nbytes >> 1);
1010 } while (readcount);
1011 wcount -= blocksize;
1018 * Synchronously read a block of 16-bit halfwords into a buffer
1019 * @param swjdp The DAP connected to the MEM-AP.
1020 * @param buffer where the halfwords will be stored (in host byte order).
1021 * @param count How many halfwords to read.
1022 * @param address Memory address from which to read words; all the
1023 * words must be readable by the currently selected MEM-AP.
1025 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
1026 int count, uint32_t address)
1028 uint32_t invalue, i;
1029 int retval = ERROR_OK;
1032 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1036 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1037 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1038 retval = jtagdp_transaction_endcheck(swjdp);
1041 for (i = 0; i < 2; i++)
1043 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1050 uint16_t svalue = (invalue >> 8 * (address & 0x3));
1051 memcpy(buffer, &svalue, sizeof(uint16_t));
1061 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1062 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1064 * The solution is to arrange for a large out/in scan in this loop and
1065 * and convert data afterwards.
1067 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1068 uint8_t *buffer, int count, uint32_t address)
1071 int retval = ERROR_OK;
1072 int wcount, blocksize, readcount, i;
1080 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1081 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1083 if (wcount < blocksize)
1086 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1087 readcount = blocksize;
1091 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1092 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1094 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1095 return ERROR_JTAG_DEVICE_ERROR;
1098 nbytes = MIN(readcount, 4);
1100 for (i = 0; i < nbytes; i++)
1102 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1107 readcount -= nbytes;
1108 } while (readcount);
1109 wcount -= blocksize;
1116 * Synchronously read a block of bytes into a buffer
1117 * @param swjdp The DAP connected to the MEM-AP.
1118 * @param buffer where the bytes will be stored.
1119 * @param count How many bytes to read.
1120 * @param address Memory address from which to read data; all the
1121 * data must be readable by the currently selected MEM-AP.
1123 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
1124 int count, uint32_t address)
1127 int retval = ERROR_OK;
1130 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1134 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1135 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1136 retval = jtagdp_transaction_endcheck(swjdp);
1137 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1147 * Initialize a DAP. This sets up the power domains, prepares the DP
1148 * for further use, and arranges to use AP #0 for all AP operations
1149 * until dap_ap-select() changes that policy.
1151 * @param swjdp The DAP being initialized.
1153 * @todo Rename this. We also need an initialization scheme which account
1154 * for SWD transports not just JTAG; that will need to address differences
1155 * in layering. (JTAG is useful without any debug target; but not SWD.)
1156 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1158 int ahbap_debugport_init(struct swjdp_common *swjdp)
1160 uint32_t idreg, romaddr, dummy;
1167 /* Default MEM-AP setup.
1169 * REVISIT AP #0 may be an inappropriate default for this.
1170 * Should we probe, or take a hint from the caller?
1171 * Presumably we can ignore the possibility of multiple APs.
1174 dap_ap_select(swjdp, 0);
1176 /* DP initialization */
1177 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1178 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1179 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1181 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1183 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1184 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1185 if ((retval = jtag_execute_queue()) != ERROR_OK)
1188 /* Check that we have debug power domains activated */
1189 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1191 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1192 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1193 if ((retval = jtag_execute_queue()) != ERROR_OK)
1198 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1200 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1201 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1202 if ((retval = jtag_execute_queue()) != ERROR_OK)
1207 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1208 /* With debug power on we can activate OVERRUN checking */
1209 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1210 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1211 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1214 * REVISIT this isn't actually *initializing* anything in an AP,
1215 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1216 * Should it? If the ROM address is valid, is this the right
1217 * place to scan the table and do any topology detection?
1219 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1220 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1222 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1223 ", Debug ROM Address 0x%" PRIx32,
1224 swjdp->apsel, idreg, romaddr);
1229 /* CID interpretation -- see ARM IHI 0029B section 3
1230 * and ARM IHI 0031A table 13-3.
1232 static const char *class_description[16] ={
1233 "Reserved", "ROM table", "Reserved", "Reserved",
1234 "Reserved", "Reserved", "Reserved", "Reserved",
1235 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1236 "Reserved", "OptimoDE DESS",
1237 "Generic IP component", "PrimeCell or System component"
1241 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1243 return cid3 == 0xb1 && cid2 == 0x05
1244 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1247 int dap_info_command(struct command_context *cmd_ctx,
1248 struct swjdp_common *swjdp, int apsel)
1251 uint32_t dbgbase, apid;
1252 int romtable_present = 0;
1256 /* AP address is in bits 31:24 of DP_SELECT */
1258 return ERROR_INVALID_ARGUMENTS;
1260 apselold = swjdp->apsel;
1261 dap_ap_select(swjdp, apsel);
1262 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1263 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1264 jtagdp_transaction_endcheck(swjdp);
1265 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1266 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1267 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1273 command_print(cmd_ctx, "\tType is JTAG-AP");
1276 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1279 command_print(cmd_ctx, "\tType is MEM-AP APB");
1282 command_print(cmd_ctx, "\tUnknown AP type");
1286 /* NOTE: a MEM-AP may have a single CoreSight component that's
1287 * not a ROM table ... or have no such components at all.
1290 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1295 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1298 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1299 if (romtable_present)
1301 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1302 uint16_t entry_offset;
1304 /* bit 16 of apid indicates a memory access port */
1306 command_print(cmd_ctx, "\tValid ROM table present");
1308 command_print(cmd_ctx, "\tROM table in legacy format");
1310 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1311 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1312 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1313 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1314 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1315 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1316 jtagdp_transaction_endcheck(swjdp);
1317 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1318 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1319 ", CID2 0x%2.2" PRIx32
1320 ", CID1 0x%2.2" PRIx32
1321 ", CID0 0x%2.2" PRIx32,
1322 cid3, cid2, cid1, cid0);
1324 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1326 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1327 "Dedicated debug bus.");
1329 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1333 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1334 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1337 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1338 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1339 uint32_t component_start, component_base;
1343 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1344 + (int)(romentry & 0xFFFFF000));
1345 mem_ap_read_atomic_u32(swjdp,
1346 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1347 mem_ap_read_atomic_u32(swjdp,
1348 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1349 mem_ap_read_atomic_u32(swjdp,
1350 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1351 mem_ap_read_atomic_u32(swjdp,
1352 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1353 mem_ap_read_atomic_u32(swjdp,
1354 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1355 mem_ap_read_atomic_u32(swjdp,
1356 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1357 mem_ap_read_atomic_u32(swjdp,
1358 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1359 mem_ap_read_atomic_u32(swjdp,
1360 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1361 mem_ap_read_atomic_u32(swjdp,
1362 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1363 component_start = component_base - 0x1000*(c_pid4 >> 4);
1365 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1366 ", start address 0x%" PRIx32,
1367 component_base, component_start);
1368 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1369 (int) (c_cid1 >> 4) & 0xf,
1370 /* See ARM IHI 0029B Table 3-3 */
1371 class_description[(c_cid1 >> 4) & 0xf]);
1373 /* CoreSight component? */
1374 if (((c_cid1 >> 4) & 0x0f) == 9) {
1377 char *major = "Reserved", *subtype = "Reserved";
1379 mem_ap_read_atomic_u32(swjdp,
1380 (component_base & 0xfffff000) | 0xfcc,
1382 minor = (devtype >> 4) & 0x0f;
1383 switch (devtype & 0x0f) {
1385 major = "Miscellaneous";
1391 subtype = "Validation component";
1396 major = "Trace Sink";
1410 major = "Trace Link";
1416 subtype = "Funnel, router";
1422 subtype = "FIFO, buffer";
1427 major = "Trace Source";
1433 subtype = "Processor";
1439 subtype = "Engine/Coprocessor";
1447 major = "Debug Control";
1453 subtype = "Trigger Matrix";
1456 subtype = "Debug Auth";
1461 major = "Debug Logic";
1467 subtype = "Processor";
1473 subtype = "Engine/Coprocessor";
1478 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1479 (unsigned) (devtype & 0xff),
1481 /* REVISIT also show 0xfc8 DevId */
1484 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1485 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1486 ", CID2 0x%2.2" PRIx32
1487 ", CID1 0x%2.2" PRIx32
1488 ", CID0 0x%2.2" PRIx32,
1489 c_cid3, c_cid2, c_cid1, c_cid0);
1490 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1491 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1493 (int) c_pid3, (int) c_pid2,
1494 (int) c_pid1, (int) c_pid0);
1496 /* Part number interpretations are from Cortex
1497 * core specs, the CoreSight components TRM
1498 * (ARM DDI 0314H), and ETM specs; also from
1499 * chip observation (e.g. TI SDTI).
1501 part_num = c_pid0 & 0xff;
1502 part_num |= (c_pid1 & 0x0f) << 8;
1505 type = "Cortex-M3 NVIC";
1506 full = "(Interrupt Controller)";
1509 type = "Cortex-M3 ITM";
1510 full = "(Instrumentation Trace Module)";
1513 type = "Cortex-M3 DWT";
1514 full = "(Data Watchpoint and Trace)";
1517 type = "Cortex-M3 FBP";
1518 full = "(Flash Patch and Breakpoint)";
1521 type = "CoreSight ETM11";
1522 full = "(Embedded Trace)";
1524 // case 0x113: what?
1525 case 0x120: /* from OMAP3 memmap */
1527 full = "(System Debug Trace Interface)";
1529 case 0x343: /* from OMAP3 memmap */
1534 type = "Cortex-M3 ETM";
1535 full = "(Embedded Trace)";
1538 type = "Coresight CTI";
1539 full = "(Cross Trigger)";
1542 type = "Coresight ETB";
1543 full = "(Trace Buffer)";
1546 type = "Coresight CSTF";
1547 full = "(Trace Funnel)";
1550 type = "CoreSight ETM9";
1551 full = "(Embedded Trace)";
1554 type = "Coresight TPIU";
1555 full = "(Trace Port Interface Unit)";
1558 type = "Cortex-A8 ETM";
1559 full = "(Embedded Trace)";
1562 type = "Cortex-A8 CTI";
1563 full = "(Cross Trigger)";
1566 type = "Cortex-M3 TPIU";
1567 full = "(Trace Port Interface Unit)";
1570 type = "Cortex-A8 Debug";
1571 full = "(Debug Unit)";
1574 type = "-*- unrecognized -*-";
1578 command_print(cmd_ctx, "\t\tPart is %s %s",
1584 command_print(cmd_ctx, "\t\tComponent not present");
1586 command_print(cmd_ctx, "\t\tEnd of ROM table");
1589 } while (romentry > 0);
1593 command_print(cmd_ctx, "\tNo ROM table present");
1595 dap_ap_select(swjdp, apselold);
1600 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1602 uint32_t apsel, apselsave, baseaddr;
1605 apselsave = swjdp->apsel;
1608 apsel = swjdp->apsel;
1611 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1612 /* AP address is in bits 31:24 of DP_SELECT */
1614 return ERROR_INVALID_ARGUMENTS;
1617 return ERROR_COMMAND_SYNTAX_ERROR;
1620 if (apselsave != apsel)
1621 dap_ap_select(swjdp, apsel);
1623 /* NOTE: assumes we're talking to a MEM-AP, which
1624 * has a base address. There are other kinds of AP,
1625 * though they're not common for now. This should
1626 * use the ID register to verify it's a MEM-AP.
1628 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1629 retval = jtagdp_transaction_endcheck(swjdp);
1630 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1632 if (apselsave != apsel)
1633 dap_ap_select(swjdp, apselsave);
1638 DAP_COMMAND_HANDLER(dap_memaccess_command)
1640 uint32_t memaccess_tck;
1644 memaccess_tck = swjdp->memaccess_tck;
1647 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1650 return ERROR_COMMAND_SYNTAX_ERROR;
1652 swjdp->memaccess_tck = memaccess_tck;
1654 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1655 swjdp->memaccess_tck);
1660 DAP_COMMAND_HANDLER(dap_apsel_command)
1662 uint32_t apsel, apid;
1670 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1671 /* AP address is in bits 31:24 of DP_SELECT */
1673 return ERROR_INVALID_ARGUMENTS;
1676 return ERROR_COMMAND_SYNTAX_ERROR;
1679 dap_ap_select(swjdp, apsel);
1680 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1681 retval = jtagdp_transaction_endcheck(swjdp);
1682 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1688 DAP_COMMAND_HANDLER(dap_apid_command)
1690 uint32_t apsel, apselsave, apid;
1693 apselsave = swjdp->apsel;
1696 apsel = swjdp->apsel;
1699 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1700 /* AP address is in bits 31:24 of DP_SELECT */
1702 return ERROR_INVALID_ARGUMENTS;
1705 return ERROR_COMMAND_SYNTAX_ERROR;
1708 if (apselsave != apsel)
1709 dap_ap_select(swjdp, apsel);
1711 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1712 retval = jtagdp_transaction_endcheck(swjdp);
1713 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1714 if (apselsave != apsel)
1715 dap_ap_select(swjdp, apselsave);
1721 * This represents the bits which must be sent out on TMS/SWDIO to
1722 * switch a DAP implemented using an SWJ-DP module into SWD mode.
1723 * These bits are stored (and transmitted) LSB-first.
1725 * See the DAP-Lite specification, section 2.2.5 for information
1726 * about making the debug link select SWD or JTAG. (Similar info
1727 * is in a few other ARM documents.)
1729 static const uint8_t jtag2swd_bitseq[] = {
1730 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1731 * putting both JTAG and SWD logic into reset state.
1733 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1734 /* Switching sequence enables SWD and disables JTAG
1735 * NOTE: bits in the DP's IDCODE may expose the need for
1736 * an old/deprecated sequence (0xb6 0xed).
1739 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1740 * putting both JTAG and SWD logic into reset state.
1742 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1746 * Put the debug link into SWD mode, if the target supports it.
1747 * The link's initial mode may be either JTAG (for example,
1748 * with SWJ-DP after reset) or SWD.
1750 * @param target Enters SWD mode (if possible).
1752 * Note that targets using the JTAG-DP do not support SWD, and that
1753 * some targets which could otherwise support it may have have been
1754 * configured to disable SWD signaling
1756 * @return ERROR_OK or else a fault code.
1758 int dap_to_swd(struct target *target)
1762 LOG_DEBUG("Enter SWD mode");
1764 /* REVISIT it's nasty to need to make calls to a "jtag"
1765 * subsystem if the link isn't in JTAG mode...
1768 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1769 jtag2swd_bitseq, TAP_INVALID);
1770 if (retval == ERROR_OK)
1771 retval = jtag_execute_queue();
1773 /* REVISIT set up the DAP's ops vector for SWD mode. */
1779 * This represents the bits which must be sent out on TMS/SWDIO to
1780 * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1781 * These bits are stored (and transmitted) LSB-first.
1783 * These bits are stored (and transmitted) LSB-first.
1785 static const uint8_t swd2jtag_bitseq[] = {
1786 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1787 * putting both JTAG and SWD logic into reset state.
1789 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1790 /* Switching equence disables SWD and enables JTAG
1791 * NOTE: bits in the DP's IDCODE can expose the need for
1792 * the old/deprecated sequence (0xae 0xde).
1795 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1796 * putting both JTAG and SWD logic into reset state.
1797 * NOTE: some docs say "at least 5".
1799 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1802 /** Put the debug link into JTAG mode, if the target supports it.
1803 * The link's initial mode may be either SWD or JTAG.
1805 * @param target Enters JTAG mode (if possible).
1807 * Note that targets implemented with SW-DP do not support JTAG, and
1808 * that some targets which could otherwise support it may have been
1809 * configured to disable JTAG signaling
1811 * @return ERROR_OK or else a fault code.
1813 int dap_to_jtag(struct target *target)
1817 LOG_DEBUG("Enter JTAG mode");
1819 /* REVISIT it's nasty to need to make calls to a "jtag"
1820 * subsystem if the link isn't in JTAG mode...
1823 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
1824 swd2jtag_bitseq, TAP_RESET);
1825 if (retval == ERROR_OK)
1826 retval = jtag_execute_queue();
1828 /* REVISIT set up the DAP's ops vector for JTAG mode. */