1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
30 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
32 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
33 * Cortex-M3(tm) TRM, ARM DDI 0337C *
35 ***************************************************************************/
41 #include "arm_adi_v5.h"
42 #include "time_support.h"
46 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
47 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
48 * result checking until swjdp_end_transaction()
49 * This must be done before using or deallocating any return variables.
50 * swjdp->trans_mode == TRANS_MODE_ATOMIC
51 * All reads and writes to the AHB bus are checked for valid completion, and return values
52 * are immediatley available.
55 /***************************************************************************
57 * DPACC and APACC scanchain access through JTAG-DP *
59 ***************************************************************************/
61 /* Scan out and in from target ordered u8 buffers */
62 int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
64 scan_field_t fields[2];
67 jtag_add_end_state(TAP_IDLE);
68 arm_jtag_set_instr(jtag_info, instr, NULL);
70 fields[0].tap = jtag_info->tap;
71 fields[0].num_bits = 3;
72 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
73 fields[0].out_value = &out_addr_buf;
75 fields[0].in_value = ack;
81 fields[1].tap = jtag_info->tap;
82 fields[1].num_bits = 32;
83 fields[1].out_value = outvalue;
85 fields[1].in_value = invalue;
91 jtag_add_dr_scan(2, fields, TAP_INVALID);
96 /* Scan out and in from host ordered u32 variables */
97 int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
99 scan_field_t fields[2];
103 jtag_add_end_state(TAP_IDLE);
104 arm_jtag_set_instr(jtag_info, instr, NULL);
106 fields[0].tap = jtag_info->tap;
107 fields[0].num_bits = 3;
108 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
109 fields[0].out_value = &out_addr_buf;
110 fields[0].in_value = ack;
114 fields[1].tap = jtag_info->tap;
115 fields[1].num_bits = 32;
116 buf_set_u32(out_value_buf, 0, 32, outvalue);
117 fields[1].out_value = out_value_buf;
118 fields[1].in_value = NULL;
124 fields[1].in_value = tmp;
125 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
127 *invalue=le_to_h_u32(tmp);
131 jtag_add_dr_scan(2, fields, TAP_INVALID);
137 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
138 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
140 adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
141 if ((RnW == DPAP_READ) && (invalue != NULL))
143 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
146 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
147 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
149 return swjdp_transaction_endcheck(swjdp);
155 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
157 adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
158 if ((RnW==DPAP_READ) && (invalue != NULL))
160 adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
163 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
164 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
166 return swjdp_transaction_endcheck(swjdp);
172 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
177 /* too expensive to call keep_alive() here */
180 /* Danger!!!! BROKEN!!!! */
181 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
182 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
183 R956 introduced the check on return value here and now Michael Schwingen reports
184 that this code no longer works....
186 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
188 if ((retval=jtag_execute_queue())!=ERROR_OK)
190 LOG_ERROR("BUG: Why does this fail the first time????");
192 /* Why??? second time it works??? */
195 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
196 if ((retval=jtag_execute_queue())!=ERROR_OK)
199 swjdp->ack = swjdp->ack & 0x7;
203 long long then=timeval_ms();
204 while (swjdp->ack != 2)
208 if ((timeval_ms()-then) > 1000)
210 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
211 return ERROR_JTAG_DEVICE_ERROR;
216 LOG_WARNING("Invalid ACK in SWJDP transaction");
217 return ERROR_JTAG_DEVICE_ERROR;
220 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
221 if ((retval=jtag_execute_queue())!=ERROR_OK)
223 swjdp->ack = swjdp->ack & 0x7;
227 /* common code path avoids fn to timeval_ms() */
230 /* Check for STICKYERR and STICKYORUN */
231 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
233 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
234 /* Check power to debug regions */
235 if ((ctrlstat & 0xf0000000) != 0xf0000000)
237 ahbap_debugport_init(swjdp);
241 u32 mem_ap_csw, mem_ap_tar;
243 /* Print information about last AHBAP access */
244 LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
245 if (ctrlstat & SSTICKYORUN)
246 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
248 if (ctrlstat & SSTICKYERR)
249 LOG_ERROR("SWJ-DP STICKY ERROR");
251 /* Clear Sticky Error Bits */
252 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
253 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
254 if ((retval=jtag_execute_queue())!=ERROR_OK)
257 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
259 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
260 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
261 if ((retval=jtag_execute_queue())!=ERROR_OK)
263 LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
266 if ((retval=jtag_execute_queue())!=ERROR_OK)
268 return ERROR_JTAG_DEVICE_ERROR;
274 /***************************************************************************
276 * DP and MEM-AP register access through APACC and DPACC *
278 ***************************************************************************/
280 int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
282 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
285 int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
287 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
290 int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
293 select = (apsel<<24) & 0xFF000000;
295 if (select != swjdp->apsel)
297 swjdp->apsel = select;
298 /* Switchin AP invalidates cached values */
299 swjdp->dp_select_value = -1;
300 swjdp->ap_csw_value = -1;
301 swjdp->ap_tar_value = -1;
307 int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
310 select = (ap_reg & 0x000000F0);
312 if (select != swjdp->dp_select_value)
314 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
315 swjdp->dp_select_value = select;
321 int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
323 dap_dp_bankselect(swjdp, reg_addr);
324 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
329 int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
331 dap_dp_bankselect(swjdp, reg_addr);
332 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
336 int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
340 buf_set_u32(out_value_buf, 0, 32, value);
341 dap_dp_bankselect(swjdp, reg_addr);
342 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
347 int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
349 dap_dp_bankselect(swjdp, reg_addr);
350 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
355 /***************************************************************************
357 * AHB-AP access to memory and system registers on AHB bus *
359 ***************************************************************************/
361 int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
363 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
364 if (csw != swjdp->ap_csw_value)
366 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
367 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
368 swjdp->ap_csw_value = csw;
370 if (tar != swjdp->ap_tar_value)
372 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
373 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
374 swjdp->ap_tar_value = tar;
376 if (csw & CSW_ADDRINC_MASK)
378 /* Do not cache TAR value when autoincrementing */
379 swjdp->ap_tar_value = -1;
384 /*****************************************************************************
386 * mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
388 * Read a u32 value from memory or system register *
389 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
390 * but with less overhead *
391 *****************************************************************************/
392 int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
394 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
396 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
397 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
402 int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
404 mem_ap_read_u32(swjdp, address, value);
406 return swjdp_transaction_endcheck(swjdp);
409 /*****************************************************************************
411 * mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
413 * Write a u32 value to memory or memory mapped register *
415 *****************************************************************************/
416 int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
418 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
420 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
421 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
426 int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
428 mem_ap_write_u32(swjdp, address, value);
430 return swjdp_transaction_endcheck(swjdp);
433 /*****************************************************************************
435 * mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
437 * Write a buffer in target order (little endian) *
439 *****************************************************************************/
440 int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
442 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
444 u8* pBuffer = buffer;
446 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
451 /* if we have an unaligned access - reorder data */
454 for (writecount = 0; writecount < count; writecount++)
458 memcpy(&outvalue, pBuffer, sizeof(u32));
460 for (i = 0; i < 4; i++ )
462 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
466 pBuffer += sizeof(u32);
472 /* Adjust to write blocks within 4K aligned boundaries */
473 blocksize = (0x1000 - (0xFFF & address)) >> 2;
474 if (wcount < blocksize)
477 /* handle unaligned data at 4k boundary */
481 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
483 for (writecount = 0; writecount < blocksize; writecount++)
485 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
488 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
490 wcount = wcount - blocksize;
491 address = address + 4 * blocksize;
492 buffer = buffer + 4 * blocksize;
501 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
502 return ERROR_JTAG_DEVICE_ERROR;
509 int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
511 int retval = ERROR_OK;
512 int wcount, blocksize, writecount, i;
514 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
522 /* Adjust to read within 4K block boundaries */
523 blocksize = (0x1000 - (0xFFF & address)) >> 1;
525 if (wcount < blocksize)
528 /* handle unaligned data at 4k boundary */
532 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
533 writecount = blocksize;
537 nbytes = MIN((writecount << 1), 4);
541 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
543 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
544 return ERROR_JTAG_DEVICE_ERROR;
547 address += nbytes >> 1;
552 memcpy(&outvalue, buffer, sizeof(u32));
554 for (i = 0; i < nbytes; i++ )
556 *((u8*)buffer + (address & 0x3)) = outvalue;
561 memcpy(&outvalue, buffer, sizeof(u32));
562 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
563 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
565 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
566 return ERROR_JTAG_DEVICE_ERROR;
570 buffer += nbytes >> 1;
571 writecount -= nbytes >> 1;
573 } while (writecount);
580 int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
582 int retval = ERROR_OK;
585 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
587 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
591 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
593 memcpy(&svalue, buffer, sizeof(u16));
594 u32 outvalue = (u32)svalue << 8 * (address & 0x3);
595 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
596 retval = swjdp_transaction_endcheck(swjdp);
605 int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
607 int retval = ERROR_OK;
608 int wcount, blocksize, writecount, i;
610 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
618 /* Adjust to read within 4K block boundaries */
619 blocksize = (0x1000 - (0xFFF & address));
621 if (wcount < blocksize)
624 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
625 writecount = blocksize;
629 nbytes = MIN(writecount, 4);
633 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
635 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
636 return ERROR_JTAG_DEVICE_ERROR;
644 memcpy(&outvalue, buffer, sizeof(u32));
646 for (i = 0; i < nbytes; i++ )
648 *((u8*)buffer + (address & 0x3)) = outvalue;
653 memcpy(&outvalue, buffer, sizeof(u32));
654 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
655 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
657 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
658 return ERROR_JTAG_DEVICE_ERROR;
663 writecount -= nbytes;
665 } while (writecount);
672 int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
674 int retval = ERROR_OK;
677 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
679 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
683 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
684 u32 outvalue = (u32)*buffer << 8 * (address & 0x3);
685 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
686 retval = swjdp_transaction_endcheck(swjdp);
695 /*********************************************************************************
697 * mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
699 * Read block fast in target order (little endian) into a buffer *
701 **********************************************************************************/
702 int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
704 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
706 u8* pBuffer = buffer;
708 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
715 /* Adjust to read within 4K block boundaries */
716 blocksize = (0x1000 - (0xFFF & address)) >> 2;
717 if (wcount < blocksize)
720 /* handle unaligned data at 4k boundary */
724 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
726 /* Scan out first read */
727 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
728 for (readcount = 0; readcount < blocksize - 1; readcount++)
730 /* Scan out read instruction and scan in previous value */
731 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
734 /* Scan in last value */
735 adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
736 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
738 wcount = wcount - blocksize;
739 address += 4 * blocksize;
740 buffer += 4 * blocksize;
749 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
750 return ERROR_JTAG_DEVICE_ERROR;
754 /* if we have an unaligned access - reorder data */
757 for (readcount = 0; readcount < count; readcount++)
761 memcpy(&data, pBuffer, sizeof(u32));
763 for (i = 0; i < 4; i++ )
765 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
775 int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
778 int retval = ERROR_OK;
779 int wcount, blocksize, readcount, i;
781 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
789 /* Adjust to read within 4K block boundaries */
790 blocksize = (0x1000 - (0xFFF & address)) >> 1;
791 if (wcount < blocksize)
794 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
796 /* handle unaligned data at 4k boundary */
799 readcount = blocksize;
803 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
804 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
806 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
807 return ERROR_JTAG_DEVICE_ERROR;
810 nbytes = MIN((readcount << 1), 4);
812 for (i = 0; i < nbytes; i++ )
814 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
819 readcount -= (nbytes >> 1);
827 int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
830 int retval = ERROR_OK;
833 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
835 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
839 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
840 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
841 retval = swjdp_transaction_endcheck(swjdp);
844 for (i = 0; i < 2; i++ )
846 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
853 u16 svalue = (invalue >> 8 * (address & 0x3));
854 memcpy(buffer, &svalue, sizeof(u16));
864 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
865 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
867 * The solution is to arrange for a large out/in scan in this loop and
868 * and convert data afterwards.
870 int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
873 int retval = ERROR_OK;
874 int wcount, blocksize, readcount, i;
876 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
884 /* Adjust to read within 4K block boundaries */
885 blocksize = (0x1000 - (0xFFF & address));
887 if (wcount < blocksize)
890 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
891 readcount = blocksize;
895 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
896 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
898 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
899 return ERROR_JTAG_DEVICE_ERROR;
902 nbytes = MIN(readcount, 4);
904 for (i = 0; i < nbytes; i++ )
906 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
919 int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
922 int retval = ERROR_OK;
925 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
927 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
931 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
932 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
933 retval = swjdp_transaction_endcheck(swjdp);
934 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
943 int ahbap_debugport_init(swjdp_common_t *swjdp)
945 u32 idreg, romaddr, dummy;
953 swjdp->ap_csw_value = -1;
954 swjdp->ap_tar_value = -1;
955 swjdp->trans_mode = TRANS_MODE_ATOMIC;
956 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
957 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
958 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
960 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
962 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
963 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
964 if ((retval=jtag_execute_queue())!=ERROR_OK)
967 /* Check that we have debug power domains activated */
968 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
970 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
971 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
972 if ((retval=jtag_execute_queue())!=ERROR_OK)
977 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
979 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
980 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
981 if ((retval=jtag_execute_queue())!=ERROR_OK)
986 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
987 /* With debug power on we can activate OVERRUN checking */
988 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
989 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
990 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
992 dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
993 dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
995 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
1001 char * class_description[16] ={
1003 "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
1004 "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
1006 int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
1010 int romtable_present = 0;
1014 apselold = swjdp->apsel;
1015 dap_ap_select(swjdp, apsel);
1016 dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
1017 dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
1018 swjdp_transaction_endcheck(swjdp);
1019 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1020 mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
1021 command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
1027 command_print(cmd_ctx, "\tType is jtag-ap");
1030 command_print(cmd_ctx, "\tType is mem-ap AHB");
1033 command_print(cmd_ctx, "\tType is mem-ap APB");
1036 command_print(cmd_ctx, "\tUnknown AP-type");
1039 command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
1043 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1046 romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
1047 if (romtable_present)
1049 u32 cid0,cid1,cid2,cid3,memtype,romentry;
1051 /* bit 16 of apid indicates a memory access port */
1054 command_print(cmd_ctx, "\tValid ROM table present");
1058 command_print(cmd_ctx, "\tROM table in legacy format" );
1060 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1061 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
1062 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
1063 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
1064 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
1065 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
1066 swjdp_transaction_endcheck(swjdp);
1067 command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
1070 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1074 command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
1077 /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
1081 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
1082 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
1085 u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
1086 u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
1087 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
1088 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
1089 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
1090 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
1091 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
1092 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
1093 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
1094 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
1095 mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
1096 component_start = component_base - 0x1000*(c_pid4>>4);
1097 command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
1098 command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
1099 command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
1100 command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
1101 /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
1106 command_print(cmd_ctx, "\t\tComponent not present");
1108 command_print(cmd_ctx, "\t\tEnd of ROM table");
1111 } while (romentry>0);
1115 command_print(cmd_ctx, "\tNo ROM table present");
1117 dap_ap_select(swjdp, apselold);