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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (dap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && dap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         size_t nbytes = size * count;
 426         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 427         uint32_t csw_size;
 428         uint32_t address = adr;
 429         int retval;
 430
 431         /* TI BE-32 Quirks mode:
 432          * Reads on big-endian TMS570 behave strangely differently than writes.
 433          * They read from the physical address requested, but with DRW byte-reversed.
 434          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 435          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 436          * so avoid them. */
 437
 438         if (size == 4)
 439                 csw_size = CSW_32BIT;
 440         else if (size == 2)
 441                 csw_size = CSW_16BIT;
 442         else if (size == 1)
 443                 csw_size = CSW_8BIT;
 444         else
 445                 return ERROR_TARGET_UNALIGNED_ACCESS;
 446
 447         if (dap->unaligned_access_bad && (adr % size != 0))
 448                 return ERROR_TARGET_UNALIGNED_ACCESS;
 449
 450         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 451          * over-allocation if packed transfers are going to be used, but determining the real need at
 452          * this point would be messy. */
 453         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 454         uint32_t *read_ptr = read_buf;
 455         if (read_buf == NULL) {
 456                 LOG_ERROR("Failed to allocate read buffer");
 457                 return ERROR_FAIL;
 458         }
 459
 460         retval = dap_setup_accessport_tar(dap, address);
 461         if (retval != ERROR_OK) {
 462                 free(read_buf);
 463                 return retval;
 464         }
 465
 466         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 467          * useful bytes it contains, and their location in the word, depends on the type of transfer
 468          * and alignment. */
 469         while (nbytes > 0) {
 470                 uint32_t this_size = size;
 471
 472                 /* Select packed transfer if possible */
 473                 if (addrinc && dap->packed_transfers && nbytes >= 4
 474                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 475                         this_size = 4;
 476                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 477                 } else {
 478                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 479                 }
 480                 if (retval != ERROR_OK)
 481                         break;
 482
 483                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 484                 if (retval != ERROR_OK)
 485                         break;
 486
 487                 nbytes -= this_size;
 488                 address += this_size;
 489
 490                 /* Rewrite TAR if it wrapped */
 491                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 492                         retval = dap_setup_accessport_tar(dap, address);
 493                         if (retval != ERROR_OK)
 494                                 break;
 495                 }
 496         }
 497
 498         if (retval == ERROR_OK)
 499                 retval = dap_run(dap);
 500
 501         /* Restore state */
 502         address = adr;
 503         nbytes = size * count;
 504         read_ptr = read_buf;
 505
 506         /* If something failed, read TAR to find out how much data was successfully read, so we can
 507          * at least give the caller what we have. */
 508         if (retval != ERROR_OK) {
 509                 uint32_t tar;
 510                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 511                                 && dap_run(dap) == ERROR_OK) {
 512                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 513                         if (nbytes > tar - address)
 514                                 nbytes = tar - address;
 515                 } else {
 516                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 517                         nbytes = 0;
 518                 }
 519         }
 520
 521         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 522         while (nbytes > 0) {
 523                 uint32_t this_size = size;
 524
 525                 if (addrinc && dap->packed_transfers && nbytes >= 4
 526                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 527                         this_size = 4;
 528                 }
 529
 530                 if (dap->ti_be_32_quirks) {
 531                         switch (this_size) {
 532                         case 4:
 533                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                         case 2:
 536                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 537                         case 1:
 538                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 539                         }
 540                 } else {
 541                         switch (this_size) {
 542                         case 4:
 543                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                         case 2:
 546                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 547                         case 1:
 548                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 549                         }
 550                 }
 551
 552                 read_ptr++;
 553                 nbytes -= this_size;
 554         }
 555
 556         free(read_buf);
 557         return retval;
 558 }
 559
 560 /*--------------------------------------------------------------------*/
 561 /*          Wrapping function with selection of AP                    */
 562 /*--------------------------------------------------------------------*/
 563 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 564                 uint32_t address, uint32_t *value)
 565 {
 566         dap_ap_select(swjdp, ap);
 567         return mem_ap_read_u32(swjdp, address, value);
 568 }
 569
 570 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 571                 uint32_t address, uint32_t value)
 572 {
 573         dap_ap_select(swjdp, ap);
 574         return mem_ap_write_u32(swjdp, address, value);
 575 }
 576
 577 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 578                 uint32_t address, uint32_t *value)
 579 {
 580         dap_ap_select(swjdp, ap);
 581         return mem_ap_read_atomic_u32(swjdp, address, value);
 582 }
 583
 584 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 585                 uint32_t address, uint32_t value)
 586 {
 587         dap_ap_select(swjdp, ap);
 588         return mem_ap_write_atomic_u32(swjdp, address, value);
 589 }
 590
 591 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 592                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 593 {
 594         dap_ap_select(swjdp, ap);
 595         return mem_ap_read(swjdp, buffer, size, count, address, true);
 596 }
 597
 598 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 599                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 600 {
 601         dap_ap_select(swjdp, ap);
 602         return mem_ap_write(swjdp, buffer, size, count, address, true);
 603 }
 604
 605 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 606                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 607 {
 608         dap_ap_select(swjdp, ap);
 609         return mem_ap_read(swjdp, buffer, size, count, address, false);
 610 }
 611
 612 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 613                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 614 {
 615         dap_ap_select(swjdp, ap);
 616         return mem_ap_write(swjdp, buffer, size, count, address, false);
 617 }
 618
 619 /*--------------------------------------------------------------------------*/
 620
 621
 622 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 623
 624 /* FIXME don't import ... just initialize as
 625  * part of DAP transport setup
 626 */
 627 extern const struct dap_ops jtag_dp_ops;
 628
 629 /*--------------------------------------------------------------------------*/
 630
 631 /**
 632  * Initialize a DAP.  This sets up the power domains, prepares the DP
 633  * for further use, and arranges to use AP #0 for all AP operations
 634  * until dap_ap-select() changes that policy.
 635  *
 636  * @param dap The DAP being initialized.
 637  *
 638  * @todo Rename this.  We also need an initialization scheme which account
 639  * for SWD transports not just JTAG; that will need to address differences
 640  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 641  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 642  */
 643 int ahbap_debugport_init(struct adiv5_dap *dap)
 644 {
 645         int retval;
 646
 647         LOG_DEBUG(" ");
 648
 649         /* JTAG-DP or SWJ-DP, in JTAG mode
 650          * ... for SWD mode this is patched as part
 651          * of link switchover
 652          */
 653         if (!dap->ops)
 654                 dap->ops = &jtag_dp_ops;
 655
 656         /* Default MEM-AP setup.
 657          *
 658          * REVISIT AP #0 may be an inappropriate default for this.
 659          * Should we probe, or take a hint from the caller?
 660          * Presumably we can ignore the possibility of multiple APs.
 661          */
 662         dap->ap_current = !0;
 663         dap_ap_select(dap, 0);
 664
 665         /* DP initialization */
 666
 667         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 668         if (retval != ERROR_OK)
 669                 return retval;
 670
 671         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674
 675         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 676         if (retval != ERROR_OK)
 677                 return retval;
 678
 679         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 680         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 681         if (retval != ERROR_OK)
 682                 return retval;
 683
 684         /* Check that we have debug power domains activated */
 685         LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 686         retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 687                                       CDBGPWRUPACK, CDBGPWRUPACK,
 688                                       DAP_POWER_DOMAIN_TIMEOUT);
 689         if (retval != ERROR_OK)
 690                 return retval;
 691
 692         LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 693         retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 694                                       CSYSPWRUPACK, CSYSPWRUPACK,
 695                                       DAP_POWER_DOMAIN_TIMEOUT);
 696         if (retval != ERROR_OK)
 697                 return retval;
 698
 699         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 700         if (retval != ERROR_OK)
 701                 return retval;
 702         /* With debug power on we can activate OVERRUN checking */
 703         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 704         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 705         if (retval != ERROR_OK)
 706                 return retval;
 707         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 708         if (retval != ERROR_OK)
 709                 return retval;
 710
 711         /* check that we support packed transfers */
 712         uint32_t csw, cfg;
 713
 714         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 715         if (retval != ERROR_OK)
 716                 return retval;
 717
 718         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 719         if (retval != ERROR_OK)
 720                 return retval;
 721
 722         retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
 723         if (retval != ERROR_OK)
 724                 return retval;
 725
 726         retval = dap_run(dap);
 727         if (retval != ERROR_OK)
 728                 return retval;
 729
 730         if (csw & CSW_ADDRINC_PACKED)
 731                 dap->packed_transfers = true;
 732         else
 733                 dap->packed_transfers = false;
 734
 735         /* Packed transfers on TI BE-32 processors do not work correctly in
 736          * many cases. */
 737         if (dap->ti_be_32_quirks)
 738                 dap->packed_transfers = false;
 739
 740         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 741                         dap->packed_transfers ? "enabled" : "disabled");
 742
 743         /* The ARM ADI spec leaves implementation-defined whether unaligned
 744          * memory accesses work, only work partially, or cause a sticky error.
 745          * On TI BE-32 processors, reads seem to return garbage in some bytes
 746          * and unaligned writes seem to cause a sticky error.
 747          * TODO: it would be nice to have a way to detect whether unaligned
 748          * operations are supported on other processors. */
 749         dap->unaligned_access_bad = dap->ti_be_32_quirks;
 750
 751         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 752                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 753
 754         return ERROR_OK;
 755 }
 756
 757 /* CID interpretation -- see ARM IHI 0029B section 3
 758  * and ARM IHI 0031A table 13-3.
 759  */
 760 static const char *class_description[16] = {
 761         "Reserved", "ROM table", "Reserved", "Reserved",
 762         "Reserved", "Reserved", "Reserved", "Reserved",
 763         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 764         "Reserved", "OptimoDE DESS",
 765         "Generic IP component", "PrimeCell or System component"
 766 };
 767
 768 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 769 {
 770         return cid3 == 0xb1 && cid2 == 0x05
 771                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 772 }
 773
 774 /*
 775  * This function checks the ID for each access port to find the requested Access Port type
 776  */
 777 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 778 {
 779         int ap;
 780
 781         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 782         for (ap = 0; ap <= 255; ap++) {
 783
 784                 /* read the IDR register of the Access Port */
 785                 uint32_t id_val = 0;
 786                 dap_ap_select(dap, ap);
 787
 788                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 789                 if (retval != ERROR_OK)
 790                         return retval;
 791
 792                 retval = dap_run(dap);
 793
 794                 /* IDR bits:
 795                  * 31-28 : Revision
 796                  * 27-24 : JEDEC bank (0x4 for ARM)
 797                  * 23-17 : JEDEC code (0x3B for ARM)
 798                  * 16    : Mem-AP
 799                  * 15-8  : Reserved
 800                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 801                  */
 802
 803                 /* Reading register for a non-existant AP should not cause an error,
 804                  * but just to be sure, try to continue searching if an error does happen.
 805                  */
 806                 if ((retval == ERROR_OK) &&                  /* Register read success */
 807                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 808                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 809
 810                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 811                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 812                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 813                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 814                                                 ap, id_val);
 815
 816                         *ap_num_out = ap;
 817                         return ERROR_OK;
 818                 }
 819         }
 820
 821         LOG_DEBUG("No %s found",
 822                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 823                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 824                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 825         return ERROR_FAIL;
 826 }
 827
 828 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 829                         uint32_t *out_dbgbase, uint32_t *out_apid)
 830 {
 831         uint32_t ap_old;
 832         int retval;
 833         uint32_t dbgbase, apid;
 834
 835         /* AP address is in bits 31:24 of DP_SELECT */
 836         if (ap >= 256)
 837                 return ERROR_COMMAND_SYNTAX_ERROR;
 838
 839         ap_old = dap->ap_current;
 840         dap_ap_select(dap, ap);
 841
 842         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
 843         if (retval != ERROR_OK)
 844                 return retval;
 845         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
 846         if (retval != ERROR_OK)
 847                 return retval;
 848         retval = dap_run(dap);
 849         if (retval != ERROR_OK)
 850                 return retval;
 851
 852         /* Excavate the device ID code */
 853         struct jtag_tap *tap = dap->jtag_info->tap;
 854         while (tap != NULL) {
 855                 if (tap->hasidcode)
 856                         break;
 857                 tap = tap->next_tap;
 858         }
 859         if (tap == NULL || !tap->hasidcode)
 860                 return ERROR_OK;
 861
 862         dap_ap_select(dap, ap_old);
 863
 864         /* The asignment happens only here to prevent modification of these
 865          * values before they are certain. */
 866         *out_dbgbase = dbgbase;
 867         *out_apid = apid;
 868
 869         return ERROR_OK;
 870 }
 871
 872 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 873                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
 874 {
 875         uint32_t ap_old;
 876         uint32_t romentry, entry_offset = 0, component_base, devtype;
 877         int retval = ERROR_FAIL;
 878
 879         if (ap >= 256)
 880                 return ERROR_COMMAND_SYNTAX_ERROR;
 881
 882         ap_old = dap->ap_current;
 883         dap_ap_select(dap, ap);
 884
 885         do {
 886                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
 887                                                 entry_offset, &romentry);
 888                 if (retval != ERROR_OK)
 889                         return retval;
 890
 891                 component_base = (dbgbase & 0xFFFFF000)
 892                         + (romentry & 0xFFFFF000);
 893
 894                 if (romentry & 0x1) {
 895                         retval = mem_ap_read_atomic_u32(dap,
 896                                         (component_base & 0xfffff000) | 0xfcc,
 897                                         &devtype);
 898                         if (retval != ERROR_OK)
 899                                 return retval;
 900                         if ((devtype & 0xff) == type) {
 901                                 *addr = component_base;
 902                                 retval = ERROR_OK;
 903                                 break;
 904                         }
 905                 }
 906                 entry_offset += 4;
 907         } while (romentry > 0);
 908
 909         dap_ap_select(dap, ap_old);
 910
 911         return retval;
 912 }
 913
 914 static int dap_rom_display(struct command_context *cmd_ctx,
 915                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
 916 {
 917         int retval;
 918         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 919         uint16_t entry_offset;
 920         char tabs[7] = "";
 921
 922         if (depth > 16) {
 923                 command_print(cmd_ctx, "\tTables too deep");
 924                 return ERROR_FAIL;
 925         }
 926
 927         if (depth)
 928                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 929
 930         /* bit 16 of apid indicates a memory access port */
 931         if (dbgbase & 0x02)
 932                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 933         else
 934                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 935
 936         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 937         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 938         if (retval != ERROR_OK)
 939                 return retval;
 940         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 941         if (retval != ERROR_OK)
 942                 return retval;
 943         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 944         if (retval != ERROR_OK)
 945                 return retval;
 946         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 947         if (retval != ERROR_OK)
 948                 return retval;
 949         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 950         if (retval != ERROR_OK)
 951                 return retval;
 952         retval = dap_run(dap);
 953         if (retval != ERROR_OK)
 954                 return retval;
 955
 956         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 957                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 958                                 ", CID2 0x%02x"
 959                                 ", CID1 0x%02x"
 960                                 ", CID0 0x%02x",
 961                                 tabs,
 962                                 (unsigned)cid3, (unsigned)cid2,
 963                                 (unsigned)cid1, (unsigned)cid0);
 964         if (memtype & 0x01)
 965                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 966         else
 967                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 968
 969         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 970         for (entry_offset = 0; ; entry_offset += 4) {
 971                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 972                 if (retval != ERROR_OK)
 973                         return retval;
 974                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 975                                 tabs, entry_offset, romentry);
 976                 if (romentry & 0x01) {
 977                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 978                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 979                         uint32_t component_base;
 980                         unsigned part_num;
 981                         char *type, *full;
 982
 983                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 984
 985                         /* IDs are in last 4K section */
 986                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
 987                         if (retval != ERROR_OK) {
 988                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
 989                                               ", the corresponding core might be turned off", tabs, component_base);
 990                                 continue;
 991                         }
 992                         c_pid0 &= 0xff;
 993                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
 994                         if (retval != ERROR_OK)
 995                                 return retval;
 996                         c_pid1 &= 0xff;
 997                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
 998                         if (retval != ERROR_OK)
 999                                 return retval;
1000                         c_pid2 &= 0xff;
1001                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1002                         if (retval != ERROR_OK)
1003                                 return retval;
1004                         c_pid3 &= 0xff;
1005                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1006                         if (retval != ERROR_OK)
1007                                 return retval;
1008                         c_pid4 &= 0xff;
1009
1010                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1011                         if (retval != ERROR_OK)
1012                                 return retval;
1013                         c_cid0 &= 0xff;
1014                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1015                         if (retval != ERROR_OK)
1016                                 return retval;
1017                         c_cid1 &= 0xff;
1018                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1019                         if (retval != ERROR_OK)
1020                                 return retval;
1021                         c_cid2 &= 0xff;
1022                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1023                         if (retval != ERROR_OK)
1024                                 return retval;
1025                         c_cid3 &= 0xff;
1026
1027                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1028                                       "start address 0x%" PRIx32, component_base,
1029                                       /* component may take multiple 4K pages */
1030                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1031                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1032                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1033                                         /* See ARM IHI 0029B Table 3-3 */
1034                                         class_description[(c_cid1 >> 4) & 0xf]);
1035
1036                         /* CoreSight component? */
1037                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1038                                 uint32_t devtype;
1039                                 unsigned minor;
1040                                 char *major = "Reserved", *subtype = "Reserved";
1041
1042                                 retval = mem_ap_read_atomic_u32(dap,
1043                                                 (component_base & 0xfffff000) | 0xfcc,
1044                                                 &devtype);
1045                                 if (retval != ERROR_OK)
1046                                         return retval;
1047                                 minor = (devtype >> 4) & 0x0f;
1048                                 switch (devtype & 0x0f) {
1049                                 case 0:
1050                                         major = "Miscellaneous";
1051                                         switch (minor) {
1052                                         case 0:
1053                                                 subtype = "other";
1054                                                 break;
1055                                         case 4:
1056                                                 subtype = "Validation component";
1057                                                 break;
1058                                         }
1059                                         break;
1060                                 case 1:
1061                                         major = "Trace Sink";
1062                                         switch (minor) {
1063                                         case 0:
1064                                                 subtype = "other";
1065                                                 break;
1066                                         case 1:
1067                                                 subtype = "Port";
1068                                                 break;
1069                                         case 2:
1070                                                 subtype = "Buffer";
1071                                                 break;
1072                                         }
1073                                         break;
1074                                 case 2:
1075                                         major = "Trace Link";
1076                                         switch (minor) {
1077                                         case 0:
1078                                                 subtype = "other";
1079                                                 break;
1080                                         case 1:
1081                                                 subtype = "Funnel, router";
1082                                                 break;
1083                                         case 2:
1084                                                 subtype = "Filter";
1085                                                 break;
1086                                         case 3:
1087                                                 subtype = "FIFO, buffer";
1088                                                 break;
1089                                         }
1090                                         break;
1091                                 case 3:
1092                                         major = "Trace Source";
1093                                         switch (minor) {
1094                                         case 0:
1095                                                 subtype = "other";
1096                                                 break;
1097                                         case 1:
1098                                                 subtype = "Processor";
1099                                                 break;
1100                                         case 2:
1101                                                 subtype = "DSP";
1102                                                 break;
1103                                         case 3:
1104                                                 subtype = "Engine/Coprocessor";
1105                                                 break;
1106                                         case 4:
1107                                                 subtype = "Bus";
1108                                                 break;
1109                                         }
1110                                         break;
1111                                 case 4:
1112                                         major = "Debug Control";
1113                                         switch (minor) {
1114                                         case 0:
1115                                                 subtype = "other";
1116                                                 break;
1117                                         case 1:
1118                                                 subtype = "Trigger Matrix";
1119                                                 break;
1120                                         case 2:
1121                                                 subtype = "Debug Auth";
1122                                                 break;
1123                                         }
1124                                         break;
1125                                 case 5:
1126                                         major = "Debug Logic";
1127                                         switch (minor) {
1128                                         case 0:
1129                                                 subtype = "other";
1130                                                 break;
1131                                         case 1:
1132                                                 subtype = "Processor";
1133                                                 break;
1134                                         case 2:
1135                                                 subtype = "DSP";
1136                                                 break;
1137                                         case 3:
1138                                                 subtype = "Engine/Coprocessor";
1139                                                 break;
1140                                         }
1141                                         break;
1142                                 }
1143                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1144                                                 (uint8_t)(devtype & 0xff),
1145                                                 major, subtype);
1146                                 /* REVISIT also show 0xfc8 DevId */
1147                         }
1148
1149                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1150                                 command_print(cmd_ctx,
1151                                                 "\t\tCID3 0%02x"
1152                                                 ", CID2 0%02x"
1153                                                 ", CID1 0%02x"
1154                                                 ", CID0 0%02x",
1155                                                 (int)c_cid3,
1156                                                 (int)c_cid2,
1157                                                 (int)c_cid1,
1158                                                 (int)c_cid0);
1159                         command_print(cmd_ctx,
1160                                 "\t\tPeripheral ID[4..0] = hex "
1161                                 "%02x %02x %02x %02x %02x",
1162                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1163                                 (int)c_pid1, (int)c_pid0);
1164
1165                         /* Part number interpretations are from Cortex
1166                          * core specs, the CoreSight components TRM
1167                          * (ARM DDI 0314H), CoreSight System Design
1168                          * Guide (ARM DGI 0012D) and ETM specs; also
1169                          * from chip observation (e.g. TI SDTI).
1170                          */
1171                         part_num = (c_pid0 & 0xff);
1172                         part_num |= (c_pid1 & 0x0f) << 8;
1173                         switch (part_num) {
1174                         case 0x000:
1175                                 type = "Cortex-M3 NVIC";
1176                                 full = "(Interrupt Controller)";
1177                                 break;
1178                         case 0x001:
1179                                 type = "Cortex-M3 ITM";
1180                                 full = "(Instrumentation Trace Module)";
1181                                 break;
1182                         case 0x002:
1183                                 type = "Cortex-M3 DWT";
1184                                 full = "(Data Watchpoint and Trace)";
1185                                 break;
1186                         case 0x003:
1187                                 type = "Cortex-M3 FBP";
1188                                 full = "(Flash Patch and Breakpoint)";
1189                                 break;
1190                         case 0x00c:
1191                                 type = "Cortex-M4 SCS";
1192                                 full = "(System Control Space)";
1193                                 break;
1194                         case 0x00d:
1195                                 type = "CoreSight ETM11";
1196                                 full = "(Embedded Trace)";
1197                                 break;
1198                         /* case 0x113: what? */
1199                         case 0x120:             /* from OMAP3 memmap */
1200                                 type = "TI SDTI";
1201                                 full = "(System Debug Trace Interface)";
1202                                 break;
1203                         case 0x343:             /* from OMAP3 memmap */
1204                                 type = "TI DAPCTL";
1205                                 full = "";
1206                                 break;
1207                         case 0x906:
1208                                 type = "Coresight CTI";
1209                                 full = "(Cross Trigger)";
1210                                 break;
1211                         case 0x907:
1212                                 type = "Coresight ETB";
1213                                 full = "(Trace Buffer)";
1214                                 break;
1215                         case 0x908:
1216                                 type = "Coresight CSTF";
1217                                 full = "(Trace Funnel)";
1218                                 break;
1219                         case 0x910:
1220                                 type = "CoreSight ETM9";
1221                                 full = "(Embedded Trace)";
1222                                 break;
1223                         case 0x912:
1224                                 type = "Coresight TPIU";
1225                                 full = "(Trace Port Interface Unit)";
1226                                 break;
1227                         case 0x913:
1228                                 type = "Coresight ITM";
1229                                 full = "(Instrumentation Trace Macrocell)";
1230                                 break;
1231                         case 0x921:
1232                                 type = "Cortex-A8 ETM";
1233                                 full = "(Embedded Trace)";
1234                                 break;
1235                         case 0x922:
1236                                 type = "Cortex-A8 CTI";
1237                                 full = "(Cross Trigger)";
1238                                 break;
1239                         case 0x923:
1240                                 type = "Cortex-M3 TPIU";
1241                                 full = "(Trace Port Interface Unit)";
1242                                 break;
1243                         case 0x924:
1244                                 type = "Cortex-M3 ETM";
1245                                 full = "(Embedded Trace)";
1246                                 break;
1247                         case 0x925:
1248                                 type = "Cortex-M4 ETM";
1249                                 full = "(Embedded Trace)";
1250                                 break;
1251                         case 0x930:
1252                                 type = "Cortex-R4 ETM";
1253                                 full = "(Embedded Trace)";
1254                                 break;
1255                         case 0x950:
1256                                 type = "CoreSight Component";
1257                                 full = "(unidentified Cortex-A9 component)";
1258                                 break;
1259                         case 0x9a0:
1260                                 type = "CoreSight PMU";
1261                                 full = "(Performance Monitoring Unit)";
1262                                 break;
1263                         case 0x9a1:
1264                                 type = "Cortex-M4 TPUI";
1265                                 full = "(Trace Port Interface Unit)";
1266                                 break;
1267                         case 0xc08:
1268                                 type = "Cortex-A8 Debug";
1269                                 full = "(Debug Unit)";
1270                                 break;
1271                         case 0xc09:
1272                                 type = "Cortex-A9 Debug";
1273                                 full = "(Debug Unit)";
1274                                 break;
1275                         default:
1276                                 type = "-*- unrecognized -*-";
1277                                 full = "";
1278                                 break;
1279                         }
1280                         command_print(cmd_ctx, "\t\tPart is %s %s",
1281                                         type, full);
1282
1283                         /* ROM Table? */
1284                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1285                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1286                                 if (retval != ERROR_OK)
1287                                         return retval;
1288                         }
1289                 } else {
1290                         if (romentry)
1291                                 command_print(cmd_ctx, "\t\tComponent not present");
1292                         else
1293                                 break;
1294                 }
1295         }
1296         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1297         return ERROR_OK;
1298 }
1299
1300 static int dap_info_command(struct command_context *cmd_ctx,
1301                 struct adiv5_dap *dap, int ap)
1302 {
1303         int retval;
1304         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1305         int romtable_present = 0;
1306         uint8_t mem_ap;
1307         uint32_t ap_old;
1308
1309         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1310         if (retval != ERROR_OK)
1311                 return retval;
1312
1313         ap_old = dap->ap_current;
1314         dap_ap_select(dap, ap);
1315
1316         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1317         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1318         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1319         if (apid) {
1320                 switch (apid&0x0F) {
1321                         case 0:
1322                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1323                                 break;
1324                         case 1:
1325                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1326                                 break;
1327                         case 2:
1328                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1329                                 break;
1330                         default:
1331                                 command_print(cmd_ctx, "\tUnknown AP type");
1332                                 break;
1333                 }
1334
1335                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1336                  * not a ROM table ... or have no such components at all.
1337                  */
1338                 if (mem_ap)
1339                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1340         } else
1341                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1342
1343         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1344         if (romtable_present) {
1345                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1346         } else
1347                 command_print(cmd_ctx, "\tNo ROM table present");
1348         dap_ap_select(dap, ap_old);
1349
1350         return ERROR_OK;
1351 }
1352
1353 COMMAND_HANDLER(handle_dap_info_command)
1354 {
1355         struct target *target = get_current_target(CMD_CTX);
1356         struct arm *arm = target_to_arm(target);
1357         struct adiv5_dap *dap = arm->dap;
1358         uint32_t apsel;
1359
1360         switch (CMD_ARGC) {
1361         case 0:
1362                 apsel = dap->apsel;
1363                 break;
1364         case 1:
1365                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1366                 break;
1367         default:
1368                 return ERROR_COMMAND_SYNTAX_ERROR;
1369         }
1370
1371         return dap_info_command(CMD_CTX, dap, apsel);
1372 }
1373
1374 COMMAND_HANDLER(dap_baseaddr_command)
1375 {
1376         struct target *target = get_current_target(CMD_CTX);
1377         struct arm *arm = target_to_arm(target);
1378         struct adiv5_dap *dap = arm->dap;
1379
1380         uint32_t apsel, baseaddr;
1381         int retval;
1382
1383         switch (CMD_ARGC) {
1384         case 0:
1385                 apsel = dap->apsel;
1386                 break;
1387         case 1:
1388                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1389                 /* AP address is in bits 31:24 of DP_SELECT */
1390                 if (apsel >= 256)
1391                         return ERROR_COMMAND_SYNTAX_ERROR;
1392                 break;
1393         default:
1394                 return ERROR_COMMAND_SYNTAX_ERROR;
1395         }
1396
1397         dap_ap_select(dap, apsel);
1398
1399         /* NOTE:  assumes we're talking to a MEM-AP, which
1400          * has a base address.  There are other kinds of AP,
1401          * though they're not common for now.  This should
1402          * use the ID register to verify it's a MEM-AP.
1403          */
1404         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1405         if (retval != ERROR_OK)
1406                 return retval;
1407         retval = dap_run(dap);
1408         if (retval != ERROR_OK)
1409                 return retval;
1410
1411         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1412
1413         return retval;
1414 }
1415
1416 COMMAND_HANDLER(dap_memaccess_command)
1417 {
1418         struct target *target = get_current_target(CMD_CTX);
1419         struct arm *arm = target_to_arm(target);
1420         struct adiv5_dap *dap = arm->dap;
1421
1422         uint32_t memaccess_tck;
1423
1424         switch (CMD_ARGC) {
1425         case 0:
1426                 memaccess_tck = dap->memaccess_tck;
1427                 break;
1428         case 1:
1429                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1430                 break;
1431         default:
1432                 return ERROR_COMMAND_SYNTAX_ERROR;
1433         }
1434         dap->memaccess_tck = memaccess_tck;
1435
1436         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1437                         dap->memaccess_tck);
1438
1439         return ERROR_OK;
1440 }
1441
1442 COMMAND_HANDLER(dap_apsel_command)
1443 {
1444         struct target *target = get_current_target(CMD_CTX);
1445         struct arm *arm = target_to_arm(target);
1446         struct adiv5_dap *dap = arm->dap;
1447
1448         uint32_t apsel, apid;
1449         int retval;
1450
1451         switch (CMD_ARGC) {
1452         case 0:
1453                 apsel = 0;
1454                 break;
1455         case 1:
1456                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1457                 /* AP address is in bits 31:24 of DP_SELECT */
1458                 if (apsel >= 256)
1459                         return ERROR_COMMAND_SYNTAX_ERROR;
1460                 break;
1461         default:
1462                 return ERROR_COMMAND_SYNTAX_ERROR;
1463         }
1464
1465         dap->apsel = apsel;
1466         dap_ap_select(dap, apsel);
1467
1468         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1469         if (retval != ERROR_OK)
1470                 return retval;
1471         retval = dap_run(dap);
1472         if (retval != ERROR_OK)
1473                 return retval;
1474
1475         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1476                         apsel, apid);
1477
1478         return retval;
1479 }
1480
1481 COMMAND_HANDLER(dap_apcsw_command)
1482 {
1483         struct target *target = get_current_target(CMD_CTX);
1484         struct arm *arm = target_to_arm(target);
1485         struct adiv5_dap *dap = arm->dap;
1486
1487         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1488
1489         switch (CMD_ARGC) {
1490         case 0:
1491                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1492                         (dap->apsel), apcsw);
1493                 break;
1494         case 1:
1495                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1496                 /* AP address is in bits 31:24 of DP_SELECT */
1497                 if (sprot > 1)
1498                         return ERROR_COMMAND_SYNTAX_ERROR;
1499                 if (sprot)
1500                         apcsw |= CSW_SPROT;
1501                 else
1502                         apcsw &= ~CSW_SPROT;
1503                 break;
1504         default:
1505                 return ERROR_COMMAND_SYNTAX_ERROR;
1506         }
1507         dap->apcsw[dap->apsel] = apcsw;
1508
1509         return 0;
1510 }
1511
1512
1513
1514 COMMAND_HANDLER(dap_apid_command)
1515 {
1516         struct target *target = get_current_target(CMD_CTX);
1517         struct arm *arm = target_to_arm(target);
1518         struct adiv5_dap *dap = arm->dap;
1519
1520         uint32_t apsel, apid;
1521         int retval;
1522
1523         switch (CMD_ARGC) {
1524         case 0:
1525                 apsel = dap->apsel;
1526                 break;
1527         case 1:
1528                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1529                 /* AP address is in bits 31:24 of DP_SELECT */
1530                 if (apsel >= 256)
1531                         return ERROR_COMMAND_SYNTAX_ERROR;
1532                 break;
1533         default:
1534                 return ERROR_COMMAND_SYNTAX_ERROR;
1535         }
1536
1537         dap_ap_select(dap, apsel);
1538
1539         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1540         if (retval != ERROR_OK)
1541                 return retval;
1542         retval = dap_run(dap);
1543         if (retval != ERROR_OK)
1544                 return retval;
1545
1546         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1547
1548         return retval;
1549 }
1550
1551 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1552 {
1553         struct target *target = get_current_target(CMD_CTX);
1554         struct arm *arm = target_to_arm(target);
1555         struct adiv5_dap *dap = arm->dap;
1556
1557         uint32_t enable = dap->ti_be_32_quirks;
1558
1559         switch (CMD_ARGC) {
1560         case 0:
1561                 break;
1562         case 1:
1563                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1564                 if (enable > 1)
1565                         return ERROR_COMMAND_SYNTAX_ERROR;
1566                 break;
1567         default:
1568                 return ERROR_COMMAND_SYNTAX_ERROR;
1569         }
1570         dap->ti_be_32_quirks = enable;
1571         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1572                 enable ? "enabled" : "disabled");
1573
1574         return 0;
1575 }
1576
1577 static const struct command_registration dap_commands[] = {
1578         {
1579                 .name = "info",
1580                 .handler = handle_dap_info_command,
1581                 .mode = COMMAND_EXEC,
1582                 .help = "display ROM table for MEM-AP "
1583                         "(default currently selected AP)",
1584                 .usage = "[ap_num]",
1585         },
1586         {
1587                 .name = "apsel",
1588                 .handler = dap_apsel_command,
1589                 .mode = COMMAND_EXEC,
1590                 .help = "Set the currently selected AP (default 0) "
1591                         "and display the result",
1592                 .usage = "[ap_num]",
1593         },
1594         {
1595                 .name = "apcsw",
1596                 .handler = dap_apcsw_command,
1597                 .mode = COMMAND_EXEC,
1598                 .help = "Set csw access bit ",
1599                 .usage = "[sprot]",
1600         },
1601
1602         {
1603                 .name = "apid",
1604                 .handler = dap_apid_command,
1605                 .mode = COMMAND_EXEC,
1606                 .help = "return ID register from AP "
1607                         "(default currently selected AP)",
1608                 .usage = "[ap_num]",
1609         },
1610         {
1611                 .name = "baseaddr",
1612                 .handler = dap_baseaddr_command,
1613                 .mode = COMMAND_EXEC,
1614                 .help = "return debug base address from MEM-AP "
1615                         "(default currently selected AP)",
1616                 .usage = "[ap_num]",
1617         },
1618         {
1619                 .name = "memaccess",
1620                 .handler = dap_memaccess_command,
1621                 .mode = COMMAND_EXEC,
1622                 .help = "set/get number of extra tck for MEM-AP memory "
1623                         "bus access [0-255]",
1624                 .usage = "[cycles]",
1625         },
1626         {
1627                 .name = "ti_be_32_quirks",
1628                 .handler = dap_ti_be_32_quirks_command,
1629                 .mode = COMMAND_CONFIG,
1630                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1631                 .usage = "[enable]",
1632         },
1633         COMMAND_REGISTRATION_DONE
1634 };
1635
1636 const struct command_registration dap_command_handlers[] = {
1637         {
1638                 .name = "dap",
1639                 .mode = COMMAND_EXEC,
1640                 .help = "DAP command group",
1641                 .usage = "",
1642                 .chain = dap_commands,
1643         },
1644         COMMAND_REGISTRATION_DONE
1645 };