1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x1
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x4
50 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
52 /* A[3:0] for DP registers; A[1:0] are always zero.
53 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
54 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
55 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
57 #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
58 #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
59 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
60 #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
61 #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
62 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
63 #define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
65 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
66 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
68 /* Fields of the DP's AP ABORT register */
69 #define DAPABORT (1UL << 0)
70 #define STKCMPCLR (1UL << 1) /* SWD-only */
71 #define STKERRCLR (1UL << 2) /* SWD-only */
72 #define WDERRCLR (1UL << 3) /* SWD-only */
73 #define ORUNERRCLR (1UL << 4) /* SWD-only */
75 /* Fields of the DP's CTRL/STAT register */
76 #define CORUNDETECT (1UL << 0)
77 #define SSTICKYORUN (1UL << 1)
78 /* 3:2 - transaction mode (e.g. pushed compare) */
79 #define SSTICKYCMP (1UL << 4)
80 #define SSTICKYERR (1UL << 5)
81 #define READOK (1UL << 6) /* SWD-only */
82 #define WDATAERR (1UL << 7) /* SWD-only */
83 /* 11:8 - mask lanes for pushed compare or verify ops */
84 /* 21:12 - transaction counter */
85 #define CDBGRSTREQ (1UL << 26)
86 #define CDBGRSTACK (1UL << 27)
87 #define CDBGPWRUPREQ (1UL << 28)
88 #define CDBGPWRUPACK (1UL << 29)
89 #define CSYSPWRUPREQ (1UL << 30)
90 #define CSYSPWRUPACK (1UL << 31)
92 /* MEM-AP register addresses */
93 #define MEM_AP_REG_CSW 0x00
94 #define MEM_AP_REG_TAR 0x04
95 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
96 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
97 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
98 #define MEM_AP_REG_BD1 0x14
99 #define MEM_AP_REG_BD2 0x18
100 #define MEM_AP_REG_BD3 0x1C
101 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
102 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
103 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
104 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
105 /* Generic AP register address */
106 #define AP_REG_IDR 0xFC /* RO: Identification Register */
108 /* Fields of the MEM-AP's CSW register */
112 #define CSW_ADDRINC_MASK (3UL << 4)
113 #define CSW_ADDRINC_OFF 0UL
114 #define CSW_ADDRINC_SINGLE (1UL << 4)
115 #define CSW_ADDRINC_PACKED (2UL << 4)
116 #define CSW_DEVICE_EN (1UL << 6)
117 #define CSW_TRIN_PROG (1UL << 7)
118 #define CSW_SPIDEN (1UL << 23)
119 /* 30:24 - implementation-defined! */
120 #define CSW_HPROT (1UL << 25) /* ? */
121 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
122 #define CSW_SPROT (1UL << 30)
123 #define CSW_DBGSWENABLE (1UL << 31)
126 * This represents an ARM Debug Interface (v5) Access Port (AP).
127 * Most common is a MEM-AP, for memory access.
131 * Default value for (MEM-AP) AP_REG_CSW register.
133 uint32_t csw_default;
136 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
137 * configure an access mode, such as autoincrementing AP_REG_TAR during
138 * word access. "-1" indicates no cached value.
143 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
144 * configure the address being read or written
145 * "-1" indicates no cached value.
150 * Configures how many extra tck clocks are added after starting a
151 * MEM-AP access before we try to read its status (and/or result).
153 uint32_t memaccess_tck;
155 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
156 uint32_t tar_autoincr_block;
158 /* true if packed transfers are supported by the MEM-AP */
159 bool packed_transfers;
161 /* true if unaligned memory access is not supported by the MEM-AP */
162 bool unaligned_access_bad;
167 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
168 * A DAP has two types of component: one Debug Port (DP), which is a
169 * transport agent; and at least one Access Port (AP), controlling
172 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
173 * Accordingly, this interface is responsible for hiding the transport
174 * differences so upper layer code can largely ignore them.
176 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
177 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
178 * a choice made at board design time (by only using the SWD pins), or
179 * as part of setting up a debug session (if all the dual-role JTAG/SWD
180 * signals are available).
183 const struct dap_ops *ops;
185 struct arm_jtag *jtag_info;
187 uint32_t dp_ctrl_stat;
189 struct adiv5_ap ap[256];
191 /* The current manually selected AP by the "dap apsel" command */
195 * Cache for DP_SELECT bits identifying the current AP. A DAP may
196 * connect to multiple APs, such as one MEM-AP for general access,
197 * another reserved for accessing debug modules, and a JTAG-DP.
198 * "-1" indicates no cached value.
203 * Cache for DP_SELECT bits identifying the current four-word AP
204 * register bank. This caches AP register addresss bits 7:4; JTAG
205 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
206 * "-1" indicates no cached value.
208 uint32_t ap_bank_value;
211 * Cache for DP_SELECT bits identifying the current four-word DP
212 * register bank. This caches DP register addresss bits 7:4; JTAG
213 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
215 uint32_t dp_bank_value;
217 /* information about current pending SWjDP-AHBAP transaction */
221 * Holds the pointer to the destination word for the last queued read,
222 * for use with posted AP read sequence optimization.
226 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
227 * despite lack of support in the ARMv7 architecture. Memory access through
228 * the AHB-AP has strange byte ordering these processors, and we need to
229 * swizzle appropriately. */
230 bool ti_be_32_quirks;
233 * Signals that an attempt to reestablish communication afresh
234 * should be performed before the next access.
240 * Transport-neutral representation of queued DAP transactions, supporting
241 * both JTAG and SWD transports. All submitted transactions are logically
242 * queued, until the queue is executed by run(). Some implementations might
243 * execute transactions as soon as they're submitted, but no status is made
244 * available until run().
247 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
248 * code may need to care about the difference in some cases.
252 /** DP register read. */
253 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
255 /** DP register write. */
256 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
259 /** AP register read. */
260 int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
262 /** AP register write. */
263 int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
266 /** AP operation abort. */
267 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
269 /** Executes all queued DAP operations. */
270 int (*run)(struct adiv5_dap *dap);
277 AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */
278 AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */
279 AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
283 * Queue a DP register read.
284 * Note that not all DP registers are readable; also, that JTAG and SWD
285 * have slight differences in DP register support.
287 * @param dap The DAP used for reading.
288 * @param reg The two-bit number of the DP register being read.
289 * @param data Pointer saying where to store the register's value
290 * (in host endianness).
292 * @return ERROR_OK for success, else a fault code.
294 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
295 unsigned reg, uint32_t *data)
297 assert(dap->ops != NULL);
298 return dap->ops->queue_dp_read(dap, reg, data);
302 * Queue a DP register write.
303 * Note that not all DP registers are writable; also, that JTAG and SWD
304 * have slight differences in DP register support.
306 * @param dap The DAP used for writing.
307 * @param reg The two-bit number of the DP register being written.
308 * @param data Value being written (host endianness)
310 * @return ERROR_OK for success, else a fault code.
312 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
313 unsigned reg, uint32_t data)
315 assert(dap->ops != NULL);
316 return dap->ops->queue_dp_write(dap, reg, data);
320 * Queue an AP register read.
322 * @param dap The DAP used for reading.
323 * @param reg The number of the AP register being read.
324 * @param data Pointer saying where to store the register's value
325 * (in host endianness).
327 * @return ERROR_OK for success, else a fault code.
329 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
330 unsigned reg, uint32_t *data)
332 assert(dap->ops != NULL);
333 return dap->ops->queue_ap_read(dap, reg, data);
337 * Queue an AP register write.
339 * @param dap The DAP used for writing.
340 * @param reg The number of the AP register being written.
341 * @param data Value being written (host endianness)
343 * @return ERROR_OK for success, else a fault code.
345 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
346 unsigned reg, uint32_t data)
348 assert(dap->ops != NULL);
349 return dap->ops->queue_ap_write(dap, reg, data);
353 * Queue an AP abort operation. The current AP transaction is aborted,
354 * including any update of the transaction counter. The AP is left in
355 * an unknown state (so it must be re-initialized). For use only after
356 * the AP has reported WAIT status for an extended period.
358 * @param dap The DAP used for writing.
359 * @param ack Pointer to where transaction status will be stored.
361 * @return ERROR_OK for success, else a fault code.
363 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
365 assert(dap->ops != NULL);
366 return dap->ops->queue_ap_abort(dap, ack);
370 * Perform all queued DAP operations, and clear any errors posted in the
371 * CTRL_STAT register when they are done. Note that if more than one AP
372 * operation will be queued, one of the first operations in the queue
373 * should probably enable CORUNDETECT in the CTRL/STAT register.
375 * @param dap The DAP used.
377 * @return ERROR_OK for success, else a fault code.
379 static inline int dap_run(struct adiv5_dap *dap)
381 assert(dap->ops != NULL);
382 return dap->ops->run(dap);
385 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
390 retval = dap_queue_dp_read(dap, reg, value);
391 if (retval != ERROR_OK)
397 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
398 uint32_t mask, uint32_t value, int timeout)
401 assert((value & mask) == value);
405 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
408 ret = dap_dp_read_atomic(dap, reg, ®val);
412 if ((regval & mask) == value)
419 LOG_DEBUG("DAP: poll %x timeout", reg);
426 /** Accessor for currently selected DAP-AP number (0..255) */
427 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
429 return (uint8_t)(swjdp->ap_current >> 24);
432 /* AP selection applies to future AP transactions */
433 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
435 /* Queued AP transactions */
436 int dap_setup_accessport(struct adiv5_dap *swjdp,
437 uint32_t csw, uint32_t tar);
439 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
440 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
441 uint32_t address, uint32_t *value);
442 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
443 uint32_t address, uint32_t value);
445 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
446 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
447 uint32_t address, uint32_t *value);
448 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
449 uint32_t address, uint32_t value);
451 /* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
452 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
453 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
454 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
455 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
457 /* Synchronous, non-incrementing buffer functions for accessing fifos, with
459 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
460 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
461 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
462 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
464 /* Create DAP struct */
465 struct adiv5_dap *dap_init(void);
467 /* Initialisation of the debug system, power domains and registers */
468 int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
470 /* Probe the AP for ROM Table location */
471 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
472 uint32_t *dbgbase, uint32_t *apid);
474 /* Probe Access Ports to find a particular type */
475 int dap_find_ap(struct adiv5_dap *dap,
476 enum ap_type type_to_find,
477 uint8_t *ap_num_out);
479 /* Lookup CoreSight component */
480 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
481 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
485 /* Put debug link into SWD mode */
486 int dap_to_swd(struct target *target);
488 /* Put debug link into JTAG mode */
489 int dap_to_jtag(struct target *target);
491 extern const struct command_registration dap_command_handlers[];