1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef ARM_DISASSEMBLER_H
21 #define ARM_DISASSEMBLER_H
25 enum arm_instruction_type
27 ARM_UNKNOWN_INSTUCTION,
29 /* Branch instructions */
35 /* Data processing instructions */
53 /* Load/store instructions */
74 /* Status register access instructions */
78 /* Multiply instructions */
86 /* Miscellaneous instructions */
89 /* Exception generating instructions */
93 /* Coprocessor instructions */
100 /* Semaphore instructions */
104 /* Enhanced DSP extensions */
120 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
123 typedef struct arm_instruction_s
125 enum arm_instruction_type type;
134 extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
136 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
138 #endif /* ARM_DISASSEMBLER_H */