2 * Copyright (C) 2009 by David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include "armv4_5.h" /* REVISIT to become arm.h */
32 * Implements various ARM DPM operations using architectural debug registers.
33 * These routines layer over core-specific communication methods to cope with
34 * implementation differences between cores like ARM1136 and Cortex-A8.
41 /* Read coprocessor */
42 static int dpm_mrc(struct target *target, int cpnum,
43 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
46 struct arm *arm = target_to_arm(target);
47 struct arm_dpm *dpm = arm->dpm;
50 retval = dpm->prepare(dpm);
51 if (retval != ERROR_OK)
54 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
56 /* read coprocessor register into R0; return via DCC */
57 retval = dpm->instr_read_data_r0(dpm,
58 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
61 /* (void) */ dpm->finish(dpm);
65 static int dpm_mcr(struct target *target, int cpnum,
66 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
69 struct arm *arm = target_to_arm(target);
70 struct arm_dpm *dpm = arm->dpm;
73 retval = dpm->prepare(dpm);
74 if (retval != ERROR_OK)
77 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
79 /* read DCC into r0; then write coprocessor register from R0 */
80 retval = dpm->instr_write_data_r0(dpm,
81 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
84 /* (void) */ dpm->finish(dpm);
89 * Register access utilities
92 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
93 * Routines *must* restore the original mode before returning!!
95 static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
100 /* restore previous mode */
101 if (mode == ARMV4_5_MODE_ANY)
102 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
104 /* else force to the specified mode */
108 retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
110 if (dpm->instr_cpsr_sync)
111 retval = dpm->instr_cpsr_sync(dpm);
116 /* just read the register -- rely on the core mode being right */
117 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
124 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
125 retval = dpm->instr_read_data_dcc(dpm,
126 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
130 /* "MOV r0, pc"; then return via DCC */
131 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
133 /* NOTE: this seems like a slightly awkward place to update
134 * this value ... but if the PC gets written (the only way
135 * to change what we compute), the arch spec says subsequent
136 * reads return values which are "unpredictable". So this
137 * is always right except in those broken-by-intent cases.
139 switch (dpm->arm->core_state) {
140 case ARMV4_5_STATE_ARM:
143 case ARMV4_5_STATE_THUMB:
144 case ARM_STATE_THUMB_EE:
147 case ARMV4_5_STATE_JAZELLE:
148 /* core-specific ... ? */
149 LOG_WARNING("Jazelle PC adjustment unknown");
154 /* 16: "MRS r0, CPSR"; then return via DCC
155 * 17: "MRS r0, SPSR"; then return via DCC
157 retval = dpm->instr_read_data_r0(dpm,
158 ARMV4_5_MRS(0, regnum & 1),
163 if (retval == ERROR_OK) {
164 buf_set_u32(r->value, 0, 32, value);
167 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
173 /* just write the register -- rely on the core mode being right */
174 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
177 uint32_t value = buf_get_u32(r->value, 0, 32);
181 /* load register from DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
182 retval = dpm->instr_write_data_dcc(dpm,
183 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
187 /* read r0 from DCC; then "MOV pc, r0" */
188 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
191 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
192 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
194 retval = dpm->instr_write_data_r0(dpm,
195 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
198 if (regnum == 16 && dpm->instr_cpsr_sync)
199 retval = dpm->instr_cpsr_sync(dpm);
204 if (retval == ERROR_OK) {
206 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
213 * Read basic registers of the the current context: R0 to R15, and CPSR;
214 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
215 * In normal operation this is called on entry to halting debug state,
216 * possibly after some other operations supporting restore of debug state
217 * or making sure the CPU is fully idle (drain write buffer, etc).
219 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
221 struct arm *arm = dpm->arm;
226 retval = dpm->prepare(dpm);
227 if (retval != ERROR_OK)
230 /* read R0 first (it's used for scratch), then CPSR */
231 r = arm->core_cache->reg_list + 0;
233 retval = dpm_read_reg(dpm, r, 0);
234 if (retval != ERROR_OK)
239 retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
240 if (retval != ERROR_OK)
243 /* update core mode and state, plus shadow mapping for R8..R14 */
244 arm_set_cpsr(arm, cpsr);
246 /* REVISIT we can probably avoid reading R1..R14, saving time... */
247 for (unsigned i = 1; i < 16; i++) {
248 r = arm_reg_current(arm, i);
252 retval = dpm_read_reg(dpm, r, i);
253 if (retval != ERROR_OK)
257 /* NOTE: SPSR ignored (if it's even relevant). */
260 /* (void) */ dpm->finish(dpm);
265 * Writes all modified core registers for all processor modes. In normal
266 * operation this is called on exit from halting debug state.
268 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm)
270 struct arm *arm = dpm->arm;
271 struct reg_cache *cache = arm->core_cache;
275 retval = dpm->prepare(dpm);
276 if (retval != ERROR_OK)
279 /* Scan the registers until we find one that's both dirty and
280 * eligible for flushing. Flush that and everything else that
281 * shares the same core mode setting. Typically this won't
282 * actually find anything to do...
285 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
289 /* check everything except our scratch register R0 */
290 for (unsigned i = 1; i < cache->num_regs; i++) {
294 /* also skip PC, CPSR, and non-dirty */
297 if (arm->cpsr == cache->reg_list + i)
299 if (!cache->reg_list[i].dirty)
302 r = cache->reg_list[i].arch_info;
305 /* may need to pick and set a mode */
307 enum armv4_5_mode tmode;
310 mode = tmode = r->mode;
312 /* cope with special cases */
315 /* r8..r12 "anything but FIQ" case;
316 * we "know" core mode is accurate
317 * since we haven't changed it yet
319 if (arm->core_mode == ARMV4_5_MODE_FIQ
322 tmode = ARMV4_5_MODE_USR;
330 /* REVISIT error checks */
331 if (tmode != ARMV4_5_MODE_ANY)
332 retval = dpm_modeswitch(dpm, tmode);
337 retval = dpm_write_reg(dpm,
345 /* Restore original CPSR ... assuming either that we changed it,
346 * or it's dirty. Must write PC to ensure the return address is
347 * defined, and must not write it before CPSR.
349 retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
350 arm->cpsr->dirty = false;
352 retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
353 cache->reg_list[15].dirty = false;
355 /* flush R0 -- it's *very* dirty by now */
356 retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
357 cache->reg_list[0].dirty = false;
359 /* (void) */ dpm->finish(dpm);
364 /* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
365 * specified register ... works around flakiness from ARM core calls.
366 * Caller already filtered out SPSR access; mode is never MODE_SYS
369 static enum armv4_5_mode dpm_mapmode(struct arm *arm,
370 unsigned num, enum armv4_5_mode mode)
372 enum armv4_5_mode amode = arm->core_mode;
374 /* don't switch if the mode is already correct */
375 if (amode == ARMV4_5_MODE_SYS)
376 amode = ARMV4_5_MODE_USR;
378 return ARMV4_5_MODE_ANY;
381 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
386 /* r8..r12 aren't shadowed for anything except FIQ */
388 if (mode == ARMV4_5_MODE_FIQ)
391 /* r13/sp, and r14/lr are always shadowed */
396 LOG_WARNING("invalid register #%u", num);
399 return ARMV4_5_MODE_ANY;
402 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
403 int regnum, enum armv4_5_mode mode)
405 struct arm_dpm *dpm = target_to_arm(target)->dpm;
408 if (regnum < 0 || regnum > 16)
409 return ERROR_INVALID_ARGUMENTS;
412 if (mode != ARMV4_5_MODE_ANY)
415 mode = dpm_mapmode(dpm->arm, regnum, mode);
417 /* REVISIT what happens if we try to read SPSR in a core mode
418 * which has no such register?
421 retval = dpm->prepare(dpm);
422 if (retval != ERROR_OK)
425 if (mode != ARMV4_5_MODE_ANY) {
426 retval = dpm_modeswitch(dpm, mode);
427 if (retval != ERROR_OK)
431 retval = dpm_read_reg(dpm, r, regnum);
432 /* always clean up, regardless of error */
434 if (mode != ARMV4_5_MODE_ANY)
435 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
438 /* (void) */ dpm->finish(dpm);
442 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
443 int regnum, enum armv4_5_mode mode, uint32_t value)
445 struct arm_dpm *dpm = target_to_arm(target)->dpm;
449 if (regnum < 0 || regnum > 16)
450 return ERROR_INVALID_ARGUMENTS;
453 if (mode != ARMV4_5_MODE_ANY)
456 mode = dpm_mapmode(dpm->arm, regnum, mode);
458 /* REVISIT what happens if we try to write SPSR in a core mode
459 * which has no such register?
462 retval = dpm->prepare(dpm);
463 if (retval != ERROR_OK)
466 if (mode != ARMV4_5_MODE_ANY) {
467 retval = dpm_modeswitch(dpm, mode);
468 if (retval != ERROR_OK)
472 retval = dpm_write_reg(dpm, r, regnum);
473 /* always clean up, regardless of error */
475 if (mode != ARMV4_5_MODE_ANY)
476 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
479 /* (void) */ dpm->finish(dpm);
483 static int arm_dpm_full_context(struct target *target)
485 struct arm *arm = target_to_arm(target);
486 struct arm_dpm *dpm = arm->dpm;
487 struct reg_cache *cache = arm->core_cache;
491 retval = dpm->prepare(dpm);
492 if (retval != ERROR_OK)
496 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
500 /* We "know" arm_dpm_read_current_registers() was called so
501 * the unmapped registers (R0..R7, PC, AND CPSR) and some
502 * view of R8..R14 are current. We also "know" oddities of
503 * register mapping: special cases for R8..R12 and SPSR.
505 * Pick some mode with unread registers and read them all.
508 for (unsigned i = 0; i < cache->num_regs; i++) {
511 if (cache->reg_list[i].valid)
513 r = cache->reg_list[i].arch_info;
515 /* may need to pick a mode and set CPSR */
520 /* For R8..R12 when we've entered debug
521 * state in FIQ mode... patch mode.
523 if (mode == ARMV4_5_MODE_ANY)
524 mode = ARMV4_5_MODE_USR;
526 /* REVISIT error checks */
527 retval = dpm_modeswitch(dpm, mode);
532 /* CPSR was read, so "R16" must mean SPSR */
533 retval = dpm_read_reg(dpm,
535 (r->num == 16) ? 17 : r->num);
541 retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
542 /* (void) */ dpm->finish(dpm);
548 * Hooks up this DPM to its associated target; call only once.
549 * Initially this only covers the register cache.
551 int arm_dpm_setup(struct arm_dpm *dpm)
553 struct arm *arm = dpm->arm;
554 struct target *target = arm->target;
555 struct reg_cache *cache;
559 arm->full_context = arm_dpm_full_context;
560 arm->read_core_reg = arm_dpm_read_core_reg;
561 arm->write_core_reg = arm_dpm_write_core_reg;
563 cache = armv4_5_build_reg_cache(target, arm);
567 *register_get_last_cache_p(&target->reg_cache) = cache;
576 * Reinitializes DPM state at the beginning of a new debug session
577 * or after a reset which may have affected the debug module.
579 int arm_dpm_initialize(struct arm_dpm *dpm)
581 /* FIXME -- nothing yet */