git.sur5r.net Git - openocd/blob - src/target/arm_dpm.c

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifdef HAVE_CONFIG_H
  19 #include "config.h"
  20 #endif
  21
  22 #include "arm.h"
  23 #include "arm_dpm.h"
  24 #include "armv8_dpm.h"
  25 #include <jtag/jtag.h>
  26 #include "register.h"
  27 #include "breakpoints.h"
  28 #include "target_type.h"
  29 #include "arm_opcodes.h"
  30
  31
  32 /**
  33  * @file
  34  * Implements various ARM DPM operations using architectural debug registers.
  35  * These routines layer over core-specific communication methods to cope with
  36  * implementation differences between cores like ARM1136 and Cortex-A8.
  37  *
  38  * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
  39  * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
  40  * ARMv7-A and ARMv7-R edition (ARM DDI 0406B).  In OpenOCD, DPM operations
  41  * are abstracted through internal programming interfaces to share code and
  42  * to minimize needless differences in debug behavior between cores.
  43  */
  44
  45 /*----------------------------------------------------------------------*/
  46
  47 /*
  48  * Coprocessor support
  49  */
  50
  51 /* Read coprocessor */
  52 static int dpm_mrc(struct target *target, int cpnum,
  53         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  54         uint32_t *value)
  55 {
  56         struct arm *arm = target_to_arm(target);
  57         struct arm_dpm *dpm = arm->dpm;
  58         int retval;
  59
  60         retval = dpm->prepare(dpm);
  61         if (retval != ERROR_OK)
  62                 return retval;
  63
  64         LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  65                 (int) op1, (int) CRn,
  66                 (int) CRm, (int) op2);
  67
  68         /* read coprocessor register into R0; return via DCC */
  69         retval = dpm->instr_read_data_r0(dpm,
  70                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  71                         value);
  72
  73         /* (void) */ dpm->finish(dpm);
  74         return retval;
  75 }
  76
  77 static int dpm_mcr(struct target *target, int cpnum,
  78         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  79         uint32_t value)
  80 {
  81         struct arm *arm = target_to_arm(target);
  82         struct arm_dpm *dpm = arm->dpm;
  83         int retval;
  84
  85         retval = dpm->prepare(dpm);
  86         if (retval != ERROR_OK)
  87                 return retval;
  88
  89         LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  90                 (int) op1, (int) CRn,
  91                 (int) CRm, (int) op2);
  92
  93         /* read DCC into r0; then write coprocessor register from R0 */
  94         retval = dpm->instr_write_data_r0(dpm,
  95                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  96                         value);
  97
  98         /* (void) */ dpm->finish(dpm);
  99         return retval;
 100 }
 101
 102 /*----------------------------------------------------------------------*/
 103
 104 /*
 105  * Register access utilities
 106  */
 107
 108 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
 109  * Routines *must* restore the original mode before returning!!
 110  */
 111 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 112 {
 113         int retval;
 114         uint32_t cpsr;
 115
 116         /* restore previous mode */
 117         if (mode == ARM_MODE_ANY)
 118                 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 119
 120         /* else force to the specified mode */
 121         else
 122                 cpsr = mode;
 123
 124         retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 125         if (retval != ERROR_OK)
 126                 return retval;
 127
 128         if (dpm->instr_cpsr_sync)
 129                 retval = dpm->instr_cpsr_sync(dpm);
 130
 131         return retval;
 132 }
 133
 134 /* just read the register -- rely on the core mode being right */
 135 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 136 {
 137         uint32_t value;
 138         int retval;
 139
 140         switch (regnum) {
 141                 case 0 ... 14:
 142                         /* return via DCC:  "MCR p14, 0, Rnum, c0, c5, 0" */
 143                         retval = dpm->instr_read_data_dcc(dpm,
 144                                 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
 145                                 &value);
 146                         break;
 147                 case 15:/* PC
 148                          * "MOV r0, pc"; then return via DCC */
 149                         retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
 150
 151                         /* NOTE: this seems like a slightly awkward place to update
 152                          * this value ... but if the PC gets written (the only way
 153                          * to change what we compute), the arch spec says subsequent
 154                          * reads return values which are "unpredictable".  So this
 155                          * is always right except in those broken-by-intent cases.
 156                          */
 157                         switch (dpm->arm->core_state) {
 158                                 case ARM_STATE_ARM:
 159                                         value -= 8;
 160                                         break;
 161                                 case ARM_STATE_THUMB:
 162                                 case ARM_STATE_THUMB_EE:
 163                                         value -= 4;
 164                                         break;
 165                                 case ARM_STATE_JAZELLE:
 166                                         /* core-specific ... ? */
 167                                         LOG_WARNING("Jazelle PC adjustment unknown");
 168                                         break;
 169                                 default:
 170                                         LOG_WARNING("unknow core state");
 171                                         break;
 172                         }
 173                         break;
 174                 default:
 175                         /* 16: "MRS r0, CPSR"; then return via DCC
 176                          * 17: "MRS r0, SPSR"; then return via DCC
 177                          */
 178                         retval = dpm->instr_read_data_r0(dpm,
 179                                 ARMV4_5_MRS(0, regnum & 1),
 180                                 &value);
 181                         break;
 182         }
 183
 184         if (retval == ERROR_OK) {
 185                 buf_set_u32(r->value, 0, 32, value);
 186                 r->valid = true;
 187                 r->dirty = false;
 188                 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
 189         }
 190
 191         return retval;
 192 }
 193
 194 /* just write the register -- rely on the core mode being right */
 195 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 196 {
 197         int retval;
 198         uint32_t value = buf_get_u32(r->value, 0, 32);
 199
 200         switch (regnum) {
 201                 case 0 ... 14:
 202                         /* load register from DCC:  "MRC p14, 0, Rnum, c0, c5, 0" */
 203                         retval = dpm->instr_write_data_dcc(dpm,
 204                                 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
 205                                 value);
 206                         break;
 207                 case 15:/* PC
 208                          * read r0 from DCC; then "MOV pc, r0" */
 209                         retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
 210                         break;
 211                 default:
 212                         /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
 213                          * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
 214                          */
 215                         retval = dpm->instr_write_data_r0(dpm,
 216                                 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 217                                 value);
 218                         if (retval != ERROR_OK)
 219                                 return retval;
 220
 221                         if (regnum == 16 && dpm->instr_cpsr_sync)
 222                                 retval = dpm->instr_cpsr_sync(dpm);
 223
 224                         break;
 225         }
 226
 227         if (retval == ERROR_OK) {
 228                 r->dirty = false;
 229                 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
 230         }
 231
 232         return retval;
 233 }
 234
 235 /**
 236  * Write to program counter and switch the core state (arm/thumb) according to
 237  * the address.
 238  */
 239 static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
 240 {
 241         uint32_t value = buf_get_u32(r->value, 0, 32);
 242
 243         /* read r0 from DCC; then "BX r0" */
 244         return dpm->instr_write_data_r0(dpm, ARMV4_5_BX(0), value);
 245 }
 246
 247 /**
 248  * Read basic registers of the the current context:  R0 to R15, and CPSR;
 249  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
 250  * In normal operation this is called on entry to halting debug state,
 251  * possibly after some other operations supporting restore of debug state
 252  * or making sure the CPU is fully idle (drain write buffer, etc).
 253  */
 254 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 255 {
 256         struct arm *arm = dpm->arm;
 257         uint32_t cpsr;
 258         int retval;
 259         struct reg *r;
 260
 261         retval = dpm->prepare(dpm);
 262         if (retval != ERROR_OK)
 263                 return retval;
 264
 265         /* read R0 first (it's used for scratch), then CPSR */
 266         r = arm->core_cache->reg_list + 0;
 267         if (!r->valid) {
 268                 retval = dpm_read_reg(dpm, r, 0);
 269                 if (retval != ERROR_OK)
 270                         goto fail;
 271         }
 272         r->dirty = true;
 273
 274         retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
 275         if (retval != ERROR_OK)
 276                 goto fail;
 277
 278         /* update core mode and state, plus shadow mapping for R8..R14 */
 279         arm_set_cpsr(arm, cpsr);
 280
 281         /* REVISIT we can probably avoid reading R1..R14, saving time... */
 282         for (unsigned i = 1; i < 16; i++) {
 283                 r = arm_reg_current(arm, i);
 284                 if (r->valid)
 285                         continue;
 286
 287                 retval = dpm_read_reg(dpm, r, i);
 288                 if (retval != ERROR_OK)
 289                         goto fail;
 290         }
 291
 292         /* NOTE: SPSR ignored (if it's even relevant). */
 293
 294         /* REVISIT the debugger can trigger various exceptions.  See the
 295          * ARMv7A architecture spec, section C5.7, for more info about
 296          * what defenses are needed; v6 debug has the most issues.
 297          */
 298
 299 fail:
 300         /* (void) */ dpm->finish(dpm);
 301         return retval;
 302 }
 303
 304 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
 305  * unless they're removed, or need updating because of single-stepping
 306  * or running debugger code.
 307  */
 308 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 309         struct dpm_bpwp *xp, int *set_p)
 310 {
 311         int retval = ERROR_OK;
 312         bool disable;
 313
 314         if (!set_p) {
 315                 if (!xp->dirty)
 316                         goto done;
 317                 xp->dirty = false;
 318                 /* removed or startup; we must disable it */
 319                 disable = true;
 320         } else if (bpwp) {
 321                 if (!xp->dirty)
 322                         goto done;
 323                 /* disabled, but we must set it */
 324                 xp->dirty = disable = false;
 325                 *set_p = true;
 326         } else {
 327                 if (!*set_p)
 328                         goto done;
 329                 /* set, but we must temporarily disable it */
 330                 xp->dirty = disable = true;
 331                 *set_p = false;
 332         }
 333
 334         if (disable)
 335                 retval = dpm->bpwp_disable(dpm, xp->number);
 336         else
 337                 retval = dpm->bpwp_enable(dpm, xp->number,
 338                                 xp->address, xp->control);
 339
 340         if (retval != ERROR_OK)
 341                 LOG_ERROR("%s: can't %s HW %spoint %d",
 342                         disable ? "disable" : "enable",
 343                         target_name(dpm->arm->target),
 344                         (xp->number < 16) ? "break" : "watch",
 345                         xp->number & 0xf);
 346 done:
 347         return retval;
 348 }
 349
 350 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
 351
 352 /**
 353  * Writes all modified core registers for all processor modes.  In normal
 354  * operation this is called on exit from halting debug state.
 355  *
 356  * @param dpm: represents the processor
 357  * @param bpwp: true ensures breakpoints and watchpoints are set,
 358  *      false ensures they are cleared
 359  */
 360 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 361 {
 362         struct arm *arm = dpm->arm;
 363         struct reg_cache *cache = arm->core_cache;
 364         int retval;
 365         bool did_write;
 366
 367         retval = dpm->prepare(dpm);
 368         if (retval != ERROR_OK)
 369                 goto done;
 370
 371         /* If we're managing hardware breakpoints for this core, enable
 372          * or disable them as requested.
 373          *
 374          * REVISIT We don't yet manage them for ANY cores.  Eventually
 375          * we should be able to assume we handle them; but until then,
 376          * cope with the hand-crafted breakpoint code.
 377          */
 378         if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
 379                 for (unsigned i = 0; i < dpm->nbp; i++) {
 380                         struct dpm_bp *dbp = dpm->dbp + i;
 381                         struct breakpoint *bp = dbp->bp;
 382
 383                         retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
 384                                         bp ? &bp->set : NULL);
 385                         if (retval != ERROR_OK)
 386                                 goto done;
 387                 }
 388         }
 389
 390         /* enable/disable watchpoints */
 391         for (unsigned i = 0; i < dpm->nwp; i++) {
 392                 struct dpm_wp *dwp = dpm->dwp + i;
 393                 struct watchpoint *wp = dwp->wp;
 394
 395                 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
 396                                 wp ? &wp->set : NULL);
 397                 if (retval != ERROR_OK)
 398                         goto done;
 399         }
 400
 401         /* NOTE:  writes to breakpoint and watchpoint registers might
 402          * be queued, and need (efficient/batched) flushing later.
 403          */
 404
 405         /* Scan the registers until we find one that's both dirty and
 406          * eligible for flushing.  Flush that and everything else that
 407          * shares the same core mode setting.  Typically this won't
 408          * actually find anything to do...
 409          */
 410         do {
 411                 enum arm_mode mode = ARM_MODE_ANY;
 412
 413                 did_write = false;
 414
 415                 /* check everything except our scratch register R0 */
 416                 for (unsigned i = 1; i < cache->num_regs; i++) {
 417                         struct arm_reg *r;
 418                         unsigned regnum;
 419
 420                         /* also skip PC, CPSR, and non-dirty */
 421                         if (i == 15)
 422                                 continue;
 423                         if (arm->cpsr == cache->reg_list + i)
 424                                 continue;
 425                         if (!cache->reg_list[i].dirty)
 426                                 continue;
 427
 428                         r = cache->reg_list[i].arch_info;
 429                         regnum = r->num;
 430
 431                         /* may need to pick and set a mode */
 432                         if (!did_write) {
 433                                 enum arm_mode tmode;
 434
 435                                 did_write = true;
 436                                 mode = tmode = r->mode;
 437
 438                                 /* cope with special cases */
 439                                 switch (regnum) {
 440                                 case 8 ... 12:
 441                                         /* r8..r12 "anything but FIQ" case;
 442                                          * we "know" core mode is accurate
 443                                          * since we haven't changed it yet
 444                                          */
 445                                         if (arm->core_mode == ARM_MODE_FIQ
 446                                             && ARM_MODE_ANY
 447                                             != mode)
 448                                                 tmode = ARM_MODE_USR;
 449                                         break;
 450                                 case 16:
 451                                         /* SPSR */
 452                                         regnum++;
 453                                         break;
 454                                 }
 455
 456                                 /* REVISIT error checks */
 457                                 if (tmode != ARM_MODE_ANY) {
 458                                         retval = dpm_modeswitch(dpm, tmode);
 459                                         if (retval != ERROR_OK)
 460                                                 goto done;
 461                                 }
 462                         }
 463                         if (r->mode != mode)
 464                                 continue;
 465
 466                         retval = dpm_write_reg(dpm,
 467                                                &cache->reg_list[i],
 468                                                regnum);
 469                         if (retval != ERROR_OK)
 470                                 goto done;
 471                 }
 472
 473         } while (did_write);
 474
 475         /* Restore original CPSR ... assuming either that we changed it,
 476          * or it's dirty.  Must write PC to ensure the return address is
 477          * defined, and must not write it before CPSR.
 478          */
 479         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 480         if (retval != ERROR_OK)
 481                 goto done;
 482         arm->cpsr->dirty = false;
 483
 484         /* restore the PC, make sure to also switch the core state
 485          * to whatever it was set to with "arm core_state" command.
 486          * target code will have set PC to an appropriate resume address.
 487          */
 488         retval = dpm_write_pc_core_state(dpm, arm->pc);
 489         if (retval != ERROR_OK)
 490                 goto done;
 491         /* on Cortex-A5 (as found on NXP VF610 SoC), BX instruction
 492          * executed in debug state doesn't appear to set the PC,
 493          * explicitly set it with a "MOV pc, r0". This doesn't influence
 494          * CPSR on Cortex-A9 so it should be OK. Maybe due to different
 495          * debug version?
 496          */
 497         retval = dpm_write_reg(dpm, arm->pc, 15);
 498         if (retval != ERROR_OK)
 499                 goto done;
 500         arm->pc->dirty = false;
 501
 502         /* flush R0 -- it's *very* dirty by now */
 503         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 504         if (retval != ERROR_OK)
 505                 goto done;
 506         cache->reg_list[0].dirty = false;
 507
 508         /* (void) */ dpm->finish(dpm);
 509 done:
 510         return retval;
 511 }
 512
 513 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
 514  * specified register ... works around flakiness from ARM core calls.
 515  * Caller already filtered out SPSR access; mode is never MODE_SYS
 516  * or MODE_ANY.
 517  */
 518 static enum arm_mode dpm_mapmode(struct arm *arm,
 519         unsigned num, enum arm_mode mode)
 520 {
 521         enum arm_mode amode = arm->core_mode;
 522
 523         /* don't switch if the mode is already correct */
 524         if (amode == ARM_MODE_SYS)
 525                 amode = ARM_MODE_USR;
 526         if (mode == amode)
 527                 return ARM_MODE_ANY;
 528
 529         switch (num) {
 530                 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
 531                 case 0 ... 7:
 532                 case 15:
 533                 case 16:
 534                         break;
 535                 /* r8..r12 aren't shadowed for anything except FIQ */
 536                 case 8 ... 12:
 537                         if (mode == ARM_MODE_FIQ)
 538                                 return mode;
 539                         break;
 540                 /* r13/sp, and r14/lr are always shadowed */
 541                 case 13:
 542                 case 14:
 543                         return mode;
 544                 default:
 545                         LOG_WARNING("invalid register #%u", num);
 546                         break;
 547         }
 548         return ARM_MODE_ANY;
 549 }
 550
 551
 552 /*
 553  * Standard ARM register accessors ... there are three methods
 554  * in "struct arm", to support individual read/write and bulk read
 555  * of registers.
 556  */
 557
 558 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 559         int regnum, enum arm_mode mode)
 560 {
 561         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 562         int retval;
 563
 564         if (regnum < 0 || regnum > 16)
 565                 return ERROR_COMMAND_SYNTAX_ERROR;
 566
 567         if (regnum == 16) {
 568                 if (mode != ARM_MODE_ANY)
 569                         regnum = 17;
 570         } else
 571                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 572
 573         /* REVISIT what happens if we try to read SPSR in a core mode
 574          * which has no such register?
 575          */
 576
 577         retval = dpm->prepare(dpm);
 578         if (retval != ERROR_OK)
 579                 return retval;
 580
 581         if (mode != ARM_MODE_ANY) {
 582                 retval = dpm_modeswitch(dpm, mode);
 583                 if (retval != ERROR_OK)
 584                         goto fail;
 585         }
 586
 587         retval = dpm_read_reg(dpm, r, regnum);
 588         if (retval != ERROR_OK)
 589                 goto fail;
 590         /* always clean up, regardless of error */
 591
 592         if (mode != ARM_MODE_ANY)
 593                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 594
 595 fail:
 596         /* (void) */ dpm->finish(dpm);
 597         return retval;
 598 }
 599
 600 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
 601         int regnum, enum arm_mode mode, uint8_t *value)
 602 {
 603         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 604         int retval;
 605
 606
 607         if (regnum < 0 || regnum > 16)
 608                 return ERROR_COMMAND_SYNTAX_ERROR;
 609
 610         if (regnum == 16) {
 611                 if (mode != ARM_MODE_ANY)
 612                         regnum = 17;
 613         } else
 614                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 615
 616         /* REVISIT what happens if we try to write SPSR in a core mode
 617          * which has no such register?
 618          */
 619
 620         retval = dpm->prepare(dpm);
 621         if (retval != ERROR_OK)
 622                 return retval;
 623
 624         if (mode != ARM_MODE_ANY) {
 625                 retval = dpm_modeswitch(dpm, mode);
 626                 if (retval != ERROR_OK)
 627                         goto fail;
 628         }
 629
 630         retval = dpm_write_reg(dpm, r, regnum);
 631         /* always clean up, regardless of error */
 632
 633         if (mode != ARM_MODE_ANY)
 634                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 635
 636 fail:
 637         /* (void) */ dpm->finish(dpm);
 638         return retval;
 639 }
 640
 641 static int arm_dpm_full_context(struct target *target)
 642 {
 643         struct arm *arm = target_to_arm(target);
 644         struct arm_dpm *dpm = arm->dpm;
 645         struct reg_cache *cache = arm->core_cache;
 646         int retval;
 647         bool did_read;
 648
 649         retval = dpm->prepare(dpm);
 650         if (retval != ERROR_OK)
 651                 goto done;
 652
 653         do {
 654                 enum arm_mode mode = ARM_MODE_ANY;
 655
 656                 did_read = false;
 657
 658                 /* We "know" arm_dpm_read_current_registers() was called so
 659                  * the unmapped registers (R0..R7, PC, AND CPSR) and some
 660                  * view of R8..R14 are current.  We also "know" oddities of
 661                  * register mapping: special cases for R8..R12 and SPSR.
 662                  *
 663                  * Pick some mode with unread registers and read them all.
 664                  * Repeat until done.
 665                  */
 666                 for (unsigned i = 0; i < cache->num_regs; i++) {
 667                         struct arm_reg *r;
 668
 669                         if (cache->reg_list[i].valid)
 670                                 continue;
 671                         r = cache->reg_list[i].arch_info;
 672
 673                         /* may need to pick a mode and set CPSR */
 674                         if (!did_read) {
 675                                 did_read = true;
 676                                 mode = r->mode;
 677
 678                                 /* For regular (ARM_MODE_ANY) R8..R12
 679                                  * in case we've entered debug state
 680                                  * in FIQ mode we need to patch mode.
 681                                  */
 682                                 if (mode != ARM_MODE_ANY)
 683                                         retval = dpm_modeswitch(dpm, mode);
 684                                 else
 685                                         retval = dpm_modeswitch(dpm, ARM_MODE_USR);
 686
 687                                 if (retval != ERROR_OK)
 688                                         goto done;
 689                         }
 690                         if (r->mode != mode)
 691                                 continue;
 692
 693                         /* CPSR was read, so "R16" must mean SPSR */
 694                         retval = dpm_read_reg(dpm,
 695                                         &cache->reg_list[i],
 696                                         (r->num == 16) ? 17 : r->num);
 697                         if (retval != ERROR_OK)
 698                                 goto done;
 699                 }
 700
 701         } while (did_read);
 702
 703         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 704         /* (void) */ dpm->finish(dpm);
 705 done:
 706         return retval;
 707 }
 708
 709
 710 /*----------------------------------------------------------------------*/
 711
 712 /*
 713  * Breakpoint and Watchpoint support.
 714  *
 715  * Hardware {break,watch}points are usually left active, to minimize
 716  * debug entry/exit costs.  When they are set or cleared, it's done in
 717  * batches.  Also, DPM-conformant hardware can update debug registers
 718  * regardless of whether the CPU is running or halted ... though that
 719  * fact isn't currently leveraged.
 720  */
 721
 722 static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 723         uint32_t addr, uint32_t length)
 724 {
 725         uint32_t control;
 726
 727         control = (1 << 0)      /* enable */
 728                 | (3 << 1);     /* both user and privileged access */
 729
 730         /* Match 1, 2, or all 4 byte addresses in this word.
 731          *
 732          * FIXME:  v7 hardware allows lengths up to 2 GB for BP and WP.
 733          * Support larger length, when addr is suitably aligned.  In
 734          * particular, allow watchpoints on 8 byte "double" values.
 735          *
 736          * REVISIT allow watchpoints on unaligned 2-bit values; and on
 737          * v7 hardware, unaligned 4-byte ones too.
 738          */
 739         switch (length) {
 740                 case 1:
 741                         control |= (1 << (addr & 3)) << 5;
 742                         break;
 743                 case 2:
 744                         /* require 2-byte alignment */
 745                         if (!(addr & 1)) {
 746                                 control |= (3 << (addr & 2)) << 5;
 747                                 break;
 748                         }
 749                 /* FALL THROUGH */
 750                 case 4:
 751                         /* require 4-byte alignment */
 752                         if (!(addr & 3)) {
 753                                 control |= 0xf << 5;
 754                                 break;
 755                         }
 756                 /* FALL THROUGH */
 757                 default:
 758                         LOG_ERROR("unsupported {break,watch}point length/alignment");
 759                         return ERROR_COMMAND_SYNTAX_ERROR;
 760         }
 761
 762         /* other shared control bits:
 763          * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
 764          * bit 20 == 0 ... not linked to a context ID
 765          * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
 766          */
 767
 768         xp->address = addr & ~3;
 769         xp->control = control;
 770         xp->dirty = true;
 771
 772         LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
 773                 xp->address, control, xp->number);
 774
 775         /* hardware is updated in write_dirty_registers() */
 776         return ERROR_OK;
 777 }
 778
 779 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 780 {
 781         struct arm *arm = target_to_arm(target);
 782         struct arm_dpm *dpm = arm->dpm;
 783         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 784
 785         if (bp->length < 2)
 786                 return ERROR_COMMAND_SYNTAX_ERROR;
 787         if (!dpm->bpwp_enable)
 788                 return retval;
 789
 790         /* FIXME we need a generic solution for software breakpoints. */
 791         if (bp->type == BKPT_SOFT)
 792                 LOG_DEBUG("using HW bkpt, not SW...");
 793
 794         for (unsigned i = 0; i < dpm->nbp; i++) {
 795                 if (!dpm->dbp[i].bp) {
 796                         retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
 797                                         bp->address, bp->length);
 798                         if (retval == ERROR_OK)
 799                                 dpm->dbp[i].bp = bp;
 800                         break;
 801                 }
 802         }
 803
 804         return retval;
 805 }
 806
 807 static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
 808 {
 809         struct arm *arm = target_to_arm(target);
 810         struct arm_dpm *dpm = arm->dpm;
 811         int retval = ERROR_COMMAND_SYNTAX_ERROR;
 812
 813         for (unsigned i = 0; i < dpm->nbp; i++) {
 814                 if (dpm->dbp[i].bp == bp) {
 815                         dpm->dbp[i].bp = NULL;
 816                         dpm->dbp[i].bpwp.dirty = true;
 817
 818                         /* hardware is updated in write_dirty_registers() */
 819                         retval = ERROR_OK;
 820                         break;
 821                 }
 822         }
 823
 824         return retval;
 825 }
 826
 827 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
 828         struct watchpoint *wp)
 829 {
 830         int retval;
 831         struct dpm_wp *dwp = dpm->dwp + index_t;
 832         uint32_t control;
 833
 834         /* this hardware doesn't support data value matching or masking */
 835         if (wp->value || wp->mask != ~(uint32_t)0) {
 836                 LOG_DEBUG("watchpoint values and masking not supported");
 837                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 838         }
 839
 840         retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
 841         if (retval != ERROR_OK)
 842                 return retval;
 843
 844         control = dwp->bpwp.control;
 845         switch (wp->rw) {
 846                 case WPT_READ:
 847                         control |= 1 << 3;
 848                         break;
 849                 case WPT_WRITE:
 850                         control |= 2 << 3;
 851                         break;
 852                 case WPT_ACCESS:
 853                         control |= 3 << 3;
 854                         break;
 855         }
 856         dwp->bpwp.control = control;
 857
 858         dpm->dwp[index_t].wp = wp;
 859
 860         return retval;
 861 }
 862
 863 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
 864 {
 865         struct arm *arm = target_to_arm(target);
 866         struct arm_dpm *dpm = arm->dpm;
 867         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 868
 869         if (dpm->bpwp_enable) {
 870                 for (unsigned i = 0; i < dpm->nwp; i++) {
 871                         if (!dpm->dwp[i].wp) {
 872                                 retval = dpm_watchpoint_setup(dpm, i, wp);
 873                                 break;
 874                         }
 875                 }
 876         }
 877
 878         return retval;
 879 }
 880
 881 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 882 {
 883         struct arm *arm = target_to_arm(target);
 884         struct arm_dpm *dpm = arm->dpm;
 885         int retval = ERROR_COMMAND_SYNTAX_ERROR;
 886
 887         for (unsigned i = 0; i < dpm->nwp; i++) {
 888                 if (dpm->dwp[i].wp == wp) {
 889                         dpm->dwp[i].wp = NULL;
 890                         dpm->dwp[i].bpwp.dirty = true;
 891
 892                         /* hardware is updated in write_dirty_registers() */
 893                         retval = ERROR_OK;
 894                         break;
 895                 }
 896         }
 897
 898         return retval;
 899 }
 900
 901 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 902 {
 903         switch (dpm->arm->core_state) {
 904                 case ARM_STATE_ARM:
 905                         addr -= 8;
 906                         break;
 907                 case ARM_STATE_THUMB:
 908                 case ARM_STATE_THUMB_EE:
 909                         addr -= 4;
 910                         break;
 911                 case ARM_STATE_JAZELLE:
 912                 case ARM_STATE_AARCH64:
 913                         /* ?? */
 914                         break;
 915         }
 916         dpm->wp_pc = addr;
 917 }
 918
 919 /*----------------------------------------------------------------------*/
 920
 921 /*
 922  * Other debug and support utilities
 923  */
 924
 925 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
 926 {
 927         struct target *target = dpm->arm->target;
 928
 929         dpm->dscr = dscr;
 930
 931         /* Examine debug reason */
 932         switch (DSCR_ENTRY(dscr)) {
 933                 case DSCR_ENTRY_HALT_REQ:       /* HALT request from debugger */
 934                 case DSCR_ENTRY_EXT_DBG_REQ:    /* EDBGRQ */
 935                         target->debug_reason = DBG_REASON_DBGRQ;
 936                         break;
 937                 case DSCR_ENTRY_BREAKPOINT:     /* HW breakpoint */
 938                 case DSCR_ENTRY_BKPT_INSTR:     /* vector catch */
 939                         target->debug_reason = DBG_REASON_BREAKPOINT;
 940                         break;
 941                 case DSCR_ENTRY_IMPRECISE_WATCHPT:      /* asynch watchpoint */
 942                 case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
 943                         target->debug_reason = DBG_REASON_WATCHPOINT;
 944                         break;
 945                 default:
 946                         target->debug_reason = DBG_REASON_UNDEFINED;
 947                         break;
 948         }
 949 }
 950
 951 /*----------------------------------------------------------------------*/
 952
 953 /*
 954  * Setup and management support.
 955  */
 956
 957 /**
 958  * Hooks up this DPM to its associated target; call only once.
 959  * Initially this only covers the register cache.
 960  *
 961  * Oh, and watchpoints.  Yeah.
 962  */
 963 int arm_dpm_setup(struct arm_dpm *dpm)
 964 {
 965         struct arm *arm = dpm->arm;
 966         struct target *target = arm->target;
 967         struct reg_cache *cache = 0;
 968
 969         arm->dpm = dpm;
 970
 971         /* register access setup */
 972         arm->full_context = arm_dpm_full_context;
 973         arm->read_core_reg = arm_dpm_read_core_reg;
 974         arm->write_core_reg = arm_dpm_write_core_reg;
 975
 976         if (arm->core_cache == NULL) {
 977                 cache = arm_build_reg_cache(target, arm);
 978                 if (!cache)
 979                         return ERROR_FAIL;
 980
 981                 *register_get_last_cache_p(&target->reg_cache) = cache;
 982         }
 983
 984         /* coprocessor access setup */
 985         arm->mrc = dpm_mrc;
 986         arm->mcr = dpm_mcr;
 987
 988         /* breakpoint setup -- optional until it works everywhere */
 989         if (!target->type->add_breakpoint) {
 990                 target->type->add_breakpoint = dpm_add_breakpoint;
 991                 target->type->remove_breakpoint = dpm_remove_breakpoint;
 992         }
 993
 994         /* watchpoint setup */
 995         target->type->add_watchpoint = dpm_add_watchpoint;
 996         target->type->remove_watchpoint = dpm_remove_watchpoint;
 997
 998         /* FIXME add vector catch support */
 999
1000         dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
1001         dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
1002         dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
1003         dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
1004
1005         if (!dpm->dbp || !dpm->dwp) {
1006                 free(dpm->dbp);
1007                 free(dpm->dwp);
1008                 return ERROR_FAIL;
1009         }
1010
1011         LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1012                 target_name(target), dpm->nbp, dpm->nwp);
1013
1014         /* REVISIT ... and some of those breakpoints could match
1015          * execution context IDs...
1016          */
1017
1018         return ERROR_OK;
1019 }
1020
1021 /**
1022  * Reinitializes DPM state at the beginning of a new debug session
1023  * or after a reset which may have affected the debug module.
1024  */
1025 int arm_dpm_initialize(struct arm_dpm *dpm)
1026 {
1027         /* Disable all breakpoints and watchpoints at startup. */
1028         if (dpm->bpwp_disable) {
1029                 unsigned i;
1030
1031                 for (i = 0; i < dpm->nbp; i++) {
1032                         dpm->dbp[i].bpwp.number = i;
1033                         (void) dpm->bpwp_disable(dpm, i);
1034                 }
1035                 for (i = 0; i < dpm->nwp; i++) {
1036                         dpm->dwp[i].bpwp.number = 16 + i;
1037                         (void) dpm->bpwp_disable(dpm, 16 + i);
1038                 }
1039         } else
1040                 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1041                         target_name(dpm->arm->target));
1042
1043         return ERROR_OK;
1044 }