2 * Copyright (C) 2009 by David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include "armv4_5.h" /* REVISIT to become arm.h */
32 * Implements various ARM DPM operations using architectural debug registers.
33 * These routines layer over core-specific communication methods to cope with
34 * implementation differences between cores like ARM1136 and Cortex-A8.
37 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
38 * Routines *must* restore the original mode before returning!!
40 static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
45 /* restore previous mode */
46 if (mode == ARMV4_5_MODE_ANY)
47 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
49 /* else force to the specified mode */
53 retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
55 if (dpm->instr_cpsr_sync)
56 retval = dpm->instr_cpsr_sync(dpm);
61 /* just read the register -- rely on the core mode being right */
62 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
69 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
70 retval = dpm->instr_read_data_dcc(dpm,
71 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
75 /* "MOV r0, pc"; then return via DCC */
76 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
78 /* NOTE: this seems like a slightly awkward place to update
79 * this value ... but if the PC gets written (the only way
80 * to change what we compute), the arch spec says subsequent
81 * reads return values which are "unpredictable". So this
82 * is always right except in those broken-by-intent cases.
84 switch (dpm->arm->core_state) {
85 case ARMV4_5_STATE_ARM:
88 case ARMV4_5_STATE_THUMB:
89 case ARM_STATE_THUMB_EE:
92 case ARMV4_5_STATE_JAZELLE:
93 /* core-specific ... ? */
94 LOG_WARNING("Jazelle PC adjustment unknown");
99 /* 16: "MRS r0, CPSR"; then return via DCC
100 * 17: "MRS r0, SPSR"; then return via DCC
102 retval = dpm->instr_read_data_r0(dpm,
103 ARMV4_5_MRS(0, regnum & 1),
108 if (retval == ERROR_OK) {
109 buf_set_u32(r->value, 0, 32, value);
112 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
118 /* just write the register -- rely on the core mode being right */
119 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
122 uint32_t value = buf_get_u32(r->value, 0, 32);
126 /* load register from DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
127 retval = dpm->instr_write_data_dcc(dpm,
128 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
132 /* read r0 from DCC; then "MOV pc, r0" */
133 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
136 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
137 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
139 retval = dpm->instr_write_data_r0(dpm,
140 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
143 if (regnum == 16 && dpm->instr_cpsr_sync)
144 retval = dpm->instr_cpsr_sync(dpm);
149 if (retval == ERROR_OK) {
151 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
158 * Read basic registers of the the current context: R0 to R15, and CPSR;
159 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
160 * In normal operation this is called on entry to halting debug state,
161 * possibly after some other operations supporting restore of debug state
162 * or making sure the CPU is fully idle (drain write buffer, etc).
164 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
166 struct arm *arm = dpm->arm;
171 retval = dpm->prepare(dpm);
172 if (retval != ERROR_OK)
175 /* read R0 first (it's used for scratch), then CPSR */
176 r = arm->core_cache->reg_list + 0;
178 retval = dpm_read_reg(dpm, r, 0);
179 if (retval != ERROR_OK)
184 retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
185 if (retval != ERROR_OK)
188 /* update core mode and state, plus shadow mapping for R8..R14 */
189 arm_set_cpsr(arm, cpsr);
191 /* REVISIT we can probably avoid reading R1..R14, saving time... */
192 for (unsigned i = 1; i < 16; i++) {
193 r = arm_reg_current(arm, i);
197 retval = dpm_read_reg(dpm, r, i);
198 if (retval != ERROR_OK)
202 /* NOTE: SPSR ignored (if it's even relevant). */
205 /* (void) */ dpm->finish(dpm);
210 * Writes all modified core registers for all processor modes. In normal
211 * operation this is called on exit from halting debug state.
213 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm)
215 struct arm *arm = dpm->arm;
216 struct reg_cache *cache = arm->core_cache;
220 retval = dpm->prepare(dpm);
221 if (retval != ERROR_OK)
224 /* Scan the registers until we find one that's both dirty and
225 * eligible for flushing. Flush that and everything else that
226 * shares the same core mode setting. Typically this won't
227 * actually find anything to do...
230 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
234 /* check everything except our scratch register R0 */
235 for (unsigned i = 1; i < cache->num_regs; i++) {
239 /* also skip PC, CPSR, and non-dirty */
242 if (arm->cpsr == cache->reg_list + i)
244 if (!cache->reg_list[i].dirty)
247 r = cache->reg_list[i].arch_info;
250 /* may need to pick and set a mode */
252 enum armv4_5_mode tmode;
255 mode = tmode = r->mode;
257 /* cope with special cases */
260 /* r8..r12 "anything but FIQ" case;
261 * we "know" core mode is accurate
262 * since we haven't changed it yet
264 if (arm->core_mode == ARMV4_5_MODE_FIQ
267 tmode = ARMV4_5_MODE_USR;
275 /* REVISIT error checks */
276 if (tmode != ARMV4_5_MODE_ANY)
277 retval = dpm_modeswitch(dpm, tmode);
282 retval = dpm_write_reg(dpm,
290 /* Restore original CPSR ... assuming either that we changed it,
291 * or it's dirty. Must write PC to ensure the return address is
292 * defined, and must not write it before CPSR.
294 retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
295 arm->cpsr->dirty = false;
297 retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
298 cache->reg_list[15].dirty = false;
300 /* flush R0 -- it's *very* dirty by now */
301 retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
302 cache->reg_list[0].dirty = false;
304 /* (void) */ dpm->finish(dpm);
309 /* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
310 * specified register ... works around flakiness from ARM core calls.
311 * Caller already filtered out SPSR access; mode is never MODE_SYS
314 static enum armv4_5_mode dpm_mapmode(struct arm *arm,
315 unsigned num, enum armv4_5_mode mode)
317 enum armv4_5_mode amode = arm->core_mode;
319 /* don't switch if the mode is already correct */
320 if (amode == ARMV4_5_MODE_SYS)
321 amode = ARMV4_5_MODE_USR;
323 return ARMV4_5_MODE_ANY;
326 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
331 /* r8..r12 aren't shadowed for anything except FIQ */
333 if (mode == ARMV4_5_MODE_FIQ)
336 /* r13/sp, and r14/lr are always shadowed */
341 LOG_WARNING("invalid register #%u", num);
344 return ARMV4_5_MODE_ANY;
347 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
348 int regnum, enum armv4_5_mode mode)
350 struct arm_dpm *dpm = target_to_arm(target)->dpm;
353 if (regnum < 0 || regnum > 16)
354 return ERROR_INVALID_ARGUMENTS;
357 if (mode != ARMV4_5_MODE_ANY)
360 mode = dpm_mapmode(dpm->arm, regnum, mode);
362 /* REVISIT what happens if we try to read SPSR in a core mode
363 * which has no such register?
366 retval = dpm->prepare(dpm);
367 if (retval != ERROR_OK)
370 if (mode != ARMV4_5_MODE_ANY) {
371 retval = dpm_modeswitch(dpm, mode);
372 if (retval != ERROR_OK)
376 retval = dpm_read_reg(dpm, r, regnum);
377 /* always clean up, regardless of error */
379 if (mode != ARMV4_5_MODE_ANY)
380 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
383 /* (void) */ dpm->finish(dpm);
387 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
388 int regnum, enum armv4_5_mode mode, uint32_t value)
390 struct arm_dpm *dpm = target_to_arm(target)->dpm;
394 if (regnum < 0 || regnum > 16)
395 return ERROR_INVALID_ARGUMENTS;
398 if (mode != ARMV4_5_MODE_ANY)
401 mode = dpm_mapmode(dpm->arm, regnum, mode);
403 /* REVISIT what happens if we try to write SPSR in a core mode
404 * which has no such register?
407 retval = dpm->prepare(dpm);
408 if (retval != ERROR_OK)
411 if (mode != ARMV4_5_MODE_ANY) {
412 retval = dpm_modeswitch(dpm, mode);
413 if (retval != ERROR_OK)
417 retval = dpm_write_reg(dpm, r, regnum);
418 /* always clean up, regardless of error */
420 if (mode != ARMV4_5_MODE_ANY)
421 /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
424 /* (void) */ dpm->finish(dpm);
428 static int arm_dpm_full_context(struct target *target)
430 struct arm *arm = target_to_arm(target);
431 struct arm_dpm *dpm = arm->dpm;
432 struct reg_cache *cache = arm->core_cache;
436 retval = dpm->prepare(dpm);
437 if (retval != ERROR_OK)
441 enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
445 /* We "know" arm_dpm_read_current_registers() was called so
446 * the unmapped registers (R0..R7, PC, AND CPSR) and some
447 * view of R8..R14 are current. We also "know" oddities of
448 * register mapping: special cases for R8..R12 and SPSR.
450 * Pick some mode with unread registers and read them all.
453 for (unsigned i = 0; i < cache->num_regs; i++) {
456 if (cache->reg_list[i].valid)
458 r = cache->reg_list[i].arch_info;
460 /* may need to pick a mode and set CPSR */
465 /* For R8..R12 when we've entered debug
466 * state in FIQ mode... patch mode.
468 if (mode == ARMV4_5_MODE_ANY)
469 mode = ARMV4_5_MODE_USR;
471 /* REVISIT error checks */
472 retval = dpm_modeswitch(dpm, mode);
477 /* CPSR was read, so "R16" must mean SPSR */
478 retval = dpm_read_reg(dpm,
480 (r->num == 16) ? 17 : r->num);
486 retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
487 /* (void) */ dpm->finish(dpm);
493 * Hooks up this DPM to its associated target; call only once.
494 * Initially this only covers the register cache.
496 int arm_dpm_setup(struct arm_dpm *dpm)
498 struct arm *arm = dpm->arm;
499 struct target *target = arm->target;
500 struct reg_cache *cache;
504 arm->full_context = arm_dpm_full_context;
505 arm->read_core_reg = arm_dpm_read_core_reg;
506 arm->write_core_reg = arm_dpm_write_core_reg;
508 cache = armv4_5_build_reg_cache(target, arm);
512 *register_get_last_cache_p(&target->reg_cache) = cache;
517 * Reinitializes DPM state at the beginning of a new debug session
518 * or after a reset which may have affected the debug module.
520 int arm_dpm_initialize(struct arm_dpm *dpm)
522 /* FIXME -- nothing yet */