2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #ifndef __ARM_OPCODES_H
27 #define __ARM_OPCODES_H
29 /* ARM mode instructions */
31 /* Store multiple increment after
33 * List: for each bit in list: store register
34 * S: in priviledged mode: store user-mode registers
35 * W = 1: update the base register. W = 0: leave the base register untouched
37 #define ARMV4_5_STMIA(Rn, List, S, W) \
38 (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
40 /* Load multiple increment after
42 * List: for each bit in list: store register
43 * S: in priviledged mode: store user-mode registers
44 * W = 1: update the base register. W = 0: leave the base register untouched
46 #define ARMV4_5_LDMIA(Rn, List, S, W) \
47 (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
50 #define ARMV4_5_NOP (0xe1a08008)
52 /* Move PSR to general purpose register
53 * R = 1: SPSR R = 0: CPSR
56 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
59 * Rd: register to store
62 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
65 * Rd: register to load
68 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
70 /* Move general purpose register to PSR
71 * R = 1: SPSR R = 0: CPSR
73 * 1: control field 2: extension field 4: status field 8: flags field
76 #define ARMV4_5_MSR_GP(Rm, Field, R) \
77 (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
78 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
79 (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
81 /* Load Register Halfword Immediate Post-Index
82 * Rd: register to load
85 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
87 /* Load Register Byte Immediate Post-Index
88 * Rd: register to load
91 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
93 /* Store register Halfword Immediate Post-Index
94 * Rd: register to store
97 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
99 /* Store register Byte Immediate Post-Index
100 * Rd: register to store
103 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
106 * Im: Branch target (left-shifted by 2 bits, added to PC)
107 * L: 1: branch and link 0: branch only
109 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
111 /* Branch and exchange (ARM state)
112 * Rm: register holding branch target address
114 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
116 /* Move to ARM register from coprocessor
117 * CP: Coprocessor number
118 * op1: Coprocessor opcode
119 * Rd: destination register
120 * CRn: first coprocessor operand
121 * CRm: second coprocessor operand
122 * op2: Second coprocessor opcode
124 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
125 (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
126 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
128 /* Move to coprocessor from ARM register
129 * CP: Coprocessor number
130 * op1: Coprocessor opcode
131 * Rd: destination register
132 * CRn: first coprocessor operand
133 * CRm: second coprocessor operand
134 * op2: Second coprocessor opcode
136 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
137 (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
138 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
140 /* Breakpoint instruction (ARMv5)
141 * Im: 16-bit immediate
143 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
146 /* Thumb mode instructions
148 * FIXME there must be some reason all these opcodes are 32-bits
149 * not 16-bits ... this should get either an explanatory comment,
150 * or be changed not to duplicate the opcode.
153 /* Store register (Thumb mode)
154 * Rd: source register
157 #define ARMV4_5_T_STR(Rd, Rn) \
158 ((0x6000 | (Rd) | ((Rn) << 3)) | \
159 ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
161 /* Load register (Thumb state)
162 * Rd: destination register
165 #define ARMV4_5_T_LDR(Rd, Rn) \
166 ((0x6800 | ((Rn) << 3) | (Rd)) \
167 | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
169 /* Load multiple (Thumb state)
171 * List: for each bit in list: store register
173 #define ARMV4_5_T_LDMIA(Rn, List) \
174 ((0xc800 | ((Rn) << 8) | (List)) \
175 | ((0xc800 | ((Rn) << 8) | (List)) << 16))
177 /* Load register with PC relative addressing
178 * Rd: register to load
180 #define ARMV4_5_T_LDR_PCREL(Rd) \
181 ((0x4800 | ((Rd) << 8)) \
182 | ((0x4800 | ((Rd) << 8)) << 16))
184 /* Move hi register (Thumb mode)
185 * Rd: destination register
186 * Rm: source register
188 #define ARMV4_5_T_MOV(Rd, Rm) \
189 ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
190 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
191 | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
192 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
194 /* No operation (Thumb mode)
195 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
196 * architected NOPs, 16-bit and 32-bit.
198 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
200 /* Move immediate to register (Thumb state)
201 * Rd: destination register
202 * Im: 8-bit immediate value
204 #define ARMV4_5_T_MOV_IM(Rd, Im) \
205 ((0x2000 | ((Rd) << 8) | (Im)) \
206 | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
208 /* Branch and Exchange
209 * Rm: register containing branch target
211 #define ARMV4_5_T_BX(Rm) \
212 ((0x4700 | ((Rm) << 3)) \
213 | ((0x4700 | ((Rm) << 3)) << 16))
215 /* Branch (Thumb state)
218 #define ARMV4_5_T_B(Imm) \
220 | ((0xe000 | (Imm)) << 16))
222 /* Breakpoint instruction (ARMv5) (Thumb state)
223 * Im: 8-bit immediate
225 #define ARMV5_T_BKPT(Im) \
227 | ((0xbe00 | (Im)) << 16))
229 /* Move to Register from Special Register
230 * 32 bit Thumb2 instruction
231 * Rd: destination register
232 * SYSm: source special register
234 #define ARM_T2_MRS(Rd, SYSm) \
235 ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
237 /* Move from Register from Special Register
238 * 32 bit Thumb2 instruction
239 * Rd: source register
240 * SYSm: destination special register
242 #define ARM_T2_MSR(SYSm, Rn) \
243 ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
245 /* Change Processor State.
246 * 16 bit Thumb2 instruction
247 * Rd: source register
248 * IF: A_FLAG and/or I_FLAG and/or F_FLAG
253 #define ARM_T2_CPSID(IF) \
254 ((0xB660 | (1 << 8) | ((IF)&0x3)) \
255 | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
256 #define ARM_T2_CPSIE(IF) \
257 ((0xB660 | (0 << 8) | ((IF)&0x3)) \
258 | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
260 #endif /* __ARM_OPCODES_H */