1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
32 #include "breakpoints.h"
33 #include "arm_disassembler.h"
34 #include <helper/binarybuffer.h>
35 #include "algorithm.h"
38 /* offsets into armv4_5 core register cache */
40 /* ARMV4_5_CPSR = 31, */
41 ARMV4_5_SPSR_FIQ = 32,
42 ARMV4_5_SPSR_IRQ = 33,
43 ARMV4_5_SPSR_SVC = 34,
44 ARMV4_5_SPSR_ABT = 35,
45 ARMV4_5_SPSR_UND = 36,
49 static const uint8_t arm_usr_indices[17] = {
50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 static const uint8_t arm_fiq_indices[8] = {
54 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 static const uint8_t arm_irq_indices[3] = {
58 23, 24, ARMV4_5_SPSR_IRQ,
61 static const uint8_t arm_svc_indices[3] = {
62 25, 26, ARMV4_5_SPSR_SVC,
65 static const uint8_t arm_abt_indices[3] = {
66 27, 28, ARMV4_5_SPSR_ABT,
69 static const uint8_t arm_und_indices[3] = {
70 29, 30, ARMV4_5_SPSR_UND,
73 static const uint8_t arm_mon_indices[3] = {
80 /* For user and system modes, these list indices for all registers.
81 * otherwise they're just indices for the shadow registers and SPSR.
83 unsigned short n_indices;
84 const uint8_t *indices;
86 /* Seven modes are standard from ARM7 on. "System" and "User" share
87 * the same registers; other modes shadow from 3 to 8 registers.
92 .n_indices = ARRAY_SIZE(arm_usr_indices),
93 .indices = arm_usr_indices,
98 .n_indices = ARRAY_SIZE(arm_fiq_indices),
99 .indices = arm_fiq_indices,
102 .name = "Supervisor",
104 .n_indices = ARRAY_SIZE(arm_svc_indices),
105 .indices = arm_svc_indices,
110 .n_indices = ARRAY_SIZE(arm_abt_indices),
111 .indices = arm_abt_indices,
116 .n_indices = ARRAY_SIZE(arm_irq_indices),
117 .indices = arm_irq_indices,
120 .name = "Undefined instruction",
122 .n_indices = ARRAY_SIZE(arm_und_indices),
123 .indices = arm_und_indices,
128 .n_indices = ARRAY_SIZE(arm_usr_indices),
129 .indices = arm_usr_indices,
131 /* TrustZone "Security Extensions" add a secure monitor mode.
132 * This is distinct from a "debug monitor" which can support
133 * non-halting debug, in conjunction with some debuggers.
136 .name = "Secure Monitor",
138 .n_indices = ARRAY_SIZE(arm_mon_indices),
139 .indices = arm_mon_indices,
142 .name = "Secure Monitor ARM1176JZF-S",
143 .psr = ARM_MODE_1176_MON,
144 .n_indices = ARRAY_SIZE(arm_mon_indices),
145 .indices = arm_mon_indices,
148 /* These special modes are currently only supported
149 * by ARMv6M and ARMv7M profiles */
152 .psr = ARM_MODE_THREAD,
155 .name = "Thread (User)",
156 .psr = ARM_MODE_USER_THREAD,
160 .psr = ARM_MODE_HANDLER,
164 /** Map PSR mode bits to the name of an ARM processor operating mode. */
165 const char *arm_mode_name(unsigned psr_mode)
167 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
168 if (arm_mode_data[i].psr == psr_mode)
169 return arm_mode_data[i].name;
171 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
172 return "UNRECOGNIZED";
175 /** Return true iff the parameter denotes a valid ARM processor mode. */
176 bool is_arm_mode(unsigned psr_mode)
178 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
179 if (arm_mode_data[i].psr == psr_mode)
185 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
186 int arm_mode_to_number(enum arm_mode mode)
190 /* map MODE_ANY to user mode */
206 case ARM_MODE_1176_MON:
209 LOG_ERROR("invalid mode value encountered %d", mode);
214 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
215 enum arm_mode armv4_5_number_to_mode(int number)
235 LOG_ERROR("mode index out of bounds %d", number);
240 static const char *arm_state_strings[] = {
241 "ARM", "Thumb", "Jazelle", "ThumbEE",
244 /* Templates for ARM core registers.
246 * NOTE: offsets in this table are coupled to the arm_mode_data
247 * table above, the armv4_5_core_reg_map array below, and also to
248 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
250 static const struct {
251 /* The name is used for e.g. the "regs" command. */
254 /* The {cookie, mode} tuple uniquely identifies one register.
255 * In a given mode, cookies 0..15 map to registers R0..R15,
256 * with R13..R15 usually called SP, LR, PC.
258 * MODE_ANY is used as *input* to the mapping, and indicates
259 * various special cases (sigh) and errors.
261 * Cookie 16 is (currently) confusing, since it indicates
262 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
263 * (Exception modes have both CPSR and SPSR registers ...)
268 } arm_core_regs[] = {
269 /* IMPORTANT: we guarantee that the first eight cached registers
270 * correspond to r0..r7, and the fifteenth to PC, so that callers
271 * don't need to map them.
273 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
274 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
275 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
276 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
277 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
278 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
279 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
280 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
282 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
283 * them as MODE_ANY creates special cases. (ANY means
284 * "not mapped" elsewhere; here it's "everything but FIQ".)
286 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
287 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
288 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
289 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
290 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
292 /* Historical GDB mapping of indices:
293 * - 13-14 are sp and lr, but banked counterparts are used
294 * - 16-24 are left for deprecated 8 FPA + 1 FPS
298 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
299 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
300 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
302 /* guaranteed to be at index 15 */
303 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
304 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
305 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
306 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
307 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
308 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
310 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
311 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
313 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
314 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
316 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
317 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
319 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
320 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
322 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
323 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
325 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
326 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
327 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
328 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
329 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
330 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
332 /* These are only used for GDB target description, banked registers are accessed instead */
333 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
334 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
336 /* These exist only when the Security Extension (TrustZone) is present */
337 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
338 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
339 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
343 /* map core mode (USR, FIQ, ...) and register number to
344 * indices into the register cache
346 const int armv4_5_core_reg_map[8][17] = {
348 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
350 { /* FIQ (8 shadows of USR, vs normal 3) */
351 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
354 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
357 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
360 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
363 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
365 { /* SYS (same registers as USR) */
366 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
369 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
374 * Configures host-side ARM records to reflect the specified CPSR.
375 * Later, code can use arm_reg_current() to map register numbers
376 * according to how they are exposed by this mode.
378 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
380 enum arm_mode mode = cpsr & 0x1f;
383 /* NOTE: this may be called very early, before the register
384 * cache is set up. We can't defend against many errors, in
385 * particular against CPSRs that aren't valid *here* ...
388 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
389 arm->cpsr->valid = 1;
390 arm->cpsr->dirty = 0;
393 arm->core_mode = mode;
395 /* mode_to_number() warned; set up a somewhat-sane mapping */
396 num = arm_mode_to_number(mode);
402 arm->map = &armv4_5_core_reg_map[num][0];
403 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
405 : arm->core_cache->reg_list + arm->map[16];
407 /* Older ARMs won't have the J bit */
408 enum arm_state state;
410 if (cpsr & (1 << 5)) { /* T */
411 if (cpsr & (1 << 24)) { /* J */
412 LOG_WARNING("ThumbEE -- incomplete support");
413 state = ARM_STATE_THUMB_EE;
415 state = ARM_STATE_THUMB;
417 if (cpsr & (1 << 24)) { /* J */
418 LOG_ERROR("Jazelle state handling is BROKEN!");
419 state = ARM_STATE_JAZELLE;
421 state = ARM_STATE_ARM;
423 arm->core_state = state;
425 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
427 arm_state_strings[arm->core_state]);
431 * Returns handle to the register currently mapped to a given number.
432 * Someone must have called arm_set_cpsr() before.
434 * \param arm This core's state and registers are used.
435 * \param regnum From 0..15 corresponding to R0..R14 and PC.
436 * Note that R0..R7 don't require mapping; you may access those
437 * as the first eight entries in the register cache. Likewise
438 * R15 (PC) doesn't need mapping; you may also access it directly.
439 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
440 * CPSR (arm->cpsr) is also not mapped.
442 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
450 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
451 r = arm->core_cache->reg_list + regnum;
453 r = arm->core_cache->reg_list + arm->map[regnum];
455 /* e.g. invalid CPSR said "secure monitor" mode on a core
456 * that doesn't support it...
459 LOG_ERROR("Invalid CPSR mode");
460 r = arm->core_cache->reg_list + regnum;
466 static const uint8_t arm_gdb_dummy_fp_value[12];
468 static struct reg_feature arm_gdb_dummy_fp_features = {
469 .name = "net.sourceforge.openocd.fake_fpa"
473 * Dummy FPA registers are required to support GDB on ARM.
474 * Register packets require eight obsolete FPA register values.
475 * Modern ARM cores use Vector Floating Point (VFP), if they
476 * have any floating point support. VFP is not FPA-compatible.
478 struct reg arm_gdb_dummy_fp_reg = {
479 .name = "GDB dummy FPA register",
480 .value = (uint8_t *) arm_gdb_dummy_fp_value,
485 .feature = &arm_gdb_dummy_fp_features,
489 static const uint8_t arm_gdb_dummy_fps_value[4];
492 * Dummy FPA status registers are required to support GDB on ARM.
493 * Register packets require an obsolete FPA status register.
495 struct reg arm_gdb_dummy_fps_reg = {
496 .name = "GDB dummy FPA status register",
497 .value = (uint8_t *) arm_gdb_dummy_fps_value,
502 .feature = &arm_gdb_dummy_fp_features,
506 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
508 static void arm_gdb_dummy_init(void)
510 register_init_dummy(&arm_gdb_dummy_fp_reg);
511 register_init_dummy(&arm_gdb_dummy_fps_reg);
514 static int armv4_5_get_core_reg(struct reg *reg)
517 struct arm_reg *reg_arch_info = reg->arch_info;
518 struct target *target = reg_arch_info->target;
520 if (target->state != TARGET_HALTED) {
521 LOG_ERROR("Target not halted");
522 return ERROR_TARGET_NOT_HALTED;
525 retval = reg_arch_info->arm->read_core_reg(target, reg,
526 reg_arch_info->num, reg_arch_info->mode);
527 if (retval == ERROR_OK) {
535 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
537 struct arm_reg *reg_arch_info = reg->arch_info;
538 struct target *target = reg_arch_info->target;
539 struct arm *armv4_5_target = target_to_arm(target);
540 uint32_t value = buf_get_u32(buf, 0, 32);
542 if (target->state != TARGET_HALTED) {
543 LOG_ERROR("Target not halted");
544 return ERROR_TARGET_NOT_HALTED;
547 /* Except for CPSR, the "reg" command exposes a writeback model
548 * for the register cache.
550 if (reg == armv4_5_target->cpsr) {
551 arm_set_cpsr(armv4_5_target, value);
553 /* Older cores need help to be in ARM mode during halt
554 * mode debug, so we clear the J and T bits if we flush.
555 * For newer cores (v6/v7a/v7r) we don't need that, but
556 * it won't hurt since CPSR is always flushed anyway.
558 if (armv4_5_target->core_mode !=
559 (enum arm_mode)(value & 0x1f)) {
560 LOG_DEBUG("changing ARM core mode to '%s'",
561 arm_mode_name(value & 0x1f));
562 value &= ~((1 << 24) | (1 << 5));
564 buf_set_u32(t, 0, 32, value);
565 armv4_5_target->write_core_reg(target, reg,
566 16, ARM_MODE_ANY, t);
569 buf_set_u32(reg->value, 0, 32, value);
577 static const struct reg_arch_type arm_reg_type = {
578 .get = armv4_5_get_core_reg,
579 .set = armv4_5_set_core_reg,
582 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
584 int num_regs = ARRAY_SIZE(arm_core_regs);
585 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
586 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
587 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
590 if (!cache || !reg_list || !reg_arch_info) {
597 cache->name = "ARM registers";
599 cache->reg_list = reg_list;
602 for (i = 0; i < num_regs; i++) {
603 /* Skip registers this core doesn't expose */
604 if (arm_core_regs[i].mode == ARM_MODE_MON
605 && arm->core_type != ARM_MODE_MON)
608 /* REVISIT handle Cortex-M, which only shadows R13/SP */
610 reg_arch_info[i].num = arm_core_regs[i].cookie;
611 reg_arch_info[i].mode = arm_core_regs[i].mode;
612 reg_arch_info[i].target = target;
613 reg_arch_info[i].arm = arm;
615 reg_list[i].name = arm_core_regs[i].name;
616 reg_list[i].number = arm_core_regs[i].gdb_index;
617 reg_list[i].size = 32;
618 reg_list[i].value = reg_arch_info[i].value;
619 reg_list[i].type = &arm_reg_type;
620 reg_list[i].arch_info = ®_arch_info[i];
621 reg_list[i].exist = true;
623 /* This really depends on the calling convention in use */
624 reg_list[i].caller_save = false;
626 /* Registers data type, as used by GDB target description */
627 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
628 switch (arm_core_regs[i].cookie) {
630 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
634 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
637 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
641 /* let GDB shows banked registers only in "info all-reg" */
642 reg_list[i].feature = malloc(sizeof(struct reg_feature));
643 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
644 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
645 reg_list[i].group = "general";
647 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
648 reg_list[i].group = "banked";
654 arm->pc = reg_list + 15;
655 arm->cpsr = reg_list + ARMV4_5_CPSR;
656 arm->core_cache = cache;
660 int arm_arch_state(struct target *target)
662 struct arm *arm = target_to_arm(target);
664 if (arm->common_magic != ARM_COMMON_MAGIC) {
665 LOG_ERROR("BUG: called for a non-ARM target");
669 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
670 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
671 arm_state_strings[arm->core_state],
672 debug_reason_name(target),
673 arm_mode_name(arm->core_mode),
674 buf_get_u32(arm->cpsr->value, 0, 32),
675 buf_get_u32(arm->pc->value, 0, 32),
676 arm->is_semihosting ? ", semihosting" : "");
681 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
682 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
684 COMMAND_HANDLER(handle_armv4_5_reg_command)
686 struct target *target = get_current_target(CMD_CTX);
687 struct arm *arm = target_to_arm(target);
691 command_print(CMD_CTX, "current target isn't an ARM");
695 if (target->state != TARGET_HALTED) {
696 command_print(CMD_CTX, "error: target must be halted for register accesses");
700 if (arm->core_type != ARM_MODE_ANY) {
701 command_print(CMD_CTX,
702 "Microcontroller Profile not supported - use standard reg cmd");
706 if (!is_arm_mode(arm->core_mode)) {
707 LOG_ERROR("not a valid arm core mode - communication failure?");
711 if (!arm->full_context) {
712 command_print(CMD_CTX, "error: target doesn't support %s",
717 regs = arm->core_cache->reg_list;
719 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
724 /* label this bank of registers (or shadows) */
725 switch (arm_mode_data[mode].psr) {
729 name = "System and User";
733 if (arm->core_type != ARM_MODE_MON)
737 name = arm_mode_data[mode].name;
741 command_print(CMD_CTX, "%s%s mode %sregisters",
744 /* display N rows of up to 4 registers each */
745 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
749 for (unsigned j = 0; j < 4; j++, i++) {
751 struct reg *reg = regs;
753 if (i >= arm_mode_data[mode].n_indices)
756 reg += arm_mode_data[mode].indices[i];
758 /* REVISIT be smarter about faults... */
760 arm->full_context(target);
762 value = buf_get_u32(reg->value, 0, 32);
763 output_len += snprintf(output + output_len,
764 sizeof(output) - output_len,
765 "%8s: %8.8" PRIx32 " ",
768 command_print(CMD_CTX, "%s", output);
775 COMMAND_HANDLER(handle_armv4_5_core_state_command)
777 struct target *target = get_current_target(CMD_CTX);
778 struct arm *arm = target_to_arm(target);
781 command_print(CMD_CTX, "current target isn't an ARM");
785 if (arm->core_type == ARM_MODE_THREAD) {
786 /* armv7m not supported */
787 command_print(CMD_CTX, "Unsupported Command");
792 if (strcmp(CMD_ARGV[0], "arm") == 0)
793 arm->core_state = ARM_STATE_ARM;
794 if (strcmp(CMD_ARGV[0], "thumb") == 0)
795 arm->core_state = ARM_STATE_THUMB;
798 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
803 COMMAND_HANDLER(handle_arm_disassemble_command)
805 int retval = ERROR_OK;
806 struct target *target = get_current_target(CMD_CTX);
808 if (target == NULL) {
809 LOG_ERROR("No target selected");
813 struct arm *arm = target_to_arm(target);
819 command_print(CMD_CTX, "current target isn't an ARM");
823 if (arm->core_type == ARM_MODE_THREAD) {
824 /* armv7m is always thumb mode */
830 if (strcmp(CMD_ARGV[2], "thumb") != 0)
835 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
838 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
839 if (address & 0x01) {
841 command_print(CMD_CTX, "Disassemble as Thumb");
850 retval = ERROR_COMMAND_SYNTAX_ERROR;
853 while (count-- > 0) {
854 struct arm_instruction cur_instruction;
857 /* Always use Thumb2 disassembly for best handling
858 * of 32-bit BL/BLX, and to work with newer cores
859 * (some ARMv6, all ARMv7) that use Thumb2.
861 retval = thumb2_opcode(target, address,
863 if (retval != ERROR_OK)
868 retval = target_read_u32(target, address, &opcode);
869 if (retval != ERROR_OK)
871 retval = arm_evaluate_opcode(opcode, address,
872 &cur_instruction) != ERROR_OK;
873 if (retval != ERROR_OK)
876 command_print(CMD_CTX, "%s", cur_instruction.text);
877 address += cur_instruction.instruction_size;
883 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
885 struct command_context *context;
886 struct target *target;
890 context = current_command_context(interp);
891 assert(context != NULL);
893 target = get_current_target(context);
894 if (target == NULL) {
895 LOG_ERROR("%s: no current target", __func__);
898 if (!target_was_examined(target)) {
899 LOG_ERROR("%s: not yet examined", target_name(target));
902 arm = target_to_arm(target);
904 LOG_ERROR("%s: not an ARM", target_name(target));
908 if ((argc < 6) || (argc > 7)) {
909 /* FIXME use the command name to verify # params... */
910 LOG_ERROR("%s: wrong number of arguments", __func__);
922 /* NOTE: parameter sequence matches ARM instruction set usage:
923 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
924 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
925 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
927 retval = Jim_GetLong(interp, argv[1], &l);
928 if (retval != JIM_OK)
931 LOG_ERROR("%s: %s %d out of range", __func__,
932 "coprocessor", (int) l);
937 retval = Jim_GetLong(interp, argv[2], &l);
938 if (retval != JIM_OK)
941 LOG_ERROR("%s: %s %d out of range", __func__,
947 retval = Jim_GetLong(interp, argv[3], &l);
948 if (retval != JIM_OK)
951 LOG_ERROR("%s: %s %d out of range", __func__,
957 retval = Jim_GetLong(interp, argv[4], &l);
958 if (retval != JIM_OK)
961 LOG_ERROR("%s: %s %d out of range", __func__,
967 retval = Jim_GetLong(interp, argv[5], &l);
968 if (retval != JIM_OK)
971 LOG_ERROR("%s: %s %d out of range", __func__,
979 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
980 * that could easily be a typo! Check both...
982 * FIXME change the call syntax here ... simplest to just pass
983 * the MRC() or MCR() instruction to be executed. That will also
984 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
985 * if that's ever needed.
988 retval = Jim_GetLong(interp, argv[6], &l);
989 if (retval != JIM_OK)
993 /* NOTE: parameters reordered! */
994 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
995 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
996 if (retval != ERROR_OK)
999 /* NOTE: parameters reordered! */
1000 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1001 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1002 if (retval != ERROR_OK)
1005 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1011 COMMAND_HANDLER(handle_arm_semihosting_command)
1013 struct target *target = get_current_target(CMD_CTX);
1015 if (target == NULL) {
1016 LOG_ERROR("No target selected");
1020 struct arm *arm = target_to_arm(target);
1023 command_print(CMD_CTX, "current target isn't an ARM");
1027 if (!arm->setup_semihosting) {
1028 command_print(CMD_CTX, "semihosting not supported for current target");
1035 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1037 if (!target_was_examined(target)) {
1038 LOG_ERROR("Target not examined yet");
1042 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1043 LOG_ERROR("Failed to Configure semihosting");
1047 /* FIXME never let that "catch" be dropped! */
1048 arm->is_semihosting = semihosting;
1051 command_print(CMD_CTX, "semihosting is %s",
1053 ? "enabled" : "disabled");
1058 static const struct command_registration arm_exec_command_handlers[] = {
1061 .handler = handle_armv4_5_reg_command,
1062 .mode = COMMAND_EXEC,
1063 .help = "display ARM core registers",
1067 .name = "core_state",
1068 .handler = handle_armv4_5_core_state_command,
1069 .mode = COMMAND_EXEC,
1070 .usage = "['arm'|'thumb']",
1071 .help = "display/change ARM core state",
1074 .name = "disassemble",
1075 .handler = handle_arm_disassemble_command,
1076 .mode = COMMAND_EXEC,
1077 .usage = "address [count ['thumb']]",
1078 .help = "disassemble instructions ",
1082 .mode = COMMAND_EXEC,
1083 .jim_handler = &jim_mcrmrc,
1084 .help = "write coprocessor register",
1085 .usage = "cpnum op1 CRn CRm op2 value",
1089 .jim_handler = &jim_mcrmrc,
1090 .help = "read coprocessor register",
1091 .usage = "cpnum op1 CRn CRm op2",
1095 .handler = handle_arm_semihosting_command,
1096 .mode = COMMAND_EXEC,
1097 .usage = "['enable'|'disable']",
1098 .help = "activate support for semihosting operations",
1101 COMMAND_REGISTRATION_DONE
1103 const struct command_registration arm_command_handlers[] = {
1106 .mode = COMMAND_ANY,
1107 .help = "ARM command group",
1109 .chain = arm_exec_command_handlers,
1111 COMMAND_REGISTRATION_DONE
1114 int arm_get_gdb_reg_list(struct target *target,
1115 struct reg **reg_list[], int *reg_list_size,
1116 enum target_register_class reg_class)
1118 struct arm *arm = target_to_arm(target);
1121 if (!is_arm_mode(arm->core_mode)) {
1122 LOG_ERROR("not a valid arm core mode - communication failure?");
1126 switch (reg_class) {
1127 case REG_CLASS_GENERAL:
1128 *reg_list_size = 26;
1129 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1131 for (i = 0; i < 16; i++)
1132 (*reg_list)[i] = arm_reg_current(arm, i);
1134 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1135 for (i = 16; i < 24; i++)
1136 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1137 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1139 (*reg_list)[25] = arm->cpsr;
1145 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1146 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1148 for (i = 0; i < 16; i++)
1149 (*reg_list)[i] = arm_reg_current(arm, i);
1151 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1152 int reg_index = arm->core_cache->reg_list[i].number;
1153 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1154 && arm->core_type != ARM_MODE_MON))
1155 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1158 /* When we supply the target description, there is no need for fake FPA */
1159 for (i = 16; i < 24; i++) {
1160 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1161 (*reg_list)[i]->size = 0;
1163 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1164 (*reg_list)[24]->size = 0;
1170 LOG_ERROR("not a valid register class type in query.");
1176 /* wait for execution to complete and check exit point */
1177 static int armv4_5_run_algorithm_completion(struct target *target,
1178 uint32_t exit_point,
1183 struct arm *arm = target_to_arm(target);
1185 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1186 if (retval != ERROR_OK)
1188 if (target->state != TARGET_HALTED) {
1189 retval = target_halt(target);
1190 if (retval != ERROR_OK)
1192 retval = target_wait_state(target, TARGET_HALTED, 500);
1193 if (retval != ERROR_OK)
1195 return ERROR_TARGET_TIMEOUT;
1198 /* fast exit: ARMv5+ code can use BKPT */
1199 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1201 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1202 buf_get_u32(arm->pc->value, 0, 32));
1203 return ERROR_TARGET_TIMEOUT;
1209 int armv4_5_run_algorithm_inner(struct target *target,
1210 int num_mem_params, struct mem_param *mem_params,
1211 int num_reg_params, struct reg_param *reg_params,
1212 uint32_t entry_point, uint32_t exit_point,
1213 int timeout_ms, void *arch_info,
1214 int (*run_it)(struct target *target, uint32_t exit_point,
1215 int timeout_ms, void *arch_info))
1217 struct arm *arm = target_to_arm(target);
1218 struct arm_algorithm *arm_algorithm_info = arch_info;
1219 enum arm_state core_state = arm->core_state;
1220 uint32_t context[17];
1222 int exit_breakpoint_size = 0;
1224 int retval = ERROR_OK;
1226 LOG_DEBUG("Running algorithm");
1228 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1229 LOG_ERROR("current target isn't an ARMV4/5 target");
1230 return ERROR_TARGET_INVALID;
1233 if (target->state != TARGET_HALTED) {
1234 LOG_WARNING("target not halted");
1235 return ERROR_TARGET_NOT_HALTED;
1238 if (!is_arm_mode(arm->core_mode)) {
1239 LOG_ERROR("not a valid arm core mode - communication failure?");
1243 /* armv5 and later can terminate with BKPT instruction; less overhead */
1244 if (!exit_point && arm->is_armv4) {
1245 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1249 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1250 * they'll be restored later.
1252 for (i = 0; i <= 16; i++) {
1255 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1256 arm_algorithm_info->core_mode, i);
1258 arm->read_core_reg(target, r, i,
1259 arm_algorithm_info->core_mode);
1260 context[i] = buf_get_u32(r->value, 0, 32);
1262 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1264 for (i = 0; i < num_mem_params; i++) {
1265 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1266 mem_params[i].value);
1267 if (retval != ERROR_OK)
1271 for (i = 0; i < num_reg_params; i++) {
1272 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1274 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1275 return ERROR_COMMAND_SYNTAX_ERROR;
1278 if (reg->size != reg_params[i].size) {
1279 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1280 reg_params[i].reg_name);
1281 return ERROR_COMMAND_SYNTAX_ERROR;
1284 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1285 if (retval != ERROR_OK)
1289 arm->core_state = arm_algorithm_info->core_state;
1290 if (arm->core_state == ARM_STATE_ARM)
1291 exit_breakpoint_size = 4;
1292 else if (arm->core_state == ARM_STATE_THUMB)
1293 exit_breakpoint_size = 2;
1295 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1296 return ERROR_COMMAND_SYNTAX_ERROR;
1299 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1300 LOG_DEBUG("setting core_mode: 0x%2.2x",
1301 arm_algorithm_info->core_mode);
1302 buf_set_u32(arm->cpsr->value, 0, 5,
1303 arm_algorithm_info->core_mode);
1304 arm->cpsr->dirty = 1;
1305 arm->cpsr->valid = 1;
1308 /* terminate using a hardware or (ARMv5+) software breakpoint */
1310 retval = breakpoint_add(target, exit_point,
1311 exit_breakpoint_size, BKPT_HARD);
1312 if (retval != ERROR_OK) {
1313 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1314 return ERROR_TARGET_FAILURE;
1318 retval = target_resume(target, 0, entry_point, 1, 1);
1319 if (retval != ERROR_OK)
1321 retval = run_it(target, exit_point, timeout_ms, arch_info);
1324 breakpoint_remove(target, exit_point);
1326 if (retval != ERROR_OK)
1329 for (i = 0; i < num_mem_params; i++) {
1330 if (mem_params[i].direction != PARAM_OUT) {
1331 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1333 mem_params[i].value);
1334 if (retvaltemp != ERROR_OK)
1335 retval = retvaltemp;
1339 for (i = 0; i < num_reg_params; i++) {
1340 if (reg_params[i].direction != PARAM_OUT) {
1342 struct reg *reg = register_get_by_name(arm->core_cache,
1343 reg_params[i].reg_name,
1346 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1347 retval = ERROR_COMMAND_SYNTAX_ERROR;
1351 if (reg->size != reg_params[i].size) {
1353 "BUG: register '%s' size doesn't match reg_params[i].size",
1354 reg_params[i].reg_name);
1355 retval = ERROR_COMMAND_SYNTAX_ERROR;
1359 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1363 /* restore everything we saved before (17 or 18 registers) */
1364 for (i = 0; i <= 16; i++) {
1366 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1367 arm_algorithm_info->core_mode, i).value, 0, 32);
1368 if (regvalue != context[i]) {
1369 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1370 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1371 arm_algorithm_info->core_mode, i).name, context[i]);
1372 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1373 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1374 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1376 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1381 arm_set_cpsr(arm, cpsr);
1382 arm->cpsr->dirty = 1;
1384 arm->core_state = core_state;
1389 int armv4_5_run_algorithm(struct target *target,
1391 struct mem_param *mem_params,
1393 struct reg_param *reg_params,
1394 uint32_t entry_point,
1395 uint32_t exit_point,
1399 return armv4_5_run_algorithm_inner(target,
1408 armv4_5_run_algorithm_completion);
1412 * Runs ARM code in the target to calculate a CRC32 checksum.
1415 int arm_checksum_memory(struct target *target,
1416 uint32_t address, uint32_t count, uint32_t *checksum)
1418 struct working_area *crc_algorithm;
1419 struct arm_algorithm arm_algo;
1420 struct arm *arm = target_to_arm(target);
1421 struct reg_param reg_params[2];
1424 uint32_t exit_var = 0;
1426 static const uint8_t arm_crc_code_le[] = {
1427 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1430 assert(sizeof(arm_crc_code_le) % 4 == 0);
1432 retval = target_alloc_working_area(target,
1433 sizeof(arm_crc_code_le), &crc_algorithm);
1434 if (retval != ERROR_OK)
1437 /* convert code into a buffer in target endianness */
1438 for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1439 retval = target_write_u32(target,
1440 crc_algorithm->address + i * sizeof(uint32_t),
1441 le_to_h_u32(&arm_crc_code_le[i * 4]));
1442 if (retval != ERROR_OK)
1446 arm_algo.common_magic = ARM_COMMON_MAGIC;
1447 arm_algo.core_mode = ARM_MODE_SVC;
1448 arm_algo.core_state = ARM_STATE_ARM;
1450 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
1451 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1453 buf_set_u32(reg_params[0].value, 0, 32, address);
1454 buf_set_u32(reg_params[1].value, 0, 32, count);
1456 /* 20 second timeout/megabyte */
1457 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1459 /* armv4 must exit using a hardware breakpoint */
1461 exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1463 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1464 crc_algorithm->address,
1466 timeout, &arm_algo);
1468 if (retval == ERROR_OK)
1469 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1471 LOG_ERROR("error executing ARM crc algorithm");
1473 destroy_reg_param(®_params[0]);
1474 destroy_reg_param(®_params[1]);
1477 target_free_working_area(target, crc_algorithm);
1483 * Runs ARM code in the target to check whether a memory block holds
1484 * all ones. NOR flash which has been erased, and thus may be written,
1488 int arm_blank_check_memory(struct target *target,
1489 uint32_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
1491 struct working_area *check_algorithm;
1492 struct reg_param reg_params[3];
1493 struct arm_algorithm arm_algo;
1494 struct arm *arm = target_to_arm(target);
1497 uint32_t exit_var = 0;
1499 static const uint8_t check_code_le[] = {
1500 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1503 assert(sizeof(check_code_le) % 4 == 0);
1505 if (erased_value != 0xff) {
1506 LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1511 /* make sure we have a working area */
1512 retval = target_alloc_working_area(target,
1513 sizeof(check_code_le), &check_algorithm);
1514 if (retval != ERROR_OK)
1517 /* convert code into a buffer in target endianness */
1518 for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1519 retval = target_write_u32(target,
1520 check_algorithm->address
1521 + i * sizeof(uint32_t),
1522 le_to_h_u32(&check_code_le[i * 4]));
1523 if (retval != ERROR_OK)
1527 arm_algo.common_magic = ARM_COMMON_MAGIC;
1528 arm_algo.core_mode = ARM_MODE_SVC;
1529 arm_algo.core_state = ARM_STATE_ARM;
1531 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1532 buf_set_u32(reg_params[0].value, 0, 32, address);
1534 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1535 buf_set_u32(reg_params[1].value, 0, 32, count);
1537 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
1538 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1540 /* armv4 must exit using a hardware breakpoint */
1542 exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1544 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1545 check_algorithm->address,
1549 if (retval == ERROR_OK)
1550 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1552 destroy_reg_param(®_params[0]);
1553 destroy_reg_param(®_params[1]);
1554 destroy_reg_param(®_params[2]);
1557 target_free_working_area(target, check_algorithm);
1562 static int arm_full_context(struct target *target)
1564 struct arm *arm = target_to_arm(target);
1565 unsigned num_regs = arm->core_cache->num_regs;
1566 struct reg *reg = arm->core_cache->reg_list;
1567 int retval = ERROR_OK;
1569 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1572 retval = armv4_5_get_core_reg(reg);
1577 static int arm_default_mrc(struct target *target, int cpnum,
1578 uint32_t op1, uint32_t op2,
1579 uint32_t CRn, uint32_t CRm,
1582 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1586 static int arm_default_mcr(struct target *target, int cpnum,
1587 uint32_t op1, uint32_t op2,
1588 uint32_t CRn, uint32_t CRm,
1591 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1595 int arm_init_arch_info(struct target *target, struct arm *arm)
1597 target->arch_info = arm;
1598 arm->target = target;
1600 arm->common_magic = ARM_COMMON_MAGIC;
1602 /* core_type may be overridden by subtype logic */
1603 if (arm->core_type != ARM_MODE_THREAD) {
1604 arm->core_type = ARM_MODE_ANY;
1605 arm_set_cpsr(arm, ARM_MODE_USR);
1608 /* default full_context() has no core-specific optimizations */
1609 if (!arm->full_context && arm->read_core_reg)
1610 arm->full_context = arm_full_context;
1613 arm->mrc = arm_default_mrc;
1615 arm->mcr = arm_default_mcr;