1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
32 #include "breakpoints.h"
33 #include "arm_disassembler.h"
34 #include <helper/binarybuffer.h>
35 #include "algorithm.h"
38 /* offsets into armv4_5 core register cache */
40 /* ARMV4_5_CPSR = 31, */
41 ARMV4_5_SPSR_FIQ = 32,
42 ARMV4_5_SPSR_IRQ = 33,
43 ARMV4_5_SPSR_SVC = 34,
44 ARMV4_5_SPSR_ABT = 35,
45 ARMV4_5_SPSR_UND = 36,
49 static const uint8_t arm_usr_indices[17] = {
50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 static const uint8_t arm_fiq_indices[8] = {
54 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 static const uint8_t arm_irq_indices[3] = {
58 23, 24, ARMV4_5_SPSR_IRQ,
61 static const uint8_t arm_svc_indices[3] = {
62 25, 26, ARMV4_5_SPSR_SVC,
65 static const uint8_t arm_abt_indices[3] = {
66 27, 28, ARMV4_5_SPSR_ABT,
69 static const uint8_t arm_und_indices[3] = {
70 29, 30, ARMV4_5_SPSR_UND,
73 static const uint8_t arm_mon_indices[3] = {
80 /* For user and system modes, these list indices for all registers.
81 * otherwise they're just indices for the shadow registers and SPSR.
83 unsigned short n_indices;
84 const uint8_t *indices;
86 /* Seven modes are standard from ARM7 on. "System" and "User" share
87 * the same registers; other modes shadow from 3 to 8 registers.
92 .n_indices = ARRAY_SIZE(arm_usr_indices),
93 .indices = arm_usr_indices,
98 .n_indices = ARRAY_SIZE(arm_fiq_indices),
99 .indices = arm_fiq_indices,
102 .name = "Supervisor",
104 .n_indices = ARRAY_SIZE(arm_svc_indices),
105 .indices = arm_svc_indices,
110 .n_indices = ARRAY_SIZE(arm_abt_indices),
111 .indices = arm_abt_indices,
116 .n_indices = ARRAY_SIZE(arm_irq_indices),
117 .indices = arm_irq_indices,
120 .name = "Undefined instruction",
122 .n_indices = ARRAY_SIZE(arm_und_indices),
123 .indices = arm_und_indices,
128 .n_indices = ARRAY_SIZE(arm_usr_indices),
129 .indices = arm_usr_indices,
131 /* TrustZone "Security Extensions" add a secure monitor mode.
132 * This is distinct from a "debug monitor" which can support
133 * non-halting debug, in conjunction with some debuggers.
136 .name = "Secure Monitor",
138 .n_indices = ARRAY_SIZE(arm_mon_indices),
139 .indices = arm_mon_indices,
142 .name = "Secure Monitor ARM1176JZF-S",
143 .psr = ARM_MODE_1176_MON,
144 .n_indices = ARRAY_SIZE(arm_mon_indices),
145 .indices = arm_mon_indices,
148 /* These special modes are currently only supported
149 * by ARMv6M and ARMv7M profiles */
152 .psr = ARM_MODE_THREAD,
155 .name = "Thread (User)",
156 .psr = ARM_MODE_USER_THREAD,
160 .psr = ARM_MODE_HANDLER,
164 /** Map PSR mode bits to the name of an ARM processor operating mode. */
165 const char *arm_mode_name(unsigned psr_mode)
167 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
168 if (arm_mode_data[i].psr == psr_mode)
169 return arm_mode_data[i].name;
171 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
172 return "UNRECOGNIZED";
175 /** Return true iff the parameter denotes a valid ARM processor mode. */
176 bool is_arm_mode(unsigned psr_mode)
178 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
179 if (arm_mode_data[i].psr == psr_mode)
185 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
186 int arm_mode_to_number(enum arm_mode mode)
190 /* map MODE_ANY to user mode */
206 case ARM_MODE_1176_MON:
209 LOG_ERROR("invalid mode value encountered %d", mode);
214 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
215 enum arm_mode armv4_5_number_to_mode(int number)
235 LOG_ERROR("mode index out of bounds %d", number);
240 static const char *arm_state_strings[] = {
241 "ARM", "Thumb", "Jazelle", "ThumbEE",
244 /* Templates for ARM core registers.
246 * NOTE: offsets in this table are coupled to the arm_mode_data
247 * table above, the armv4_5_core_reg_map array below, and also to
248 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
250 static const struct {
251 /* The name is used for e.g. the "regs" command. */
254 /* The {cookie, mode} tuple uniquely identifies one register.
255 * In a given mode, cookies 0..15 map to registers R0..R15,
256 * with R13..R15 usually called SP, LR, PC.
258 * MODE_ANY is used as *input* to the mapping, and indicates
259 * various special cases (sigh) and errors.
261 * Cookie 16 is (currently) confusing, since it indicates
262 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
263 * (Exception modes have both CPSR and SPSR registers ...)
268 } arm_core_regs[] = {
269 /* IMPORTANT: we guarantee that the first eight cached registers
270 * correspond to r0..r7, and the fifteenth to PC, so that callers
271 * don't need to map them.
273 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
274 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
275 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
276 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
277 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
278 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
279 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
280 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
282 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
283 * them as MODE_ANY creates special cases. (ANY means
284 * "not mapped" elsewhere; here it's "everything but FIQ".)
286 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
287 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
288 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
289 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
290 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
292 /* Historical GDB mapping of indices:
293 * - 13-14 are sp and lr, but banked counterparts are used
294 * - 16-24 are left for deprecated 8 FPA + 1 FPS
298 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
299 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
300 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
302 /* guaranteed to be at index 15 */
303 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
304 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
305 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
306 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
307 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
308 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
310 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
311 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
313 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
314 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
316 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
317 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
319 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
320 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
322 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
323 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
325 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
326 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
327 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
328 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
329 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
330 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
332 /* These are only used for GDB target description, banked registers are accessed instead */
333 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
334 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
336 /* These exist only when the Security Extension (TrustZone) is present */
337 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
338 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
339 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
343 /* map core mode (USR, FIQ, ...) and register number to
344 * indices into the register cache
346 const int armv4_5_core_reg_map[8][17] = {
348 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
350 { /* FIQ (8 shadows of USR, vs normal 3) */
351 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
354 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
357 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
360 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
363 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
365 { /* SYS (same registers as USR) */
366 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
369 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
374 * Configures host-side ARM records to reflect the specified CPSR.
375 * Later, code can use arm_reg_current() to map register numbers
376 * according to how they are exposed by this mode.
378 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
380 enum arm_mode mode = cpsr & 0x1f;
383 /* NOTE: this may be called very early, before the register
384 * cache is set up. We can't defend against many errors, in
385 * particular against CPSRs that aren't valid *here* ...
388 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
389 arm->cpsr->valid = 1;
390 arm->cpsr->dirty = 0;
393 arm->core_mode = mode;
395 /* mode_to_number() warned; set up a somewhat-sane mapping */
396 num = arm_mode_to_number(mode);
402 arm->map = &armv4_5_core_reg_map[num][0];
403 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
405 : arm->core_cache->reg_list + arm->map[16];
407 /* Older ARMs won't have the J bit */
408 enum arm_state state;
410 if (cpsr & (1 << 5)) { /* T */
411 if (cpsr & (1 << 24)) { /* J */
412 LOG_WARNING("ThumbEE -- incomplete support");
413 state = ARM_STATE_THUMB_EE;
415 state = ARM_STATE_THUMB;
417 if (cpsr & (1 << 24)) { /* J */
418 LOG_ERROR("Jazelle state handling is BROKEN!");
419 state = ARM_STATE_JAZELLE;
421 state = ARM_STATE_ARM;
423 arm->core_state = state;
425 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
427 arm_state_strings[arm->core_state]);
431 * Returns handle to the register currently mapped to a given number.
432 * Someone must have called arm_set_cpsr() before.
434 * \param arm This core's state and registers are used.
435 * \param regnum From 0..15 corresponding to R0..R14 and PC.
436 * Note that R0..R7 don't require mapping; you may access those
437 * as the first eight entries in the register cache. Likewise
438 * R15 (PC) doesn't need mapping; you may also access it directly.
439 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
440 * CPSR (arm->cpsr) is also not mapped.
442 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
450 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
451 r = arm->core_cache->reg_list + regnum;
453 r = arm->core_cache->reg_list + arm->map[regnum];
455 /* e.g. invalid CPSR said "secure monitor" mode on a core
456 * that doesn't support it...
459 LOG_ERROR("Invalid CPSR mode");
460 r = arm->core_cache->reg_list + regnum;
466 static const uint8_t arm_gdb_dummy_fp_value[12];
468 static struct reg_feature arm_gdb_dummy_fp_features = {
469 .name = "net.sourceforge.openocd.fake_fpa"
473 * Dummy FPA registers are required to support GDB on ARM.
474 * Register packets require eight obsolete FPA register values.
475 * Modern ARM cores use Vector Floating Point (VFP), if they
476 * have any floating point support. VFP is not FPA-compatible.
478 struct reg arm_gdb_dummy_fp_reg = {
479 .name = "GDB dummy FPA register",
480 .value = (uint8_t *) arm_gdb_dummy_fp_value,
485 .feature = &arm_gdb_dummy_fp_features,
489 static const uint8_t arm_gdb_dummy_fps_value[4];
492 * Dummy FPA status registers are required to support GDB on ARM.
493 * Register packets require an obsolete FPA status register.
495 struct reg arm_gdb_dummy_fps_reg = {
496 .name = "GDB dummy FPA status register",
497 .value = (uint8_t *) arm_gdb_dummy_fps_value,
502 .feature = &arm_gdb_dummy_fp_features,
506 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
508 static void arm_gdb_dummy_init(void)
510 register_init_dummy(&arm_gdb_dummy_fp_reg);
511 register_init_dummy(&arm_gdb_dummy_fps_reg);
514 static int armv4_5_get_core_reg(struct reg *reg)
517 struct arm_reg *reg_arch_info = reg->arch_info;
518 struct target *target = reg_arch_info->target;
520 if (target->state != TARGET_HALTED) {
521 LOG_ERROR("Target not halted");
522 return ERROR_TARGET_NOT_HALTED;
525 retval = reg_arch_info->arm->read_core_reg(target, reg,
526 reg_arch_info->num, reg_arch_info->mode);
527 if (retval == ERROR_OK) {
535 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
537 struct arm_reg *reg_arch_info = reg->arch_info;
538 struct target *target = reg_arch_info->target;
539 struct arm *armv4_5_target = target_to_arm(target);
540 uint32_t value = buf_get_u32(buf, 0, 32);
542 if (target->state != TARGET_HALTED) {
543 LOG_ERROR("Target not halted");
544 return ERROR_TARGET_NOT_HALTED;
547 /* Except for CPSR, the "reg" command exposes a writeback model
548 * for the register cache.
550 if (reg == armv4_5_target->cpsr) {
551 arm_set_cpsr(armv4_5_target, value);
553 /* Older cores need help to be in ARM mode during halt
554 * mode debug, so we clear the J and T bits if we flush.
555 * For newer cores (v6/v7a/v7r) we don't need that, but
556 * it won't hurt since CPSR is always flushed anyway.
558 if (armv4_5_target->core_mode !=
559 (enum arm_mode)(value & 0x1f)) {
560 LOG_DEBUG("changing ARM core mode to '%s'",
561 arm_mode_name(value & 0x1f));
562 value &= ~((1 << 24) | (1 << 5));
564 buf_set_u32(t, 0, 32, value);
565 armv4_5_target->write_core_reg(target, reg,
566 16, ARM_MODE_ANY, t);
569 buf_set_u32(reg->value, 0, 32, value);
577 static const struct reg_arch_type arm_reg_type = {
578 .get = armv4_5_get_core_reg,
579 .set = armv4_5_set_core_reg,
582 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
584 int num_regs = ARRAY_SIZE(arm_core_regs);
585 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
586 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
587 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
590 if (!cache || !reg_list || !reg_arch_info) {
597 cache->name = "ARM registers";
599 cache->reg_list = reg_list;
602 for (i = 0; i < num_regs; i++) {
603 /* Skip registers this core doesn't expose */
604 if (arm_core_regs[i].mode == ARM_MODE_MON
605 && arm->core_type != ARM_MODE_MON)
608 /* REVISIT handle Cortex-M, which only shadows R13/SP */
610 reg_arch_info[i].num = arm_core_regs[i].cookie;
611 reg_arch_info[i].mode = arm_core_regs[i].mode;
612 reg_arch_info[i].target = target;
613 reg_arch_info[i].arm = arm;
615 reg_list[i].name = arm_core_regs[i].name;
616 reg_list[i].number = arm_core_regs[i].gdb_index;
617 reg_list[i].size = 32;
618 reg_list[i].value = reg_arch_info[i].value;
619 reg_list[i].type = &arm_reg_type;
620 reg_list[i].arch_info = ®_arch_info[i];
621 reg_list[i].exist = true;
623 /* This really depends on the calling convention in use */
624 reg_list[i].caller_save = false;
626 /* Registers data type, as used by GDB target description */
627 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
628 switch (arm_core_regs[i].cookie) {
630 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
634 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
637 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
641 /* let GDB shows banked registers only in "info all-reg" */
642 reg_list[i].feature = malloc(sizeof(struct reg_feature));
643 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
644 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
645 reg_list[i].group = "general";
647 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
648 reg_list[i].group = "banked";
654 arm->pc = reg_list + 15;
655 arm->cpsr = reg_list + ARMV4_5_CPSR;
656 arm->core_cache = cache;
660 int arm_arch_state(struct target *target)
662 struct arm *arm = target_to_arm(target);
664 if (arm->common_magic != ARM_COMMON_MAGIC) {
665 LOG_ERROR("BUG: called for a non-ARM target");
669 /* avoid filling log waiting for fileio reply */
670 if (arm->semihosting_hit_fileio)
673 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
674 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
675 arm_state_strings[arm->core_state],
676 debug_reason_name(target),
677 arm_mode_name(arm->core_mode),
678 buf_get_u32(arm->cpsr->value, 0, 32),
679 buf_get_u32(arm->pc->value, 0, 32),
680 arm->is_semihosting ? ", semihosting" : "",
681 arm->is_semihosting_fileio ? " fileio" : "");
686 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
687 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
689 COMMAND_HANDLER(handle_armv4_5_reg_command)
691 struct target *target = get_current_target(CMD_CTX);
692 struct arm *arm = target_to_arm(target);
696 command_print(CMD_CTX, "current target isn't an ARM");
700 if (target->state != TARGET_HALTED) {
701 command_print(CMD_CTX, "error: target must be halted for register accesses");
705 if (arm->core_type != ARM_MODE_ANY) {
706 command_print(CMD_CTX,
707 "Microcontroller Profile not supported - use standard reg cmd");
711 if (!is_arm_mode(arm->core_mode)) {
712 LOG_ERROR("not a valid arm core mode - communication failure?");
716 if (!arm->full_context) {
717 command_print(CMD_CTX, "error: target doesn't support %s",
722 regs = arm->core_cache->reg_list;
724 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
729 /* label this bank of registers (or shadows) */
730 switch (arm_mode_data[mode].psr) {
734 name = "System and User";
738 if (arm->core_type != ARM_MODE_MON)
742 name = arm_mode_data[mode].name;
746 command_print(CMD_CTX, "%s%s mode %sregisters",
749 /* display N rows of up to 4 registers each */
750 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
754 for (unsigned j = 0; j < 4; j++, i++) {
756 struct reg *reg = regs;
758 if (i >= arm_mode_data[mode].n_indices)
761 reg += arm_mode_data[mode].indices[i];
763 /* REVISIT be smarter about faults... */
765 arm->full_context(target);
767 value = buf_get_u32(reg->value, 0, 32);
768 output_len += snprintf(output + output_len,
769 sizeof(output) - output_len,
770 "%8s: %8.8" PRIx32 " ",
773 command_print(CMD_CTX, "%s", output);
780 COMMAND_HANDLER(handle_armv4_5_core_state_command)
782 struct target *target = get_current_target(CMD_CTX);
783 struct arm *arm = target_to_arm(target);
786 command_print(CMD_CTX, "current target isn't an ARM");
790 if (arm->core_type == ARM_MODE_THREAD) {
791 /* armv7m not supported */
792 command_print(CMD_CTX, "Unsupported Command");
797 if (strcmp(CMD_ARGV[0], "arm") == 0)
798 arm->core_state = ARM_STATE_ARM;
799 if (strcmp(CMD_ARGV[0], "thumb") == 0)
800 arm->core_state = ARM_STATE_THUMB;
803 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
808 COMMAND_HANDLER(handle_arm_disassemble_command)
810 int retval = ERROR_OK;
811 struct target *target = get_current_target(CMD_CTX);
813 if (target == NULL) {
814 LOG_ERROR("No target selected");
818 struct arm *arm = target_to_arm(target);
819 target_addr_t address;
824 command_print(CMD_CTX, "current target isn't an ARM");
828 if (arm->core_type == ARM_MODE_THREAD) {
829 /* armv7m is always thumb mode */
835 if (strcmp(CMD_ARGV[2], "thumb") != 0)
840 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
843 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
844 if (address & 0x01) {
846 command_print(CMD_CTX, "Disassemble as Thumb");
855 retval = ERROR_COMMAND_SYNTAX_ERROR;
858 while (count-- > 0) {
859 struct arm_instruction cur_instruction;
862 /* Always use Thumb2 disassembly for best handling
863 * of 32-bit BL/BLX, and to work with newer cores
864 * (some ARMv6, all ARMv7) that use Thumb2.
866 retval = thumb2_opcode(target, address,
868 if (retval != ERROR_OK)
873 retval = target_read_u32(target, address, &opcode);
874 if (retval != ERROR_OK)
876 retval = arm_evaluate_opcode(opcode, address,
877 &cur_instruction) != ERROR_OK;
878 if (retval != ERROR_OK)
881 command_print(CMD_CTX, "%s", cur_instruction.text);
882 address += cur_instruction.instruction_size;
888 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
890 struct command_context *context;
891 struct target *target;
895 context = current_command_context(interp);
896 assert(context != NULL);
898 target = get_current_target(context);
899 if (target == NULL) {
900 LOG_ERROR("%s: no current target", __func__);
903 if (!target_was_examined(target)) {
904 LOG_ERROR("%s: not yet examined", target_name(target));
907 arm = target_to_arm(target);
909 LOG_ERROR("%s: not an ARM", target_name(target));
913 if ((argc < 6) || (argc > 7)) {
914 /* FIXME use the command name to verify # params... */
915 LOG_ERROR("%s: wrong number of arguments", __func__);
927 /* NOTE: parameter sequence matches ARM instruction set usage:
928 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
929 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
930 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
932 retval = Jim_GetLong(interp, argv[1], &l);
933 if (retval != JIM_OK)
936 LOG_ERROR("%s: %s %d out of range", __func__,
937 "coprocessor", (int) l);
942 retval = Jim_GetLong(interp, argv[2], &l);
943 if (retval != JIM_OK)
946 LOG_ERROR("%s: %s %d out of range", __func__,
952 retval = Jim_GetLong(interp, argv[3], &l);
953 if (retval != JIM_OK)
956 LOG_ERROR("%s: %s %d out of range", __func__,
962 retval = Jim_GetLong(interp, argv[4], &l);
963 if (retval != JIM_OK)
966 LOG_ERROR("%s: %s %d out of range", __func__,
972 retval = Jim_GetLong(interp, argv[5], &l);
973 if (retval != JIM_OK)
976 LOG_ERROR("%s: %s %d out of range", __func__,
984 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
985 * that could easily be a typo! Check both...
987 * FIXME change the call syntax here ... simplest to just pass
988 * the MRC() or MCR() instruction to be executed. That will also
989 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
990 * if that's ever needed.
993 retval = Jim_GetLong(interp, argv[6], &l);
994 if (retval != JIM_OK)
998 /* NOTE: parameters reordered! */
999 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
1000 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
1001 if (retval != ERROR_OK)
1004 /* NOTE: parameters reordered! */
1005 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1006 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1007 if (retval != ERROR_OK)
1010 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1016 COMMAND_HANDLER(handle_arm_semihosting_command)
1018 struct target *target = get_current_target(CMD_CTX);
1020 if (target == NULL) {
1021 LOG_ERROR("No target selected");
1025 struct arm *arm = target_to_arm(target);
1028 command_print(CMD_CTX, "current target isn't an ARM");
1032 if (!arm->setup_semihosting) {
1033 command_print(CMD_CTX, "semihosting not supported for current target");
1040 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1042 if (!target_was_examined(target)) {
1043 LOG_ERROR("Target not examined yet");
1047 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1048 LOG_ERROR("Failed to Configure semihosting");
1052 /* FIXME never let that "catch" be dropped! */
1053 arm->is_semihosting = semihosting;
1056 command_print(CMD_CTX, "semihosting is %s",
1058 ? "enabled" : "disabled");
1063 COMMAND_HANDLER(handle_arm_semihosting_fileio_command)
1065 struct target *target = get_current_target(CMD_CTX);
1067 if (target == NULL) {
1068 LOG_ERROR("No target selected");
1072 struct arm *arm = target_to_arm(target);
1075 command_print(CMD_CTX, "current target isn't an ARM");
1079 if (!arm->is_semihosting) {
1080 command_print(CMD_CTX, "semihosting is not enabled");
1085 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm->is_semihosting_fileio);
1087 command_print(CMD_CTX, "semihosting fileio is %s",
1088 arm->is_semihosting_fileio
1089 ? "enabled" : "disabled");
1094 static const struct command_registration arm_exec_command_handlers[] = {
1097 .handler = handle_armv4_5_reg_command,
1098 .mode = COMMAND_EXEC,
1099 .help = "display ARM core registers",
1103 .name = "core_state",
1104 .handler = handle_armv4_5_core_state_command,
1105 .mode = COMMAND_EXEC,
1106 .usage = "['arm'|'thumb']",
1107 .help = "display/change ARM core state",
1110 .name = "disassemble",
1111 .handler = handle_arm_disassemble_command,
1112 .mode = COMMAND_EXEC,
1113 .usage = "address [count ['thumb']]",
1114 .help = "disassemble instructions ",
1118 .mode = COMMAND_EXEC,
1119 .jim_handler = &jim_mcrmrc,
1120 .help = "write coprocessor register",
1121 .usage = "cpnum op1 CRn CRm op2 value",
1125 .jim_handler = &jim_mcrmrc,
1126 .help = "read coprocessor register",
1127 .usage = "cpnum op1 CRn CRm op2",
1131 .handler = handle_arm_semihosting_command,
1132 .mode = COMMAND_EXEC,
1133 .usage = "['enable'|'disable']",
1134 .help = "activate support for semihosting operations",
1137 "semihosting_fileio",
1138 .handler = handle_arm_semihosting_fileio_command,
1139 .mode = COMMAND_EXEC,
1140 .usage = "['enable'|'disable']",
1141 .help = "activate support for semihosting fileio operations",
1144 COMMAND_REGISTRATION_DONE
1146 const struct command_registration arm_command_handlers[] = {
1149 .mode = COMMAND_ANY,
1150 .help = "ARM command group",
1152 .chain = arm_exec_command_handlers,
1154 COMMAND_REGISTRATION_DONE
1157 int arm_get_gdb_reg_list(struct target *target,
1158 struct reg **reg_list[], int *reg_list_size,
1159 enum target_register_class reg_class)
1161 struct arm *arm = target_to_arm(target);
1164 if (!is_arm_mode(arm->core_mode)) {
1165 LOG_ERROR("not a valid arm core mode - communication failure?");
1169 switch (reg_class) {
1170 case REG_CLASS_GENERAL:
1171 *reg_list_size = 26;
1172 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1174 for (i = 0; i < 16; i++)
1175 (*reg_list)[i] = arm_reg_current(arm, i);
1177 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1178 for (i = 16; i < 24; i++)
1179 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1180 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1182 (*reg_list)[25] = arm->cpsr;
1188 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1189 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1191 for (i = 0; i < 16; i++)
1192 (*reg_list)[i] = arm_reg_current(arm, i);
1194 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1195 int reg_index = arm->core_cache->reg_list[i].number;
1196 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1197 && arm->core_type != ARM_MODE_MON))
1198 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1201 /* When we supply the target description, there is no need for fake FPA */
1202 for (i = 16; i < 24; i++) {
1203 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1204 (*reg_list)[i]->size = 0;
1206 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1207 (*reg_list)[24]->size = 0;
1213 LOG_ERROR("not a valid register class type in query.");
1219 /* wait for execution to complete and check exit point */
1220 static int armv4_5_run_algorithm_completion(struct target *target,
1221 uint32_t exit_point,
1226 struct arm *arm = target_to_arm(target);
1228 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1229 if (retval != ERROR_OK)
1231 if (target->state != TARGET_HALTED) {
1232 retval = target_halt(target);
1233 if (retval != ERROR_OK)
1235 retval = target_wait_state(target, TARGET_HALTED, 500);
1236 if (retval != ERROR_OK)
1238 return ERROR_TARGET_TIMEOUT;
1241 /* fast exit: ARMv5+ code can use BKPT */
1242 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1244 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1245 buf_get_u32(arm->pc->value, 0, 32));
1246 return ERROR_TARGET_TIMEOUT;
1252 int armv4_5_run_algorithm_inner(struct target *target,
1253 int num_mem_params, struct mem_param *mem_params,
1254 int num_reg_params, struct reg_param *reg_params,
1255 uint32_t entry_point, uint32_t exit_point,
1256 int timeout_ms, void *arch_info,
1257 int (*run_it)(struct target *target, uint32_t exit_point,
1258 int timeout_ms, void *arch_info))
1260 struct arm *arm = target_to_arm(target);
1261 struct arm_algorithm *arm_algorithm_info = arch_info;
1262 enum arm_state core_state = arm->core_state;
1263 uint32_t context[17];
1265 int exit_breakpoint_size = 0;
1267 int retval = ERROR_OK;
1269 LOG_DEBUG("Running algorithm");
1271 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1272 LOG_ERROR("current target isn't an ARMV4/5 target");
1273 return ERROR_TARGET_INVALID;
1276 if (target->state != TARGET_HALTED) {
1277 LOG_WARNING("target not halted");
1278 return ERROR_TARGET_NOT_HALTED;
1281 if (!is_arm_mode(arm->core_mode)) {
1282 LOG_ERROR("not a valid arm core mode - communication failure?");
1286 /* armv5 and later can terminate with BKPT instruction; less overhead */
1287 if (!exit_point && arm->is_armv4) {
1288 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1292 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1293 * they'll be restored later.
1295 for (i = 0; i <= 16; i++) {
1298 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1299 arm_algorithm_info->core_mode, i);
1301 arm->read_core_reg(target, r, i,
1302 arm_algorithm_info->core_mode);
1303 context[i] = buf_get_u32(r->value, 0, 32);
1305 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1307 for (i = 0; i < num_mem_params; i++) {
1308 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1309 mem_params[i].value);
1310 if (retval != ERROR_OK)
1314 for (i = 0; i < num_reg_params; i++) {
1315 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1317 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1318 return ERROR_COMMAND_SYNTAX_ERROR;
1321 if (reg->size != reg_params[i].size) {
1322 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1323 reg_params[i].reg_name);
1324 return ERROR_COMMAND_SYNTAX_ERROR;
1327 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1328 if (retval != ERROR_OK)
1332 arm->core_state = arm_algorithm_info->core_state;
1333 if (arm->core_state == ARM_STATE_ARM)
1334 exit_breakpoint_size = 4;
1335 else if (arm->core_state == ARM_STATE_THUMB)
1336 exit_breakpoint_size = 2;
1338 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1339 return ERROR_COMMAND_SYNTAX_ERROR;
1342 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1343 LOG_DEBUG("setting core_mode: 0x%2.2x",
1344 arm_algorithm_info->core_mode);
1345 buf_set_u32(arm->cpsr->value, 0, 5,
1346 arm_algorithm_info->core_mode);
1347 arm->cpsr->dirty = 1;
1348 arm->cpsr->valid = 1;
1351 /* terminate using a hardware or (ARMv5+) software breakpoint */
1353 retval = breakpoint_add(target, exit_point,
1354 exit_breakpoint_size, BKPT_HARD);
1355 if (retval != ERROR_OK) {
1356 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1357 return ERROR_TARGET_FAILURE;
1361 retval = target_resume(target, 0, entry_point, 1, 1);
1362 if (retval != ERROR_OK)
1364 retval = run_it(target, exit_point, timeout_ms, arch_info);
1367 breakpoint_remove(target, exit_point);
1369 if (retval != ERROR_OK)
1372 for (i = 0; i < num_mem_params; i++) {
1373 if (mem_params[i].direction != PARAM_OUT) {
1374 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1376 mem_params[i].value);
1377 if (retvaltemp != ERROR_OK)
1378 retval = retvaltemp;
1382 for (i = 0; i < num_reg_params; i++) {
1383 if (reg_params[i].direction != PARAM_OUT) {
1385 struct reg *reg = register_get_by_name(arm->core_cache,
1386 reg_params[i].reg_name,
1389 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1390 retval = ERROR_COMMAND_SYNTAX_ERROR;
1394 if (reg->size != reg_params[i].size) {
1396 "BUG: register '%s' size doesn't match reg_params[i].size",
1397 reg_params[i].reg_name);
1398 retval = ERROR_COMMAND_SYNTAX_ERROR;
1402 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1406 /* restore everything we saved before (17 or 18 registers) */
1407 for (i = 0; i <= 16; i++) {
1409 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1410 arm_algorithm_info->core_mode, i).value, 0, 32);
1411 if (regvalue != context[i]) {
1412 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1413 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1414 arm_algorithm_info->core_mode, i).name, context[i]);
1415 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1416 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1417 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1419 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1424 arm_set_cpsr(arm, cpsr);
1425 arm->cpsr->dirty = 1;
1427 arm->core_state = core_state;
1432 int armv4_5_run_algorithm(struct target *target,
1434 struct mem_param *mem_params,
1436 struct reg_param *reg_params,
1437 target_addr_t entry_point,
1438 target_addr_t exit_point,
1442 return armv4_5_run_algorithm_inner(target,
1447 (uint32_t)entry_point,
1448 (uint32_t)exit_point,
1451 armv4_5_run_algorithm_completion);
1455 * Runs ARM code in the target to calculate a CRC32 checksum.
1458 int arm_checksum_memory(struct target *target,
1459 target_addr_t address, uint32_t count, uint32_t *checksum)
1461 struct working_area *crc_algorithm;
1462 struct arm_algorithm arm_algo;
1463 struct arm *arm = target_to_arm(target);
1464 struct reg_param reg_params[2];
1467 uint32_t exit_var = 0;
1469 static const uint8_t arm_crc_code_le[] = {
1470 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1473 assert(sizeof(arm_crc_code_le) % 4 == 0);
1475 retval = target_alloc_working_area(target,
1476 sizeof(arm_crc_code_le), &crc_algorithm);
1477 if (retval != ERROR_OK)
1480 /* convert code into a buffer in target endianness */
1481 for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1482 retval = target_write_u32(target,
1483 crc_algorithm->address + i * sizeof(uint32_t),
1484 le_to_h_u32(&arm_crc_code_le[i * 4]));
1485 if (retval != ERROR_OK)
1489 arm_algo.common_magic = ARM_COMMON_MAGIC;
1490 arm_algo.core_mode = ARM_MODE_SVC;
1491 arm_algo.core_state = ARM_STATE_ARM;
1493 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
1494 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1496 buf_set_u32(reg_params[0].value, 0, 32, address);
1497 buf_set_u32(reg_params[1].value, 0, 32, count);
1499 /* 20 second timeout/megabyte */
1500 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1502 /* armv4 must exit using a hardware breakpoint */
1504 exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1506 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1507 crc_algorithm->address,
1509 timeout, &arm_algo);
1511 if (retval == ERROR_OK)
1512 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1514 LOG_ERROR("error executing ARM crc algorithm");
1516 destroy_reg_param(®_params[0]);
1517 destroy_reg_param(®_params[1]);
1520 target_free_working_area(target, crc_algorithm);
1526 * Runs ARM code in the target to check whether a memory block holds
1527 * all ones. NOR flash which has been erased, and thus may be written,
1531 int arm_blank_check_memory(struct target *target,
1532 target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
1534 struct working_area *check_algorithm;
1535 struct reg_param reg_params[3];
1536 struct arm_algorithm arm_algo;
1537 struct arm *arm = target_to_arm(target);
1540 uint32_t exit_var = 0;
1542 static const uint8_t check_code_le[] = {
1543 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1546 assert(sizeof(check_code_le) % 4 == 0);
1548 if (erased_value != 0xff) {
1549 LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1554 /* make sure we have a working area */
1555 retval = target_alloc_working_area(target,
1556 sizeof(check_code_le), &check_algorithm);
1557 if (retval != ERROR_OK)
1560 /* convert code into a buffer in target endianness */
1561 for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1562 retval = target_write_u32(target,
1563 check_algorithm->address
1564 + i * sizeof(uint32_t),
1565 le_to_h_u32(&check_code_le[i * 4]));
1566 if (retval != ERROR_OK)
1570 arm_algo.common_magic = ARM_COMMON_MAGIC;
1571 arm_algo.core_mode = ARM_MODE_SVC;
1572 arm_algo.core_state = ARM_STATE_ARM;
1574 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1575 buf_set_u32(reg_params[0].value, 0, 32, address);
1577 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1578 buf_set_u32(reg_params[1].value, 0, 32, count);
1580 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
1581 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1583 /* armv4 must exit using a hardware breakpoint */
1585 exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1587 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1588 check_algorithm->address,
1592 if (retval == ERROR_OK)
1593 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1595 destroy_reg_param(®_params[0]);
1596 destroy_reg_param(®_params[1]);
1597 destroy_reg_param(®_params[2]);
1600 target_free_working_area(target, check_algorithm);
1605 static int arm_full_context(struct target *target)
1607 struct arm *arm = target_to_arm(target);
1608 unsigned num_regs = arm->core_cache->num_regs;
1609 struct reg *reg = arm->core_cache->reg_list;
1610 int retval = ERROR_OK;
1612 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1615 retval = armv4_5_get_core_reg(reg);
1620 static int arm_default_mrc(struct target *target, int cpnum,
1621 uint32_t op1, uint32_t op2,
1622 uint32_t CRn, uint32_t CRm,
1625 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1629 static int arm_default_mcr(struct target *target, int cpnum,
1630 uint32_t op1, uint32_t op2,
1631 uint32_t CRn, uint32_t CRm,
1634 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1638 int arm_init_arch_info(struct target *target, struct arm *arm)
1640 target->arch_info = arm;
1641 arm->target = target;
1643 arm->common_magic = ARM_COMMON_MAGIC;
1645 /* core_type may be overridden by subtype logic */
1646 if (arm->core_type != ARM_MODE_THREAD) {
1647 arm->core_type = ARM_MODE_ANY;
1648 arm_set_cpsr(arm, ARM_MODE_USR);
1651 /* default full_context() has no core-specific optimizations */
1652 if (!arm->full_context && arm->read_core_reg)
1653 arm->full_context = arm_full_context;
1656 arm->mrc = arm_default_mrc;
1658 arm->mcr = arm_default_mcr;