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1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "arm_disassembler.h"
27
28 #include "armv4_5.h"
29
30 #include "target.h"
31 #include "register.h"
32 #include "log.h"
33 #include "binarybuffer.h"
34 #include "command.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 bitfield_desc_t armv4_5_psr_bitfield_desc[] = 
41 {
42         {"M[4:0]", 5},
43         {"T", 1},
44         {"F", 1},
45         {"I", 1},
46         {"reserved", 16},
47         {"J", 1},
48         {"reserved", 2},
49         {"Q", 1},
50         {"V", 1},
51         {"C", 1},
52         {"Z", 1},
53         {"N", 1},
54 };
55
56 char* armv4_5_core_reg_list[] =
57 {
58         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
59         
60         "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
61         
62         "r13_irq", "lr_irq",
63         
64         "r13_svc", "lr_svc",
65         
66         "r13_abt", "lr_abt",
67         
68         "r13_und", "lr_und",
69         
70         "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
71 };
72
73 char* armv4_5_mode_strings[] =
74 {
75         "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
76 };
77
78 char* armv4_5_state_strings[] =
79 {
80         "ARM", "Thumb", "Jazelle"
81 };
82
83 int armv4_5_core_reg_arch_type = -1;
84
85 armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] = 
86 {
87         {0, ARMV4_5_MODE_ANY, NULL, NULL},
88         {1, ARMV4_5_MODE_ANY, NULL, NULL},
89         {2, ARMV4_5_MODE_ANY, NULL, NULL},
90         {3, ARMV4_5_MODE_ANY, NULL, NULL},
91         {4, ARMV4_5_MODE_ANY, NULL, NULL},
92         {5, ARMV4_5_MODE_ANY, NULL, NULL},
93         {6, ARMV4_5_MODE_ANY, NULL, NULL},
94         {7, ARMV4_5_MODE_ANY, NULL, NULL},
95         {8, ARMV4_5_MODE_ANY, NULL, NULL},
96         {9, ARMV4_5_MODE_ANY, NULL, NULL},
97         {10, ARMV4_5_MODE_ANY, NULL, NULL},
98         {11, ARMV4_5_MODE_ANY, NULL, NULL},
99         {12, ARMV4_5_MODE_ANY, NULL, NULL},
100         {13, ARMV4_5_MODE_USR, NULL, NULL},
101         {14, ARMV4_5_MODE_USR, NULL, NULL},
102         {15, ARMV4_5_MODE_ANY, NULL, NULL},
103         
104         {8, ARMV4_5_MODE_FIQ, NULL, NULL},
105         {9, ARMV4_5_MODE_FIQ, NULL, NULL},
106         {10, ARMV4_5_MODE_FIQ, NULL, NULL},
107         {11, ARMV4_5_MODE_FIQ, NULL, NULL},
108         {12, ARMV4_5_MODE_FIQ, NULL, NULL},
109         {13, ARMV4_5_MODE_FIQ, NULL, NULL},
110         {14, ARMV4_5_MODE_FIQ, NULL, NULL},
111         
112         {13, ARMV4_5_MODE_IRQ, NULL, NULL},
113         {14, ARMV4_5_MODE_IRQ, NULL, NULL},
114
115         {13, ARMV4_5_MODE_SVC, NULL, NULL},
116         {14, ARMV4_5_MODE_SVC, NULL, NULL},
117
118         {13, ARMV4_5_MODE_ABT, NULL, NULL},
119         {14, ARMV4_5_MODE_ABT, NULL, NULL},
120         
121         {13, ARMV4_5_MODE_UND, NULL, NULL},
122         {14, ARMV4_5_MODE_UND, NULL, NULL},
123         
124         {16, ARMV4_5_MODE_ANY, NULL, NULL},
125         {16, ARMV4_5_MODE_FIQ, NULL, NULL},
126         {16, ARMV4_5_MODE_IRQ, NULL, NULL},
127         {16, ARMV4_5_MODE_SVC, NULL, NULL},
128         {16, ARMV4_5_MODE_ABT, NULL, NULL},
129         {16, ARMV4_5_MODE_UND, NULL, NULL}
130 };
131
132 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
133 int armv4_5_core_reg_map[7][17] =
134 {
135         {       /* USR */
136                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
137         },
138         {       /* FIQ */
139                 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
140         },
141         {       /* IRQ */
142                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
143         },
144         {       /* SVC */
145                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
146         },
147         {       /* ABT */
148                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
149         },
150         {       /* UND */
151                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
152         },
153         {       /* SYS */
154                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
155         }
156 };
157
158 u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
159
160 reg_t armv4_5_gdb_dummy_fp_reg =
161 {
162         "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
163 };
164
165 u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
166
167 reg_t armv4_5_gdb_dummy_fps_reg =
168 {
169         "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
170 };
171
172 /* map psr mode bits to linear number */
173 int armv4_5_mode_to_number(enum armv4_5_mode mode)
174 {
175         switch (mode)
176         {
177                 case 16: return 0; break;
178                 case 17: return 1; break;
179                 case 18: return 2; break;
180                 case 19: return 3; break;
181                 case 23: return 4; break;
182                 case 27: return 5; break;
183                 case 31: return 6; break;
184                 case -1: return 0; break;       /* map MODE_ANY to user mode */
185                 default: 
186                         ERROR("invalid mode value encountered");
187                         return -1;
188         }
189 }
190
191 /* map linear number to mode bits */
192 enum armv4_5_mode armv4_5_number_to_mode(int number)
193 {
194         switch(number)
195         {
196                 case 0: return ARMV4_5_MODE_USR; break;
197                 case 1: return ARMV4_5_MODE_FIQ; break;
198                 case 2: return ARMV4_5_MODE_IRQ; break;
199                 case 3: return ARMV4_5_MODE_SVC; break;
200                 case 4: return ARMV4_5_MODE_ABT; break;
201                 case 5: return ARMV4_5_MODE_UND; break;
202                 case 6: return ARMV4_5_MODE_SYS; break;
203                 default: 
204                         ERROR("mode index out of bounds");
205                         return -1;
206         }
207 };
208
209 int armv4_5_get_core_reg(reg_t *reg)
210 {
211         int retval;
212         armv4_5_core_reg_t *armv4_5 = reg->arch_info;
213         target_t *target = armv4_5->target;
214         
215         if (target->state != TARGET_HALTED)
216         {
217                 return ERROR_TARGET_NOT_HALTED;
218         }
219         
220         //retval = armv4_5->armv4_5_common->full_context(target);
221         retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
222         
223         return retval;
224 }
225
226 int armv4_5_set_core_reg(reg_t *reg, u32 value)
227 {
228         armv4_5_core_reg_t *armv4_5 = reg->arch_info;
229         target_t *target = armv4_5->target;
230                 
231         if (target->state != TARGET_HALTED)
232         {
233                 return ERROR_TARGET_NOT_HALTED;
234         }
235         
236         buf_set_u32(reg->value, 0, 32, value);
237         reg->dirty = 1;
238         reg->valid = 1;
239
240         return ERROR_OK;
241 }
242
243 int armv4_5_invalidate_core_regs(target_t *target)
244 {
245         armv4_5_common_t *armv4_5 = target->arch_info;
246         int i;
247         
248         for (i = 0; i < 37; i++)
249         {
250                 armv4_5->core_cache->reg_list[i].valid = 0;
251                 armv4_5->core_cache->reg_list[i].dirty = 0;
252         }
253         
254         return ERROR_OK;
255 }
256
257 reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
258 {
259         int num_regs = 37;
260         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
261         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
262         armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs);
263         int i;
264         
265         cache->name = "arm v4/5 registers";
266         cache->next = NULL;
267         cache->reg_list = reg_list;
268         cache->num_regs = num_regs;
269         
270         if (armv4_5_core_reg_arch_type == -1)
271                 armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
272                 
273         for (i = 0; i < 37; i++)
274         {
275                 arch_info[i] = armv4_5_core_reg_list_arch_info[i];
276                 arch_info[i].target = target;
277                 arch_info[i].armv4_5_common = armv4_5_common;
278                 reg_list[i].name = armv4_5_core_reg_list[i];
279                 reg_list[i].size = 32;
280                 reg_list[i].value = calloc(1, 4);
281                 reg_list[i].dirty = 0;
282                 reg_list[i].valid = 0;
283                 reg_list[i].bitfield_desc = NULL;
284                 reg_list[i].num_bitfields = 0;
285                 reg_list[i].arch_type = armv4_5_core_reg_arch_type;
286                 reg_list[i].arch_info = &arch_info[i];
287         }
288         
289         return cache;
290 }
291
292 int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size)
293 {
294         armv4_5_common_t *armv4_5 = target->arch_info;
295         
296         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
297         {
298                 ERROR("BUG: called for a non-ARMv4/5 target");
299                 exit(-1);
300         }
301         
302         snprintf(buf, buf_size,
303                          "target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
304                          armv4_5_state_strings[armv4_5->core_state],
305                          target_debug_reason_strings[target->debug_reason],
306                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
307                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
308                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
309         
310         return ERROR_OK;
311 }
312
313 int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
314 {
315         char output[128];
316         int output_len;
317         int mode, num;
318         target_t *target = get_current_target(cmd_ctx);
319         armv4_5_common_t *armv4_5 = target->arch_info;
320                 
321         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
322         {
323                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
324                 return ERROR_OK;
325         }
326         
327         if (target->state != TARGET_HALTED)
328         {
329                 command_print(cmd_ctx, "error: target must be halted for register accesses");
330                 return ERROR_OK;
331         }
332         
333         for (num = 0; num <= 15; num++)
334         {
335                 output_len = 0;
336                 for (mode = 0; mode < 6; mode++)
337                 {
338                         if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
339                         {
340                                 armv4_5->full_context(target);
341                         }
342                         output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name, 
343                                 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
344                 }
345                 command_print(cmd_ctx, output);
346         }
347         command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
348                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
349                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
350                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
351                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
352                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
353                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
354         
355         return ERROR_OK;
356 }
357
358 int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
359 {
360         target_t *target = get_current_target(cmd_ctx);
361         armv4_5_common_t *armv4_5 = target->arch_info;
362                 
363         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
364         {
365                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
366                 return ERROR_OK;
367         }
368         
369         if (argc > 0)
370         {
371                 if (strcmp(args[0], "arm") == 0)
372                 {
373                         armv4_5->core_state = ARMV4_5_STATE_ARM;
374                 }
375                 if (strcmp(args[0], "thumb") == 0)
376                 {
377                         armv4_5->core_state = ARMV4_5_STATE_THUMB;
378                 }
379         }
380         
381         command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
382         
383         return ERROR_OK;
384 }
385
386 int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
387 {
388         target_t *target = get_current_target(cmd_ctx);
389         armv4_5_common_t *armv4_5 = target->arch_info;
390         u32 address;
391         int count;
392         int i;
393         arm_instruction_t cur_instruction;
394         u32 opcode;
395         int thumb = 0;
396         
397         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
398         {
399                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
400                 return ERROR_OK;
401         }
402         
403         if (argc < 2)
404         {
405                 command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
406                 return ERROR_OK;
407         }
408         
409         address = strtoul(args[0], NULL, 0);
410         count = strtoul(args[1], NULL, 0);
411         
412         if (argc >= 3)
413                 if (strcmp(args[2], "thumb") == 0)
414                         thumb = 1;
415         
416         for (i = 0; i < count; i++)
417         {
418                 target_read_u32(target, address, &opcode);
419                 evaluate_opcode(opcode, address, &cur_instruction);
420                 command_print(cmd_ctx, "%s", cur_instruction.text);
421                 address += (thumb) ? 2 : 4;
422         }
423         
424         return ERROR_OK;
425 }
426
427 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
428 {
429         command_t *armv4_5_cmd;
430
431         armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
432         
433         register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
434         register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
435         
436         register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
437         return ERROR_OK;
438 }
439
440 int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
441 {
442         armv4_5_common_t *armv4_5 = target->arch_info;
443         int i;
444         
445         if (target->state != TARGET_HALTED)
446         {
447                 return ERROR_TARGET_NOT_HALTED;
448         }
449         
450         *reg_list_size = 26;
451         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
452         
453         for (i = 0; i < 16; i++)
454         {
455                 (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
456         }
457         
458         for (i = 16; i < 24; i++)
459         {
460                 (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
461         }
462         
463         (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
464         (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
465         
466         return ERROR_OK;
467 }
468
469 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
470 {
471         armv4_5_common_t *armv4_5 = target->arch_info;
472         armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
473         enum armv4_5_state core_state = armv4_5->core_state;
474         enum armv4_5_mode core_mode = armv4_5->core_mode;
475         u32 context[17];
476         u32 cpsr;
477         int exit_breakpoint_size = 0;
478         int i;
479         int retval = ERROR_OK;
480         
481         if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
482         {
483                 ERROR("current target isn't an ARMV4/5 target");
484                 return ERROR_TARGET_INVALID;
485         }
486         
487         if (target->state != TARGET_HALTED)
488         {
489                 WARNING("target not halted");
490                 return ERROR_TARGET_NOT_HALTED;
491         }
492         
493         for (i = 0; i <= 16; i++)
494         {
495                 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
496                         armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
497                 context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
498         }
499         cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
500         
501         for (i = 0; i < num_mem_params; i++)
502         {
503                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
504         }
505         
506         for (i = 0; i < num_reg_params; i++)
507         {
508                 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
509                 if (!reg)
510                 {
511                         ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
512                         exit(-1);
513                 }
514                 
515                 if (reg->size != reg_params[i].size)
516                 {
517                         ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
518                         exit(-1);
519                 }
520                 
521                 armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32));
522         }
523         
524         armv4_5->core_state = armv4_5_algorithm_info->core_state;
525         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
526                 exit_breakpoint_size = 4;
527         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
528                 exit_breakpoint_size = 2;
529         else
530         {
531                 ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
532                 exit(-1);
533         }
534         
535         if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
536         {
537                 DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
538                 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
539                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
540                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
541         }
542
543         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
544         {
545                 ERROR("can't add breakpoint to finish algorithm execution");
546                 return ERROR_TARGET_FAILURE;
547         }
548         
549         target->type->resume(target, 0, entry_point, 1, 1);
550         target->type->poll(target);
551         
552         while (target->state != TARGET_HALTED)
553         {
554                 usleep(10000);
555                 target->type->poll(target);
556                 if ((timeout_ms -= 10) <= 0)
557                 {
558                         ERROR("timeout waiting for algorithm to complete, trying to halt target");
559                         target->type->halt(target);
560                         timeout_ms = 1000;
561                         while (target->state != TARGET_HALTED)
562                         {
563                                 usleep(10000);
564                                 target->type->poll(target);
565                                 if ((timeout_ms -= 10) <= 0)
566                                 {
567                                         ERROR("target didn't reenter debug state, exiting");
568                                         exit(-1);
569                                 }
570                         }
571                         retval = ERROR_TARGET_TIMEOUT;
572                 }
573         }
574         
575         breakpoint_remove(target, exit_point);
576         
577         for (i = 0; i < num_mem_params; i++)
578         {
579                 if (mem_params[i].direction != PARAM_OUT)
580                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
581         }
582         
583         for (i = 0; i < num_reg_params; i++)
584         {
585                 if (reg_params[i].direction != PARAM_OUT)
586                 {
587                                 
588                         reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
589                         if (!reg)
590                         {
591                                 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
592                                 exit(-1);
593                         }
594                         
595                         if (reg->size != reg_params[i].size)
596                         {
597                                 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
598                                 exit(-1);
599                         }
600                         
601                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
602                 }
603         }
604         
605         for (i = 0; i <= 16; i++)
606         {
607                 DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32));
608                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
609                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
610                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
611         }
612         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
613         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
614         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
615         
616         armv4_5->core_state = core_state;
617         armv4_5->core_mode = core_mode;
618
619         return retval;
620 }
621
622 int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
623 {       
624         target->arch_info = armv4_5;
625
626         armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
627         armv4_5->core_state = ARMV4_5_STATE_ARM;
628         armv4_5->core_mode = ARMV4_5_MODE_USR;
629         
630         return ERROR_OK;
631 }