1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "arm_disassembler.h"
32 #include "binarybuffer.h"
35 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
51 char* armv4_5_core_reg_list[] =
53 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
55 "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
65 "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
68 char * armv4_5_mode_strings_list[] =
70 "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
73 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
74 char** armv4_5_mode_strings = armv4_5_mode_strings_list + 1;
76 char* armv4_5_state_strings[] =
78 "ARM", "Thumb", "Jazelle"
81 int armv4_5_core_reg_arch_type = -1;
83 armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
85 {0, ARMV4_5_MODE_ANY, NULL, NULL},
86 {1, ARMV4_5_MODE_ANY, NULL, NULL},
87 {2, ARMV4_5_MODE_ANY, NULL, NULL},
88 {3, ARMV4_5_MODE_ANY, NULL, NULL},
89 {4, ARMV4_5_MODE_ANY, NULL, NULL},
90 {5, ARMV4_5_MODE_ANY, NULL, NULL},
91 {6, ARMV4_5_MODE_ANY, NULL, NULL},
92 {7, ARMV4_5_MODE_ANY, NULL, NULL},
93 {8, ARMV4_5_MODE_ANY, NULL, NULL},
94 {9, ARMV4_5_MODE_ANY, NULL, NULL},
95 {10, ARMV4_5_MODE_ANY, NULL, NULL},
96 {11, ARMV4_5_MODE_ANY, NULL, NULL},
97 {12, ARMV4_5_MODE_ANY, NULL, NULL},
98 {13, ARMV4_5_MODE_USR, NULL, NULL},
99 {14, ARMV4_5_MODE_USR, NULL, NULL},
100 {15, ARMV4_5_MODE_ANY, NULL, NULL},
102 {8, ARMV4_5_MODE_FIQ, NULL, NULL},
103 {9, ARMV4_5_MODE_FIQ, NULL, NULL},
104 {10, ARMV4_5_MODE_FIQ, NULL, NULL},
105 {11, ARMV4_5_MODE_FIQ, NULL, NULL},
106 {12, ARMV4_5_MODE_FIQ, NULL, NULL},
107 {13, ARMV4_5_MODE_FIQ, NULL, NULL},
108 {14, ARMV4_5_MODE_FIQ, NULL, NULL},
110 {13, ARMV4_5_MODE_IRQ, NULL, NULL},
111 {14, ARMV4_5_MODE_IRQ, NULL, NULL},
113 {13, ARMV4_5_MODE_SVC, NULL, NULL},
114 {14, ARMV4_5_MODE_SVC, NULL, NULL},
116 {13, ARMV4_5_MODE_ABT, NULL, NULL},
117 {14, ARMV4_5_MODE_ABT, NULL, NULL},
119 {13, ARMV4_5_MODE_UND, NULL, NULL},
120 {14, ARMV4_5_MODE_UND, NULL, NULL},
122 {16, ARMV4_5_MODE_ANY, NULL, NULL},
123 {16, ARMV4_5_MODE_FIQ, NULL, NULL},
124 {16, ARMV4_5_MODE_IRQ, NULL, NULL},
125 {16, ARMV4_5_MODE_SVC, NULL, NULL},
126 {16, ARMV4_5_MODE_ABT, NULL, NULL},
127 {16, ARMV4_5_MODE_UND, NULL, NULL}
130 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
131 int armv4_5_core_reg_map[7][17] =
134 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
137 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
140 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
143 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
146 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
149 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
152 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
156 uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
158 reg_t armv4_5_gdb_dummy_fp_reg =
160 "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
163 uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
165 reg_t armv4_5_gdb_dummy_fps_reg =
167 "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
170 int armv4_5_get_core_reg(reg_t *reg)
173 armv4_5_core_reg_t *armv4_5 = reg->arch_info;
174 target_t *target = armv4_5->target;
176 if (target->state != TARGET_HALTED)
178 LOG_ERROR("Target not halted");
179 return ERROR_TARGET_NOT_HALTED;
182 /* retval = armv4_5->armv4_5_common->full_context(target); */
183 retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
188 int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
190 armv4_5_core_reg_t *armv4_5 = reg->arch_info;
191 target_t *target = armv4_5->target;
192 armv4_5_common_t *armv4_5_target = target->arch_info;
193 uint32_t value = buf_get_u32(buf, 0, 32);
195 if (target->state != TARGET_HALTED)
197 return ERROR_TARGET_NOT_HALTED;
200 if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
204 /* T bit should be set */
205 if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
207 /* change state to Thumb */
208 LOG_DEBUG("changing to Thumb state");
209 armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
214 /* T bit should be cleared */
215 if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
217 /* change state to ARM */
218 LOG_DEBUG("changing to ARM state");
219 armv4_5_target->core_state = ARMV4_5_STATE_ARM;
223 if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
225 LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
226 armv4_5_target->core_mode = value & 0x1f;
227 armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
231 buf_set_u32(reg->value, 0, 32, value);
238 int armv4_5_invalidate_core_regs(target_t *target)
240 armv4_5_common_t *armv4_5 = target->arch_info;
243 for (i = 0; i < 37; i++)
245 armv4_5->core_cache->reg_list[i].valid = 0;
246 armv4_5->core_cache->reg_list[i].dirty = 0;
252 reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
255 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
256 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
257 armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
260 cache->name = "arm v4/5 registers";
262 cache->reg_list = reg_list;
263 cache->num_regs = num_regs;
265 if (armv4_5_core_reg_arch_type == -1)
266 armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
268 register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
269 register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
271 for (i = 0; i < 37; i++)
273 arch_info[i] = armv4_5_core_reg_list_arch_info[i];
274 arch_info[i].target = target;
275 arch_info[i].armv4_5_common = armv4_5_common;
276 reg_list[i].name = armv4_5_core_reg_list[i];
277 reg_list[i].size = 32;
278 reg_list[i].value = calloc(1, 4);
279 reg_list[i].dirty = 0;
280 reg_list[i].valid = 0;
281 reg_list[i].bitfield_desc = NULL;
282 reg_list[i].num_bitfields = 0;
283 reg_list[i].arch_type = armv4_5_core_reg_arch_type;
284 reg_list[i].arch_info = &arch_info[i];
290 int armv4_5_arch_state(struct target_s *target)
292 armv4_5_common_t *armv4_5 = target->arch_info;
294 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
296 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
300 LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
301 armv4_5_state_strings[armv4_5->core_state],
302 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
303 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
304 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
305 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
310 int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
315 target_t *target = get_current_target(cmd_ctx);
316 armv4_5_common_t *armv4_5 = target->arch_info;
318 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
320 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
324 if (target->state != TARGET_HALTED)
326 command_print(cmd_ctx, "error: target must be halted for register accesses");
330 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
333 for (num = 0; num <= 15; num++)
336 for (mode = 0; mode < 6; mode++)
338 if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
340 armv4_5->full_context(target);
342 output_len += snprintf(output + output_len,
344 "%8s: %8.8" PRIx32 " ",
345 ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
346 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
348 command_print(cmd_ctx, "%s", output);
350 command_print(cmd_ctx,
351 " cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
352 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
353 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
354 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
355 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
356 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
357 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
362 int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
364 target_t *target = get_current_target(cmd_ctx);
365 armv4_5_common_t *armv4_5 = target->arch_info;
367 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
369 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
375 if (strcmp(args[0], "arm") == 0)
377 armv4_5->core_state = ARMV4_5_STATE_ARM;
379 if (strcmp(args[0], "thumb") == 0)
381 armv4_5->core_state = ARMV4_5_STATE_THUMB;
385 command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
391 handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx,
392 char *cmd, char **args, int argc)
394 int retval = ERROR_OK;
395 target_t *target = get_current_target(cmd_ctx);
396 armv4_5_common_t *armv4_5 = target->arch_info;
400 arm_instruction_t cur_instruction;
402 uint16_t thumb_opcode;
405 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
407 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
413 if (strcmp(args[2], "thumb") != 0)
418 count = strtoul(args[1], NULL, 0);
421 address = strtoul(args[0], NULL, 0);
422 if (address & 0x01) {
424 command_print(cmd_ctx, "Disassemble as Thumb");
432 command_print(cmd_ctx,
433 "usage: armv4_5 disassemble <address> [<count> ['thumb']]");
437 for (i = 0; i < count; i++)
441 if ((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
445 if ((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
451 if ((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
455 if ((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
460 command_print(cmd_ctx, "%s", cur_instruction.text);
461 address += (thumb) ? 2 : 4;
467 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
469 command_t *armv4_5_cmd;
471 armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
473 "armv4/5 specific commands");
475 register_command(cmd_ctx, armv4_5_cmd, "reg",
476 handle_armv4_5_reg_command, COMMAND_EXEC,
477 "display ARM core registers");
478 register_command(cmd_ctx, armv4_5_cmd, "core_state",
479 handle_armv4_5_core_state_command, COMMAND_EXEC,
480 "display/change ARM core state <arm | thumb>");
481 register_command(cmd_ctx, armv4_5_cmd, "disassemble",
482 handle_armv4_5_disassemble_command, COMMAND_EXEC,
483 "disassemble instructions <address> [<count> ['thumb']]");
488 int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
490 armv4_5_common_t *armv4_5 = target->arch_info;
493 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
497 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
499 for (i = 0; i < 16; i++)
501 (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
504 for (i = 16; i < 24; i++)
506 (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
509 (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
510 (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
515 /* wait for execution to complete and check exit point */
516 static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
519 armv4_5_common_t *armv4_5 = target->arch_info;
521 if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
525 if (target->state != TARGET_HALTED)
527 if ((retval = target_halt(target)) != ERROR_OK)
529 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
533 return ERROR_TARGET_TIMEOUT;
535 if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
537 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
538 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
539 return ERROR_TARGET_TIMEOUT;
545 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info))
547 armv4_5_common_t *armv4_5 = target->arch_info;
548 armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
549 enum armv4_5_state core_state = armv4_5->core_state;
550 enum armv4_5_mode core_mode = armv4_5->core_mode;
551 uint32_t context[17];
553 int exit_breakpoint_size = 0;
555 int retval = ERROR_OK;
556 LOG_DEBUG("Running algorithm");
558 if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
560 LOG_ERROR("current target isn't an ARMV4/5 target");
561 return ERROR_TARGET_INVALID;
564 if (target->state != TARGET_HALTED)
566 LOG_WARNING("target not halted");
567 return ERROR_TARGET_NOT_HALTED;
570 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
573 for (i = 0; i <= 16; i++)
575 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
576 armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
577 context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
579 cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
581 for (i = 0; i < num_mem_params; i++)
583 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
589 for (i = 0; i < num_reg_params; i++)
591 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
594 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
598 if (reg->size != reg_params[i].size)
600 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
604 if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
610 armv4_5->core_state = armv4_5_algorithm_info->core_state;
611 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
612 exit_breakpoint_size = 4;
613 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
614 exit_breakpoint_size = 2;
617 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
621 if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
623 LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
624 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
625 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
626 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
629 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
631 LOG_ERROR("can't add breakpoint to finish algorithm execution");
632 return ERROR_TARGET_FAILURE;
635 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
640 retval = run_it(target, exit_point, timeout_ms, arch_info);
642 breakpoint_remove(target, exit_point);
644 if (retval != ERROR_OK)
647 for (i = 0; i < num_mem_params; i++)
649 if (mem_params[i].direction != PARAM_OUT)
650 if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
656 for (i = 0; i < num_reg_params; i++)
658 if (reg_params[i].direction != PARAM_OUT)
661 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
664 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
668 if (reg->size != reg_params[i].size)
670 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
674 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
678 for (i = 0; i <= 16; i++)
681 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
682 if (regvalue != context[i])
684 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
685 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
686 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
687 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
690 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
691 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
692 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
694 armv4_5->core_state = core_state;
695 armv4_5->core_mode = core_mode;
700 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
702 return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
705 int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
707 target->arch_info = armv4_5;
709 armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
710 armv4_5->core_state = ARMV4_5_STATE_ARM;
711 armv4_5->core_mode = ARMV4_5_MODE_USR;