1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "arm_disassembler.h"
36 #include <helper/binarybuffer.h>
37 #include "algorithm.h"
40 /* offsets into armv4_5 core register cache */
42 /* ARMV4_5_CPSR = 31, */
43 ARMV4_5_SPSR_FIQ = 32,
44 ARMV4_5_SPSR_IRQ = 33,
45 ARMV4_5_SPSR_SVC = 34,
46 ARMV4_5_SPSR_ABT = 35,
47 ARMV4_5_SPSR_UND = 36,
51 static const uint8_t arm_usr_indices[17] = {
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
55 static const uint8_t arm_fiq_indices[8] = {
56 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
59 static const uint8_t arm_irq_indices[3] = {
60 23, 24, ARMV4_5_SPSR_IRQ,
63 static const uint8_t arm_svc_indices[3] = {
64 25, 26, ARMV4_5_SPSR_SVC,
67 static const uint8_t arm_abt_indices[3] = {
68 27, 28, ARMV4_5_SPSR_ABT,
71 static const uint8_t arm_und_indices[3] = {
72 29, 30, ARMV4_5_SPSR_UND,
75 static const uint8_t arm_mon_indices[3] = {
82 /* For user and system modes, these list indices for all registers.
83 * otherwise they're just indices for the shadow registers and SPSR.
85 unsigned short n_indices;
86 const uint8_t *indices;
88 /* Seven modes are standard from ARM7 on. "System" and "User" share
89 * the same registers; other modes shadow from 3 to 8 registers.
94 .n_indices = ARRAY_SIZE(arm_usr_indices),
95 .indices = arm_usr_indices,
100 .n_indices = ARRAY_SIZE(arm_fiq_indices),
101 .indices = arm_fiq_indices,
104 .name = "Supervisor",
106 .n_indices = ARRAY_SIZE(arm_svc_indices),
107 .indices = arm_svc_indices,
112 .n_indices = ARRAY_SIZE(arm_abt_indices),
113 .indices = arm_abt_indices,
118 .n_indices = ARRAY_SIZE(arm_irq_indices),
119 .indices = arm_irq_indices,
122 .name = "Undefined instruction",
124 .n_indices = ARRAY_SIZE(arm_und_indices),
125 .indices = arm_und_indices,
130 .n_indices = ARRAY_SIZE(arm_usr_indices),
131 .indices = arm_usr_indices,
133 /* TrustZone "Security Extensions" add a secure monitor mode.
134 * This is distinct from a "debug monitor" which can support
135 * non-halting debug, in conjunction with some debuggers.
138 .name = "Secure Monitor",
140 .n_indices = ARRAY_SIZE(arm_mon_indices),
141 .indices = arm_mon_indices,
144 .name = "Secure Monitor ARM1176JZF-S",
145 .psr = ARM_MODE_1176_MON,
146 .n_indices = ARRAY_SIZE(arm_mon_indices),
147 .indices = arm_mon_indices,
150 /* These special modes are currently only supported
151 * by ARMv6M and ARMv7M profiles */
154 .psr = ARM_MODE_THREAD,
157 .name = "Thread (User)",
158 .psr = ARM_MODE_USER_THREAD,
162 .psr = ARM_MODE_HANDLER,
166 /** Map PSR mode bits to the name of an ARM processor operating mode. */
167 const char *arm_mode_name(unsigned psr_mode)
169 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
170 if (arm_mode_data[i].psr == psr_mode)
171 return arm_mode_data[i].name;
173 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
174 return "UNRECOGNIZED";
177 /** Return true iff the parameter denotes a valid ARM processor mode. */
178 bool is_arm_mode(unsigned psr_mode)
180 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
181 if (arm_mode_data[i].psr == psr_mode)
187 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
188 int arm_mode_to_number(enum arm_mode mode)
192 /* map MODE_ANY to user mode */
208 case ARM_MODE_1176_MON:
211 LOG_ERROR("invalid mode value encountered %d", mode);
216 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
217 enum arm_mode armv4_5_number_to_mode(int number)
237 LOG_ERROR("mode index out of bounds %d", number);
242 static const char *arm_state_strings[] = {
243 "ARM", "Thumb", "Jazelle", "ThumbEE",
246 /* Templates for ARM core registers.
248 * NOTE: offsets in this table are coupled to the arm_mode_data
249 * table above, the armv4_5_core_reg_map array below, and also to
250 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
252 static const struct {
253 /* The name is used for e.g. the "regs" command. */
256 /* The {cookie, mode} tuple uniquely identifies one register.
257 * In a given mode, cookies 0..15 map to registers R0..R15,
258 * with R13..R15 usually called SP, LR, PC.
260 * MODE_ANY is used as *input* to the mapping, and indicates
261 * various special cases (sigh) and errors.
263 * Cookie 16 is (currently) confusing, since it indicates
264 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
265 * (Exception modes have both CPSR and SPSR registers ...)
270 } arm_core_regs[] = {
271 /* IMPORTANT: we guarantee that the first eight cached registers
272 * correspond to r0..r7, and the fifteenth to PC, so that callers
273 * don't need to map them.
275 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
276 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
277 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
278 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
279 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
280 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
281 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
282 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
284 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
285 * them as MODE_ANY creates special cases. (ANY means
286 * "not mapped" elsewhere; here it's "everything but FIQ".)
288 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
289 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
290 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
291 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
292 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
294 /* Historical GDB mapping of indices:
295 * - 13-14 are sp and lr, but banked counterparts are used
296 * - 16-24 are left for deprecated 8 FPA + 1 FPS
300 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
301 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
302 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
304 /* guaranteed to be at index 15 */
305 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
306 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
307 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
308 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
309 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
310 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
312 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
313 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
315 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
316 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
318 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
319 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
321 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
322 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
324 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
325 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
327 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
328 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
329 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
330 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
331 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
332 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
334 /* These are only used for GDB target description, banked registers are accessed instead */
335 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
336 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
338 /* These exist only when the Security Extension (TrustZone) is present */
339 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
340 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
341 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
345 /* map core mode (USR, FIQ, ...) and register number to
346 * indices into the register cache
348 const int armv4_5_core_reg_map[8][17] = {
350 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
352 { /* FIQ (8 shadows of USR, vs normal 3) */
353 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
356 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
359 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
362 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
365 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
367 { /* SYS (same registers as USR) */
368 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
371 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
376 * Configures host-side ARM records to reflect the specified CPSR.
377 * Later, code can use arm_reg_current() to map register numbers
378 * according to how they are exposed by this mode.
380 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
382 enum arm_mode mode = cpsr & 0x1f;
385 /* NOTE: this may be called very early, before the register
386 * cache is set up. We can't defend against many errors, in
387 * particular against CPSRs that aren't valid *here* ...
390 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
391 arm->cpsr->valid = 1;
392 arm->cpsr->dirty = 0;
395 arm->core_mode = mode;
397 /* mode_to_number() warned; set up a somewhat-sane mapping */
398 num = arm_mode_to_number(mode);
404 arm->map = &armv4_5_core_reg_map[num][0];
405 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
407 : arm->core_cache->reg_list + arm->map[16];
409 /* Older ARMs won't have the J bit */
410 enum arm_state state;
412 if (cpsr & (1 << 5)) { /* T */
413 if (cpsr & (1 << 24)) { /* J */
414 LOG_WARNING("ThumbEE -- incomplete support");
415 state = ARM_STATE_THUMB_EE;
417 state = ARM_STATE_THUMB;
419 if (cpsr & (1 << 24)) { /* J */
420 LOG_ERROR("Jazelle state handling is BROKEN!");
421 state = ARM_STATE_JAZELLE;
423 state = ARM_STATE_ARM;
425 arm->core_state = state;
427 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
429 arm_state_strings[arm->core_state]);
433 * Returns handle to the register currently mapped to a given number.
434 * Someone must have called arm_set_cpsr() before.
436 * \param arm This core's state and registers are used.
437 * \param regnum From 0..15 corresponding to R0..R14 and PC.
438 * Note that R0..R7 don't require mapping; you may access those
439 * as the first eight entries in the register cache. Likewise
440 * R15 (PC) doesn't need mapping; you may also access it directly.
441 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
442 * CPSR (arm->cpsr) is also not mapped.
444 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
452 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
453 r = arm->core_cache->reg_list + regnum;
455 r = arm->core_cache->reg_list + arm->map[regnum];
457 /* e.g. invalid CPSR said "secure monitor" mode on a core
458 * that doesn't support it...
461 LOG_ERROR("Invalid CPSR mode");
462 r = arm->core_cache->reg_list + regnum;
468 static const uint8_t arm_gdb_dummy_fp_value[12];
470 static struct reg_feature arm_gdb_dummy_fp_features = {
471 .name = "net.sourceforge.openocd.fake_fpa"
475 * Dummy FPA registers are required to support GDB on ARM.
476 * Register packets require eight obsolete FPA register values.
477 * Modern ARM cores use Vector Floating Point (VFP), if they
478 * have any floating point support. VFP is not FPA-compatible.
480 struct reg arm_gdb_dummy_fp_reg = {
481 .name = "GDB dummy FPA register",
482 .value = (uint8_t *) arm_gdb_dummy_fp_value,
487 .feature = &arm_gdb_dummy_fp_features,
491 static const uint8_t arm_gdb_dummy_fps_value[4];
494 * Dummy FPA status registers are required to support GDB on ARM.
495 * Register packets require an obsolete FPA status register.
497 struct reg arm_gdb_dummy_fps_reg = {
498 .name = "GDB dummy FPA status register",
499 .value = (uint8_t *) arm_gdb_dummy_fps_value,
504 .feature = &arm_gdb_dummy_fp_features,
508 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
510 static void arm_gdb_dummy_init(void)
512 register_init_dummy(&arm_gdb_dummy_fp_reg);
513 register_init_dummy(&arm_gdb_dummy_fps_reg);
516 static int armv4_5_get_core_reg(struct reg *reg)
519 struct arm_reg *reg_arch_info = reg->arch_info;
520 struct target *target = reg_arch_info->target;
522 if (target->state != TARGET_HALTED) {
523 LOG_ERROR("Target not halted");
524 return ERROR_TARGET_NOT_HALTED;
527 retval = reg_arch_info->arm->read_core_reg(target, reg,
528 reg_arch_info->num, reg_arch_info->mode);
529 if (retval == ERROR_OK) {
537 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
539 struct arm_reg *reg_arch_info = reg->arch_info;
540 struct target *target = reg_arch_info->target;
541 struct arm *armv4_5_target = target_to_arm(target);
542 uint32_t value = buf_get_u32(buf, 0, 32);
544 if (target->state != TARGET_HALTED) {
545 LOG_ERROR("Target not halted");
546 return ERROR_TARGET_NOT_HALTED;
549 /* Except for CPSR, the "reg" command exposes a writeback model
550 * for the register cache.
552 if (reg == armv4_5_target->cpsr) {
553 arm_set_cpsr(armv4_5_target, value);
555 /* Older cores need help to be in ARM mode during halt
556 * mode debug, so we clear the J and T bits if we flush.
557 * For newer cores (v6/v7a/v7r) we don't need that, but
558 * it won't hurt since CPSR is always flushed anyway.
560 if (armv4_5_target->core_mode !=
561 (enum arm_mode)(value & 0x1f)) {
562 LOG_DEBUG("changing ARM core mode to '%s'",
563 arm_mode_name(value & 0x1f));
564 value &= ~((1 << 24) | (1 << 5));
566 buf_set_u32(t, 0, 32, value);
567 armv4_5_target->write_core_reg(target, reg,
568 16, ARM_MODE_ANY, t);
571 buf_set_u32(reg->value, 0, 32, value);
579 static const struct reg_arch_type arm_reg_type = {
580 .get = armv4_5_get_core_reg,
581 .set = armv4_5_set_core_reg,
584 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
586 int num_regs = ARRAY_SIZE(arm_core_regs);
587 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
588 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
589 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
592 if (!cache || !reg_list || !reg_arch_info) {
599 cache->name = "ARM registers";
601 cache->reg_list = reg_list;
604 for (i = 0; i < num_regs; i++) {
605 /* Skip registers this core doesn't expose */
606 if (arm_core_regs[i].mode == ARM_MODE_MON
607 && arm->core_type != ARM_MODE_MON)
610 /* REVISIT handle Cortex-M, which only shadows R13/SP */
612 reg_arch_info[i].num = arm_core_regs[i].cookie;
613 reg_arch_info[i].mode = arm_core_regs[i].mode;
614 reg_arch_info[i].target = target;
615 reg_arch_info[i].arm = arm;
617 reg_list[i].name = arm_core_regs[i].name;
618 reg_list[i].number = arm_core_regs[i].gdb_index;
619 reg_list[i].size = 32;
620 reg_list[i].value = reg_arch_info[i].value;
621 reg_list[i].type = &arm_reg_type;
622 reg_list[i].arch_info = ®_arch_info[i];
623 reg_list[i].exist = true;
625 /* This really depends on the calling convention in use */
626 reg_list[i].caller_save = false;
628 /* Registers data type, as used by GDB target description */
629 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
630 switch (arm_core_regs[i].cookie) {
632 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
636 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
639 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
643 /* let GDB shows banked registers only in "info all-reg" */
644 reg_list[i].feature = malloc(sizeof(struct reg_feature));
645 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
646 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
647 reg_list[i].group = "general";
649 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
650 reg_list[i].group = "banked";
656 arm->pc = reg_list + 15;
657 arm->cpsr = reg_list + ARMV4_5_CPSR;
658 arm->core_cache = cache;
662 int arm_arch_state(struct target *target)
664 struct arm *arm = target_to_arm(target);
666 if (arm->common_magic != ARM_COMMON_MAGIC) {
667 LOG_ERROR("BUG: called for a non-ARM target");
671 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
672 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
673 arm_state_strings[arm->core_state],
674 debug_reason_name(target),
675 arm_mode_name(arm->core_mode),
676 buf_get_u32(arm->cpsr->value, 0, 32),
677 buf_get_u32(arm->pc->value, 0, 32),
678 arm->is_semihosting ? ", semihosting" : "");
683 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
684 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
686 COMMAND_HANDLER(handle_armv4_5_reg_command)
688 struct target *target = get_current_target(CMD_CTX);
689 struct arm *arm = target_to_arm(target);
693 command_print(CMD_CTX, "current target isn't an ARM");
697 if (target->state != TARGET_HALTED) {
698 command_print(CMD_CTX, "error: target must be halted for register accesses");
702 if (arm->core_type != ARM_MODE_ANY) {
703 command_print(CMD_CTX,
704 "Microcontroller Profile not supported - use standard reg cmd");
708 if (!is_arm_mode(arm->core_mode)) {
709 LOG_ERROR("not a valid arm core mode - communication failure?");
713 if (!arm->full_context) {
714 command_print(CMD_CTX, "error: target doesn't support %s",
719 regs = arm->core_cache->reg_list;
721 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
726 /* label this bank of registers (or shadows) */
727 switch (arm_mode_data[mode].psr) {
731 name = "System and User";
735 if (arm->core_type != ARM_MODE_MON)
739 name = arm_mode_data[mode].name;
743 command_print(CMD_CTX, "%s%s mode %sregisters",
746 /* display N rows of up to 4 registers each */
747 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
751 for (unsigned j = 0; j < 4; j++, i++) {
753 struct reg *reg = regs;
755 if (i >= arm_mode_data[mode].n_indices)
758 reg += arm_mode_data[mode].indices[i];
760 /* REVISIT be smarter about faults... */
762 arm->full_context(target);
764 value = buf_get_u32(reg->value, 0, 32);
765 output_len += snprintf(output + output_len,
766 sizeof(output) - output_len,
767 "%8s: %8.8" PRIx32 " ",
770 command_print(CMD_CTX, "%s", output);
777 COMMAND_HANDLER(handle_armv4_5_core_state_command)
779 struct target *target = get_current_target(CMD_CTX);
780 struct arm *arm = target_to_arm(target);
783 command_print(CMD_CTX, "current target isn't an ARM");
787 if (arm->core_type == ARM_MODE_THREAD) {
788 /* armv7m not supported */
789 command_print(CMD_CTX, "Unsupported Command");
794 if (strcmp(CMD_ARGV[0], "arm") == 0)
795 arm->core_state = ARM_STATE_ARM;
796 if (strcmp(CMD_ARGV[0], "thumb") == 0)
797 arm->core_state = ARM_STATE_THUMB;
800 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
805 COMMAND_HANDLER(handle_arm_disassemble_command)
807 int retval = ERROR_OK;
808 struct target *target = get_current_target(CMD_CTX);
810 if (target == NULL) {
811 LOG_ERROR("No target selected");
815 struct arm *arm = target_to_arm(target);
821 command_print(CMD_CTX, "current target isn't an ARM");
825 if (arm->core_type == ARM_MODE_THREAD) {
826 /* armv7m is always thumb mode */
832 if (strcmp(CMD_ARGV[2], "thumb") != 0)
837 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
840 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
841 if (address & 0x01) {
843 command_print(CMD_CTX, "Disassemble as Thumb");
852 retval = ERROR_COMMAND_SYNTAX_ERROR;
855 while (count-- > 0) {
856 struct arm_instruction cur_instruction;
859 /* Always use Thumb2 disassembly for best handling
860 * of 32-bit BL/BLX, and to work with newer cores
861 * (some ARMv6, all ARMv7) that use Thumb2.
863 retval = thumb2_opcode(target, address,
865 if (retval != ERROR_OK)
870 retval = target_read_u32(target, address, &opcode);
871 if (retval != ERROR_OK)
873 retval = arm_evaluate_opcode(opcode, address,
874 &cur_instruction) != ERROR_OK;
875 if (retval != ERROR_OK)
878 command_print(CMD_CTX, "%s", cur_instruction.text);
879 address += cur_instruction.instruction_size;
885 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
887 struct command_context *context;
888 struct target *target;
892 context = current_command_context(interp);
893 assert(context != NULL);
895 target = get_current_target(context);
896 if (target == NULL) {
897 LOG_ERROR("%s: no current target", __func__);
900 if (!target_was_examined(target)) {
901 LOG_ERROR("%s: not yet examined", target_name(target));
904 arm = target_to_arm(target);
906 LOG_ERROR("%s: not an ARM", target_name(target));
910 if ((argc < 6) || (argc > 7)) {
911 /* FIXME use the command name to verify # params... */
912 LOG_ERROR("%s: wrong number of arguments", __func__);
924 /* NOTE: parameter sequence matches ARM instruction set usage:
925 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
926 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
927 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
929 retval = Jim_GetLong(interp, argv[1], &l);
930 if (retval != JIM_OK)
933 LOG_ERROR("%s: %s %d out of range", __func__,
934 "coprocessor", (int) l);
939 retval = Jim_GetLong(interp, argv[2], &l);
940 if (retval != JIM_OK)
943 LOG_ERROR("%s: %s %d out of range", __func__,
949 retval = Jim_GetLong(interp, argv[3], &l);
950 if (retval != JIM_OK)
953 LOG_ERROR("%s: %s %d out of range", __func__,
959 retval = Jim_GetLong(interp, argv[4], &l);
960 if (retval != JIM_OK)
963 LOG_ERROR("%s: %s %d out of range", __func__,
969 retval = Jim_GetLong(interp, argv[5], &l);
970 if (retval != JIM_OK)
973 LOG_ERROR("%s: %s %d out of range", __func__,
981 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
982 * that could easily be a typo! Check both...
984 * FIXME change the call syntax here ... simplest to just pass
985 * the MRC() or MCR() instruction to be executed. That will also
986 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
987 * if that's ever needed.
990 retval = Jim_GetLong(interp, argv[6], &l);
991 if (retval != JIM_OK)
995 /* NOTE: parameters reordered! */
996 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
997 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
998 if (retval != ERROR_OK)
1001 /* NOTE: parameters reordered! */
1002 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1003 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1004 if (retval != ERROR_OK)
1007 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1013 COMMAND_HANDLER(handle_arm_semihosting_command)
1015 struct target *target = get_current_target(CMD_CTX);
1017 if (target == NULL) {
1018 LOG_ERROR("No target selected");
1022 struct arm *arm = target_to_arm(target);
1025 command_print(CMD_CTX, "current target isn't an ARM");
1029 if (!arm->setup_semihosting) {
1030 command_print(CMD_CTX, "semihosting not supported for current target");
1037 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1039 if (!target_was_examined(target)) {
1040 LOG_ERROR("Target not examined yet");
1044 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1045 LOG_ERROR("Failed to Configure semihosting");
1049 /* FIXME never let that "catch" be dropped! */
1050 arm->is_semihosting = semihosting;
1053 command_print(CMD_CTX, "semihosting is %s",
1055 ? "enabled" : "disabled");
1060 static const struct command_registration arm_exec_command_handlers[] = {
1063 .handler = handle_armv4_5_reg_command,
1064 .mode = COMMAND_EXEC,
1065 .help = "display ARM core registers",
1069 .name = "core_state",
1070 .handler = handle_armv4_5_core_state_command,
1071 .mode = COMMAND_EXEC,
1072 .usage = "['arm'|'thumb']",
1073 .help = "display/change ARM core state",
1076 .name = "disassemble",
1077 .handler = handle_arm_disassemble_command,
1078 .mode = COMMAND_EXEC,
1079 .usage = "address [count ['thumb']]",
1080 .help = "disassemble instructions ",
1084 .mode = COMMAND_EXEC,
1085 .jim_handler = &jim_mcrmrc,
1086 .help = "write coprocessor register",
1087 .usage = "cpnum op1 CRn CRm op2 value",
1091 .jim_handler = &jim_mcrmrc,
1092 .help = "read coprocessor register",
1093 .usage = "cpnum op1 CRn CRm op2",
1097 .handler = handle_arm_semihosting_command,
1098 .mode = COMMAND_EXEC,
1099 .usage = "['enable'|'disable']",
1100 .help = "activate support for semihosting operations",
1103 COMMAND_REGISTRATION_DONE
1105 const struct command_registration arm_command_handlers[] = {
1108 .mode = COMMAND_ANY,
1109 .help = "ARM command group",
1111 .chain = arm_exec_command_handlers,
1113 COMMAND_REGISTRATION_DONE
1116 int arm_get_gdb_reg_list(struct target *target,
1117 struct reg **reg_list[], int *reg_list_size,
1118 enum target_register_class reg_class)
1120 struct arm *arm = target_to_arm(target);
1123 if (!is_arm_mode(arm->core_mode)) {
1124 LOG_ERROR("not a valid arm core mode - communication failure?");
1128 switch (reg_class) {
1129 case REG_CLASS_GENERAL:
1130 *reg_list_size = 26;
1131 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1133 for (i = 0; i < 16; i++)
1134 (*reg_list)[i] = arm_reg_current(arm, i);
1136 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1137 for (i = 16; i < 24; i++)
1138 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1139 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1141 (*reg_list)[25] = arm->cpsr;
1147 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1148 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1150 for (i = 0; i < 16; i++)
1151 (*reg_list)[i] = arm_reg_current(arm, i);
1153 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1154 int reg_index = arm->core_cache->reg_list[i].number;
1155 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1156 && arm->core_type != ARM_MODE_MON))
1157 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1160 /* When we supply the target description, there is no need for fake FPA */
1161 for (i = 16; i < 24; i++) {
1162 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1163 (*reg_list)[i]->size = 0;
1165 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1166 (*reg_list)[24]->size = 0;
1172 LOG_ERROR("not a valid register class type in query.");
1178 /* wait for execution to complete and check exit point */
1179 static int armv4_5_run_algorithm_completion(struct target *target,
1180 uint32_t exit_point,
1185 struct arm *arm = target_to_arm(target);
1187 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1188 if (retval != ERROR_OK)
1190 if (target->state != TARGET_HALTED) {
1191 retval = target_halt(target);
1192 if (retval != ERROR_OK)
1194 retval = target_wait_state(target, TARGET_HALTED, 500);
1195 if (retval != ERROR_OK)
1197 return ERROR_TARGET_TIMEOUT;
1200 /* fast exit: ARMv5+ code can use BKPT */
1201 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1203 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1204 buf_get_u32(arm->pc->value, 0, 32));
1205 return ERROR_TARGET_TIMEOUT;
1211 int armv4_5_run_algorithm_inner(struct target *target,
1212 int num_mem_params, struct mem_param *mem_params,
1213 int num_reg_params, struct reg_param *reg_params,
1214 uint32_t entry_point, uint32_t exit_point,
1215 int timeout_ms, void *arch_info,
1216 int (*run_it)(struct target *target, uint32_t exit_point,
1217 int timeout_ms, void *arch_info))
1219 struct arm *arm = target_to_arm(target);
1220 struct arm_algorithm *arm_algorithm_info = arch_info;
1221 enum arm_state core_state = arm->core_state;
1222 uint32_t context[17];
1224 int exit_breakpoint_size = 0;
1226 int retval = ERROR_OK;
1228 LOG_DEBUG("Running algorithm");
1230 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1231 LOG_ERROR("current target isn't an ARMV4/5 target");
1232 return ERROR_TARGET_INVALID;
1235 if (target->state != TARGET_HALTED) {
1236 LOG_WARNING("target not halted");
1237 return ERROR_TARGET_NOT_HALTED;
1240 if (!is_arm_mode(arm->core_mode)) {
1241 LOG_ERROR("not a valid arm core mode - communication failure?");
1245 /* armv5 and later can terminate with BKPT instruction; less overhead */
1246 if (!exit_point && arm->is_armv4) {
1247 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1251 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1252 * they'll be restored later.
1254 for (i = 0; i <= 16; i++) {
1257 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1258 arm_algorithm_info->core_mode, i);
1260 arm->read_core_reg(target, r, i,
1261 arm_algorithm_info->core_mode);
1262 context[i] = buf_get_u32(r->value, 0, 32);
1264 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1266 for (i = 0; i < num_mem_params; i++) {
1267 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1268 mem_params[i].value);
1269 if (retval != ERROR_OK)
1273 for (i = 0; i < num_reg_params; i++) {
1274 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1276 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1277 return ERROR_COMMAND_SYNTAX_ERROR;
1280 if (reg->size != reg_params[i].size) {
1281 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1282 reg_params[i].reg_name);
1283 return ERROR_COMMAND_SYNTAX_ERROR;
1286 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1287 if (retval != ERROR_OK)
1291 arm->core_state = arm_algorithm_info->core_state;
1292 if (arm->core_state == ARM_STATE_ARM)
1293 exit_breakpoint_size = 4;
1294 else if (arm->core_state == ARM_STATE_THUMB)
1295 exit_breakpoint_size = 2;
1297 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1298 return ERROR_COMMAND_SYNTAX_ERROR;
1301 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1302 LOG_DEBUG("setting core_mode: 0x%2.2x",
1303 arm_algorithm_info->core_mode);
1304 buf_set_u32(arm->cpsr->value, 0, 5,
1305 arm_algorithm_info->core_mode);
1306 arm->cpsr->dirty = 1;
1307 arm->cpsr->valid = 1;
1310 /* terminate using a hardware or (ARMv5+) software breakpoint */
1312 retval = breakpoint_add(target, exit_point,
1313 exit_breakpoint_size, BKPT_HARD);
1314 if (retval != ERROR_OK) {
1315 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1316 return ERROR_TARGET_FAILURE;
1320 retval = target_resume(target, 0, entry_point, 1, 1);
1321 if (retval != ERROR_OK)
1323 retval = run_it(target, exit_point, timeout_ms, arch_info);
1326 breakpoint_remove(target, exit_point);
1328 if (retval != ERROR_OK)
1331 for (i = 0; i < num_mem_params; i++) {
1332 if (mem_params[i].direction != PARAM_OUT) {
1333 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1335 mem_params[i].value);
1336 if (retvaltemp != ERROR_OK)
1337 retval = retvaltemp;
1341 for (i = 0; i < num_reg_params; i++) {
1342 if (reg_params[i].direction != PARAM_OUT) {
1344 struct reg *reg = register_get_by_name(arm->core_cache,
1345 reg_params[i].reg_name,
1348 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1349 retval = ERROR_COMMAND_SYNTAX_ERROR;
1353 if (reg->size != reg_params[i].size) {
1355 "BUG: register '%s' size doesn't match reg_params[i].size",
1356 reg_params[i].reg_name);
1357 retval = ERROR_COMMAND_SYNTAX_ERROR;
1361 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1365 /* restore everything we saved before (17 or 18 registers) */
1366 for (i = 0; i <= 16; i++) {
1368 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1369 arm_algorithm_info->core_mode, i).value, 0, 32);
1370 if (regvalue != context[i]) {
1371 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1372 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1373 arm_algorithm_info->core_mode, i).name, context[i]);
1374 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1375 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1376 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1378 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1383 arm_set_cpsr(arm, cpsr);
1384 arm->cpsr->dirty = 1;
1386 arm->core_state = core_state;
1391 int armv4_5_run_algorithm(struct target *target,
1393 struct mem_param *mem_params,
1395 struct reg_param *reg_params,
1396 uint32_t entry_point,
1397 uint32_t exit_point,
1401 return armv4_5_run_algorithm_inner(target,
1410 armv4_5_run_algorithm_completion);
1414 * Runs ARM code in the target to calculate a CRC32 checksum.
1417 int arm_checksum_memory(struct target *target,
1418 uint32_t address, uint32_t count, uint32_t *checksum)
1420 struct working_area *crc_algorithm;
1421 struct arm_algorithm arm_algo;
1422 struct arm *arm = target_to_arm(target);
1423 struct reg_param reg_params[2];
1426 uint32_t exit_var = 0;
1428 /* see contrib/loaders/checksum/armv4_5_crc.s for src */
1430 static const uint32_t arm_crc_code[] = {
1431 0xE1A02000, /* mov r2, r0 */
1432 0xE3E00000, /* mov r0, #0xffffffff */
1433 0xE1A03001, /* mov r3, r1 */
1434 0xE3A04000, /* mov r4, #0 */
1435 0xEA00000B, /* b ncomp */
1437 0xE7D21004, /* ldrb r1, [r2, r4] */
1438 0xE59F7030, /* ldr r7, CRC32XOR */
1439 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1440 0xE3A05000, /* mov r5, #0 */
1442 0xE3500000, /* cmp r0, #0 */
1443 0xE1A06080, /* mov r6, r0, asl #1 */
1444 0xE2855001, /* add r5, r5, #1 */
1445 0xE1A00006, /* mov r0, r6 */
1446 0xB0260007, /* eorlt r0, r6, r7 */
1447 0xE3550008, /* cmp r5, #8 */
1448 0x1AFFFFF8, /* bne loop */
1449 0xE2844001, /* add r4, r4, #1 */
1451 0xE1540003, /* cmp r4, r3 */
1452 0x1AFFFFF1, /* bne nbyte */
1454 0xe1200070, /* bkpt #0 */
1456 0x04C11DB7 /* .word 0x04C11DB7 */
1459 retval = target_alloc_working_area(target,
1460 sizeof(arm_crc_code), &crc_algorithm);
1461 if (retval != ERROR_OK)
1464 /* convert code into a buffer in target endianness */
1465 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1466 retval = target_write_u32(target,
1467 crc_algorithm->address + i * sizeof(uint32_t),
1469 if (retval != ERROR_OK)
1473 arm_algo.common_magic = ARM_COMMON_MAGIC;
1474 arm_algo.core_mode = ARM_MODE_SVC;
1475 arm_algo.core_state = ARM_STATE_ARM;
1477 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
1478 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1480 buf_set_u32(reg_params[0].value, 0, 32, address);
1481 buf_set_u32(reg_params[1].value, 0, 32, count);
1483 /* 20 second timeout/megabyte */
1484 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1486 /* armv4 must exit using a hardware breakpoint */
1488 exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
1490 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1491 crc_algorithm->address,
1493 timeout, &arm_algo);
1494 if (retval != ERROR_OK) {
1495 LOG_ERROR("error executing ARM crc algorithm");
1496 destroy_reg_param(®_params[0]);
1497 destroy_reg_param(®_params[1]);
1498 target_free_working_area(target, crc_algorithm);
1502 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1504 destroy_reg_param(®_params[0]);
1505 destroy_reg_param(®_params[1]);
1507 target_free_working_area(target, crc_algorithm);
1513 * Runs ARM code in the target to check whether a memory block holds
1514 * all ones. NOR flash which has been erased, and thus may be written,
1518 int arm_blank_check_memory(struct target *target,
1519 uint32_t address, uint32_t count, uint32_t *blank)
1521 struct working_area *check_algorithm;
1522 struct reg_param reg_params[3];
1523 struct arm_algorithm arm_algo;
1524 struct arm *arm = target_to_arm(target);
1527 uint32_t exit_var = 0;
1529 /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
1531 static const uint32_t check_code[] = {
1533 0xe4d03001, /* ldrb r3, [r0], #1 */
1534 0xe0022003, /* and r2, r2, r3 */
1535 0xe2511001, /* subs r1, r1, #1 */
1536 0x1afffffb, /* bne loop */
1538 0xe1200070, /* bkpt #0 */
1541 /* make sure we have a working area */
1542 retval = target_alloc_working_area(target,
1543 sizeof(check_code), &check_algorithm);
1544 if (retval != ERROR_OK)
1547 /* convert code into a buffer in target endianness */
1548 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1549 retval = target_write_u32(target,
1550 check_algorithm->address
1551 + i * sizeof(uint32_t),
1553 if (retval != ERROR_OK)
1557 arm_algo.common_magic = ARM_COMMON_MAGIC;
1558 arm_algo.core_mode = ARM_MODE_SVC;
1559 arm_algo.core_state = ARM_STATE_ARM;
1561 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1562 buf_set_u32(reg_params[0].value, 0, 32, address);
1564 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1565 buf_set_u32(reg_params[1].value, 0, 32, count);
1567 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
1568 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1570 /* armv4 must exit using a hardware breakpoint */
1572 exit_var = check_algorithm->address + sizeof(check_code) - 4;
1574 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1575 check_algorithm->address,
1579 if (retval == ERROR_OK)
1580 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1582 destroy_reg_param(®_params[0]);
1583 destroy_reg_param(®_params[1]);
1584 destroy_reg_param(®_params[2]);
1587 target_free_working_area(target, check_algorithm);
1592 static int arm_full_context(struct target *target)
1594 struct arm *arm = target_to_arm(target);
1595 unsigned num_regs = arm->core_cache->num_regs;
1596 struct reg *reg = arm->core_cache->reg_list;
1597 int retval = ERROR_OK;
1599 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1602 retval = armv4_5_get_core_reg(reg);
1607 static int arm_default_mrc(struct target *target, int cpnum,
1608 uint32_t op1, uint32_t op2,
1609 uint32_t CRn, uint32_t CRm,
1612 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1616 static int arm_default_mcr(struct target *target, int cpnum,
1617 uint32_t op1, uint32_t op2,
1618 uint32_t CRn, uint32_t CRm,
1621 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1625 int arm_init_arch_info(struct target *target, struct arm *arm)
1627 target->arch_info = arm;
1628 arm->target = target;
1630 arm->common_magic = ARM_COMMON_MAGIC;
1632 /* core_type may be overridden by subtype logic */
1633 if (arm->core_type != ARM_MODE_THREAD) {
1634 arm->core_type = ARM_MODE_ANY;
1635 arm_set_cpsr(arm, ARM_MODE_USR);
1638 /* default full_context() has no core-specific optimizations */
1639 if (!arm->full_context && arm->read_core_reg)
1640 arm->full_context = arm_full_context;
1643 arm->mrc = arm_default_mrc;
1645 arm->mcr = arm_default_mcr;