1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 typedef enum armv4_5_mode
29 ARMV4_5_MODE_USR = 16,
30 ARMV4_5_MODE_FIQ = 17,
31 ARMV4_5_MODE_IRQ = 18,
32 ARMV4_5_MODE_SVC = 19,
33 ARMV4_5_MODE_ABT = 23,
34 ARMV4_5_MODE_UND = 27,
35 ARMV4_5_MODE_SYS = 31,
39 extern char** armv4_5_mode_strings;
41 typedef enum armv4_5_state
45 ARMV4_5_STATE_JAZELLE,
48 extern char* armv4_5_state_strings[];
50 extern int armv4_5_core_reg_map[7][17];
52 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
53 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
54 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
55 cache->reg_list[armv4_5_core_reg_map[mode][num]]
57 /* offsets into armv4_5 core register cache */
61 ARMV4_5_SPSR_FIQ = 32,
62 ARMV4_5_SPSR_IRQ = 33,
63 ARMV4_5_SPSR_SVC = 34,
64 ARMV4_5_SPSR_ABT = 35,
68 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
70 typedef struct armv4_5_common_s
73 reg_cache_t *core_cache;
74 enum armv4_5_mode core_mode;
75 enum armv4_5_state core_state;
76 int (*full_context)(struct target_s *target);
77 int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
78 int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
82 typedef struct armv4_5_algorithm_s
86 enum armv4_5_mode core_mode;
87 enum armv4_5_state core_state;
88 } armv4_5_algorithm_t;
90 typedef struct armv4_5_core_reg_s
93 enum armv4_5_mode mode;
95 armv4_5_common_t *armv4_5_common;
98 extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
100 /* map psr mode bits to linear number */
101 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
105 case ARMV4_5_MODE_USR: return 0; break;
106 case ARMV4_5_MODE_FIQ: return 1; break;
107 case ARMV4_5_MODE_IRQ: return 2; break;
108 case ARMV4_5_MODE_SVC: return 3; break;
109 case ARMV4_5_MODE_ABT: return 4; break;
110 case ARMV4_5_MODE_UND: return 5; break;
111 case ARMV4_5_MODE_SYS: return 6; break;
112 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
114 LOG_ERROR("invalid mode value encountered");
119 /* map linear number to mode bits */
120 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
124 case 0: return ARMV4_5_MODE_USR; break;
125 case 1: return ARMV4_5_MODE_FIQ; break;
126 case 2: return ARMV4_5_MODE_IRQ; break;
127 case 3: return ARMV4_5_MODE_SVC; break;
128 case 4: return ARMV4_5_MODE_ABT; break;
129 case 5: return ARMV4_5_MODE_UND; break;
130 case 6: return ARMV4_5_MODE_SYS; break;
132 LOG_ERROR("mode index out of bounds");
138 extern int armv4_5_arch_state(struct target_s *target);
139 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
140 extern int armv4_5_invalidate_core_regs(target_t *target);
142 extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
143 extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
145 extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
147 extern int armv4_5_invalidate_core_regs(target_t *target);
149 /* ARM mode instructions
152 /* Store multiple increment after
154 * List: for each bit in list: store register
155 * S: in priviledged mode: store user-mode registers
156 * W=1: update the base register. W=0: leave the base register untouched
158 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
160 /* Load multiple increment after
162 * List: for each bit in list: store register
163 * S: in priviledged mode: store user-mode registers
164 * W=1: update the base register. W=0: leave the base register untouched
166 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
169 #define ARMV4_5_NOP (0xe1a08008)
171 /* Move PSR to general purpose register
172 * R=1: SPSR R=0: CPSR
173 * Rn: target register
175 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
178 * Rd: register to store
181 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
184 * Rd: register to load
187 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
189 /* Move general purpose register to PSR
190 * R=1: SPSR R=0: CPSR
192 * 1: control field 2: extension field 4: status field 8: flags field
193 * Rm: source register
195 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
196 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
198 /* Load Register Halfword Immediate Post-Index
199 * Rd: register to load
202 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
204 /* Load Register Byte Immediate Post-Index
205 * Rd: register to load
208 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
210 /* Store register Halfword Immediate Post-Index
211 * Rd: register to store
214 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
216 /* Store register Byte Immediate Post-Index
217 * Rd: register to store
220 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
223 * Im: Branch target (left-shifted by 2 bits, added to PC)
224 * L: 1: branch and link 0: branch only
226 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
228 /* Branch and exchange (ARM state)
229 * Rm: register holding branch target address
231 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
233 /* Move to ARM register from coprocessor
234 * CP: Coprocessor number
235 * op1: Coprocessor opcode
236 * Rd: destination register
237 * CRn: first coprocessor operand
238 * CRm: second coprocessor operand
239 * op2: Second coprocessor opcode
241 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
243 /* Move to coprocessor from ARM register
244 * CP: Coprocessor number
245 * op1: Coprocessor opcode
246 * Rd: destination register
247 * CRn: first coprocessor operand
248 * CRm: second coprocessor operand
249 * op2: Second coprocessor opcode
251 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
253 /* Breakpoint instruction (ARMv5)
254 * Im: 16-bit immediate
256 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
259 /* Thumb mode instructions
262 /* Store register (Thumb mode)
263 * Rd: source register
266 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
268 /* Load register (Thumb state)
269 * Rd: destination register
272 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
274 /* Load multiple (Thumb state)
276 * List: for each bit in list: store register
278 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
280 /* Load register with PC relative addressing
281 * Rd: register to load
283 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
285 /* Move hi register (Thumb mode)
286 * Rd: destination register
287 * Rm: source register
289 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
291 /* No operation (Thumb mode)
293 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
295 /* Move immediate to register (Thumb state)
296 * Rd: destination register
297 * Im: 8-bit immediate value
299 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
301 /* Branch and Exchange
302 * Rm: register containing branch target
304 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
306 /* Branch (Thumb state)
309 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
311 /* Breakpoint instruction (ARMv5) (Thumb state)
312 * Im: 8-bit immediate
314 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
316 #endif /* ARMV4_5_H */