1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
33 typedef enum armv4_5_mode
35 ARMV4_5_MODE_USR = 16,
36 ARMV4_5_MODE_FIQ = 17,
37 ARMV4_5_MODE_IRQ = 18,
38 ARMV4_5_MODE_SVC = 19,
39 ARMV4_5_MODE_ABT = 23,
41 ARMV4_5_MODE_UND = 27,
42 ARMV4_5_MODE_SYS = 31,
46 const char *arm_mode_name(unsigned psr_mode);
47 bool is_arm_mode(unsigned psr_mode);
49 int armv4_5_mode_to_number(enum armv4_5_mode mode);
50 enum armv4_5_mode armv4_5_number_to_mode(int number);
52 typedef enum armv4_5_state
56 ARMV4_5_STATE_JAZELLE,
60 extern char* armv4_5_state_strings[];
62 extern const int armv4_5_core_reg_map[8][17];
64 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
65 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
67 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
68 enum { ARMV4_5_CPSR = 31, };
70 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
73 * Represents a generic ARM core, with standard application registers.
75 * There are sixteen application registers (including PC, SP, LR) and a PSR.
76 * Cortex-M series cores do not support as many core states or shadowed
77 * registers as traditional ARM cores, and only support Thumb2 instructions.
82 struct reg_cache *core_cache;
84 /** Handle to the CPSR; valid in all core modes. */
87 /** Handle to the SPSR; valid only in core modes with an SPSR. */
93 * Indicates what registers are in the ARM state core register set.
94 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
95 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
96 * more registers are shadowed, for "Secure Monitor" mode.
98 enum armv4_5_mode core_type;
100 enum armv4_5_mode core_mode;
101 enum armv4_5_state core_state;
103 /** Flag reporting unavailability of the BKPT instruction. */
106 /** Backpointer to the target. */
107 struct target *target;
109 /** Handle for the debug module, if one is present. */
112 /** Handle for the Embedded Trace Module, if one is present. */
113 struct etm_context *etm;
115 int (*full_context)(struct target *target);
116 int (*read_core_reg)(struct target *target, struct reg *reg,
117 int num, enum armv4_5_mode mode);
118 int (*write_core_reg)(struct target *target, struct reg *reg,
119 int num, enum armv4_5_mode mode, uint32_t value);
123 #define target_to_armv4_5 target_to_arm
125 /** Convert target handle to generic ARM target state handle. */
126 static inline struct arm *target_to_arm(struct target *target)
128 return target->arch_info;
131 static inline bool is_arm(struct arm *arm)
133 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
136 struct armv4_5_algorithm
140 enum armv4_5_mode core_mode;
141 enum armv4_5_state core_state;
147 enum armv4_5_mode mode;
148 struct target *target;
149 struct arm *armv4_5_common;
153 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
154 struct arm *armv4_5_common);
156 int armv4_5_arch_state(struct target *target);
157 int armv4_5_get_gdb_reg_list(struct target *target,
158 struct reg **reg_list[], int *reg_list_size);
160 extern const struct command_registration arm_command_handlers[];
162 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
164 int armv4_5_run_algorithm(struct target *target,
165 int num_mem_params, struct mem_param *mem_params,
166 int num_reg_params, struct reg_param *reg_params,
167 uint32_t entry_point, uint32_t exit_point,
168 int timeout_ms, void *arch_info);
170 int arm_checksum_memory(struct target *target,
171 uint32_t address, uint32_t count, uint32_t *checksum);
172 int arm_blank_check_memory(struct target *target,
173 uint32_t address, uint32_t count, uint32_t *blank);
175 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
176 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
178 extern struct reg arm_gdb_dummy_fp_reg;
179 extern struct reg arm_gdb_dummy_fps_reg;
181 /* ARM mode instructions
184 /* Store multiple increment after
186 * List: for each bit in list: store register
187 * S: in priviledged mode: store user-mode registers
188 * W = 1: update the base register. W = 0: leave the base register untouched
190 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
192 /* Load multiple increment after
194 * List: for each bit in list: store register
195 * S: in priviledged mode: store user-mode registers
196 * W = 1: update the base register. W = 0: leave the base register untouched
198 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
201 #define ARMV4_5_NOP (0xe1a08008)
203 /* Move PSR to general purpose register
204 * R = 1: SPSR R = 0: CPSR
205 * Rn: target register
207 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
210 * Rd: register to store
213 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
216 * Rd: register to load
219 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
221 /* Move general purpose register to PSR
222 * R = 1: SPSR R = 0: CPSR
224 * 1: control field 2: extension field 4: status field 8: flags field
225 * Rm: source register
227 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
228 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
230 /* Load Register Halfword Immediate Post-Index
231 * Rd: register to load
234 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
236 /* Load Register Byte Immediate Post-Index
237 * Rd: register to load
240 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
242 /* Store register Halfword Immediate Post-Index
243 * Rd: register to store
246 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
248 /* Store register Byte Immediate Post-Index
249 * Rd: register to store
252 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
255 * Im: Branch target (left-shifted by 2 bits, added to PC)
256 * L: 1: branch and link 0: branch only
258 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
260 /* Branch and exchange (ARM state)
261 * Rm: register holding branch target address
263 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
265 /* Move to ARM register from coprocessor
266 * CP: Coprocessor number
267 * op1: Coprocessor opcode
268 * Rd: destination register
269 * CRn: first coprocessor operand
270 * CRm: second coprocessor operand
271 * op2: Second coprocessor opcode
273 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
275 /* Move to coprocessor from ARM register
276 * CP: Coprocessor number
277 * op1: Coprocessor opcode
278 * Rd: destination register
279 * CRn: first coprocessor operand
280 * CRm: second coprocessor operand
281 * op2: Second coprocessor opcode
283 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
285 /* Breakpoint instruction (ARMv5)
286 * Im: 16-bit immediate
288 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
291 /* Thumb mode instructions
294 /* Store register (Thumb mode)
295 * Rd: source register
298 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
300 /* Load register (Thumb state)
301 * Rd: destination register
304 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
306 /* Load multiple (Thumb state)
308 * List: for each bit in list: store register
310 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
312 /* Load register with PC relative addressing
313 * Rd: register to load
315 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
317 /* Move hi register (Thumb mode)
318 * Rd: destination register
319 * Rm: source register
321 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
323 /* No operation (Thumb mode)
325 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
327 /* Move immediate to register (Thumb state)
328 * Rd: destination register
329 * Im: 8-bit immediate value
331 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
333 /* Branch and Exchange
334 * Rm: register containing branch target
336 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
338 /* Branch (Thumb state)
341 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
343 /* Breakpoint instruction (ARMv5) (Thumb state)
344 * Im: 8-bit immediate
346 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
348 /* build basic mrc/mcr opcode */
350 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
360 #endif /* ARMV4_5_H */