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[openocd] / src / target / armv4_5_cache.h
1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifndef ARMV4_5_CACHE_H
21 #define ARMV4_5_CACHE_H
22
23 #include "types.h"
24 #include "command.h"
25
26 typedef struct armv4_5_cachesize_s
27 {
28         int linelen;
29         int associativity;
30         int nsets;
31         int cachesize;
32 } armv4_5_cachesize_t;
33
34 typedef struct armv4_5_cache_common_s
35 {
36         int ctype;      /* specify supported cache operations */
37         int separate;   /* separate caches or unified cache */
38         armv4_5_cachesize_t d_u_size;   /* data cache */
39         armv4_5_cachesize_t i_size; /* instruction cache */
40         int i_cache_enabled;
41         int d_u_cache_enabled;
42 } armv4_5_cache_common_t;
43
44 extern int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache);
45 extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *cache);
46
47 extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
48
49 enum
50 {
51         ARMV4_5_D_U_CACHE_ENABLED = 0x4,
52         ARMV4_5_I_CACHE_ENABLED = 0x1000,
53         ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
54         ARMV4_5_CACHE_RR_BIT = 0x5000,
55 };
56
57 #endif /* ARMV4_5_CACHE_H */