git.sur5r.net Git - openocd/blob - src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/log.h>
  25 #include "target.h"
  26 #include "armv4_5_mmu.h"
  27
  28
  29 int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
  30 {
  31         uint32_t first_lvl_descriptor = 0x0;
  32         uint32_t second_lvl_descriptor = 0x0;
  33         uint32_t ttb;
  34         int retval;
  35         retval = armv4_5_mmu->get_ttb(target, &ttb);
  36         if (retval != ERROR_OK)
  37           return retval;
  38
  39         retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  40                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  41                 4, 1, (uint8_t*)&first_lvl_descriptor);
  42         if (retval != ERROR_OK)
  43           return retval;
  44         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  45
  46         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  47
  48         if ((first_lvl_descriptor & 0x3) == 0)
  49         {
  50                 LOG_ERROR("Address translation failure");
  51                 return ERROR_TARGET_TRANSLATION_FAULT;
  52         }
  53
  54         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  55         {
  56                 LOG_ERROR("Address translation failure");
  57                 return ERROR_TARGET_TRANSLATION_FAULT;
  58         }
  59
  60         if ((first_lvl_descriptor & 0x3) == 2)
  61         {
  62                 /* section descriptor */
  63                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  64                 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  65                 return ERROR_OK;
  66         }
  67
  68         if ((first_lvl_descriptor & 0x3) == 1)
  69         {
  70                 /* coarse page table */
  71                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  72                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  73                         4, 1, (uint8_t*)&second_lvl_descriptor);
  74                 if (retval != ERROR_OK)
  75                         return retval;
  76         }
  77         else if ((first_lvl_descriptor & 0x3) == 3)
  78         {
  79                 /* fine page table */
  80                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  81                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  82                         4, 1, (uint8_t*)&second_lvl_descriptor);
  83                 if (retval != ERROR_OK)
  84                         return retval;
  85         }
  86
  87         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  88
  89         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  90
  91         if ((second_lvl_descriptor & 0x3) == 0)
  92         {
  93                 LOG_ERROR("Address translation failure");
  94                 return ERROR_TARGET_TRANSLATION_FAULT;
  95         }
  96
  97         /* cacheable/bufferable is always specified in bits 3-2 */
  98         *cb = (second_lvl_descriptor & 0xc) >> 2;
  99
 100         if ((second_lvl_descriptor & 0x3) == 1)
 101         {
 102                 /* large page descriptor */
 103                 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 104                 return ERROR_OK;
 105         }
 106
 107         if ((second_lvl_descriptor & 0x3) == 2)
 108         {
 109                 /* small page descriptor */
 110                 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 111                 return ERROR_OK;
 112         }
 113
 114         if ((second_lvl_descriptor & 0x3) == 3)
 115         {
 116                 /* tiny page descriptor */
 117                 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 118                 return ERROR_OK;
 119         }
 120
 121         /* should not happen */
 122         LOG_ERROR("Address translation failure");
 123         return ERROR_TARGET_TRANSLATION_FAULT;
 124 }
 125
 126 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 127 {
 128         int retval;
 129
 130         if (target->state != TARGET_HALTED)
 131                 return ERROR_TARGET_NOT_HALTED;
 132
 133         /* disable MMU and data (or unified) cache */
 134         retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 135         if (retval !=ERROR_OK)
 136                 return retval;
 137
 138         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 139         if (retval !=ERROR_OK)
 140                 return retval;
 141
 142         /* reenable MMU / cache */
 143         retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 144                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 145                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 146         if (retval !=ERROR_OK)
 147                 return retval;
 148
 149         return retval;
 150 }
 151
 152 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 153 {
 154         int retval;
 155
 156         if (target->state != TARGET_HALTED)
 157                 return ERROR_TARGET_NOT_HALTED;
 158
 159         /* disable MMU and data (or unified) cache */
 160         retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 161         if (retval !=ERROR_OK)
 162                 return retval;
 163
 164         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 165         if (retval !=ERROR_OK)
 166                 return retval;
 167
 168         /* reenable MMU / cache */
 169         retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 170                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 171                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 172         if (retval !=ERROR_OK)
 173                 return retval;
 174
 175         return retval;
 176 }