git.sur5r.net Git - openocd/blob - src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/log.h>
  25 #include "target.h"
  26 #include "armv4_5_mmu.h"
  27
  28
  29 uint32_t armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
  30 {
  31         uint32_t first_lvl_descriptor = 0x0;
  32         uint32_t second_lvl_descriptor = 0x0;
  33         uint32_t ttb = armv4_5_mmu->get_ttb(target);
  34
  35         armv4_5_mmu_read_physical(target, armv4_5_mmu,
  36                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  37                 4, 1, (uint8_t*)&first_lvl_descriptor);
  38         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  39
  40         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  41
  42         if ((first_lvl_descriptor & 0x3) == 0)
  43         {
  44                 *type = -1;
  45                 LOG_ERROR("Address translation failure");
  46                 return ERROR_TARGET_TRANSLATION_FAULT;
  47         }
  48
  49         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  50         {
  51                 *type = -1;
  52                 LOG_ERROR("Address translation failure");
  53                 return ERROR_TARGET_TRANSLATION_FAULT;
  54         }
  55
  56         /* domain is always specified in bits 8-5 */
  57         *domain = (first_lvl_descriptor & 0x1e0) >> 5;
  58
  59         if ((first_lvl_descriptor & 0x3) == 2)
  60         {
  61                 /* section descriptor */
  62                 *type = ARMV4_5_SECTION;
  63                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  64                 *ap = (first_lvl_descriptor & 0xc00) >> 10;
  65                 return (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  66         }
  67
  68         if ((first_lvl_descriptor & 0x3) == 1)
  69         {
  70                 /* coarse page table */
  71                 armv4_5_mmu_read_physical(target, armv4_5_mmu,
  72                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  73                         4, 1, (uint8_t*)&second_lvl_descriptor);
  74         }
  75         else if ((first_lvl_descriptor & 0x3) == 3)
  76         {
  77                 /* fine page table */
  78                 armv4_5_mmu_read_physical(target, armv4_5_mmu,
  79                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  80                         4, 1, (uint8_t*)&second_lvl_descriptor);
  81         }
  82
  83         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  84
  85         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  86
  87         if ((second_lvl_descriptor & 0x3) == 0)
  88         {
  89                 *type = -1;
  90                 LOG_ERROR("Address translation failure");
  91                 return ERROR_TARGET_TRANSLATION_FAULT;
  92         }
  93
  94         /* cacheable/bufferable is always specified in bits 3-2 */
  95         *cb = (second_lvl_descriptor & 0xc) >> 2;
  96
  97         if ((second_lvl_descriptor & 0x3) == 1)
  98         {
  99                 /* large page descriptor */
 100                 *type = ARMV4_5_LARGE_PAGE;
 101                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 102                 return (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 103         }
 104
 105         if ((second_lvl_descriptor & 0x3) == 2)
 106         {
 107                 /* small page descriptor */
 108                 *type = ARMV4_5_SMALL_PAGE;
 109                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 110                 return (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 111         }
 112
 113         if ((second_lvl_descriptor & 0x3) == 3)
 114         {
 115                 /* tiny page descriptor */
 116                 *type = ARMV4_5_TINY_PAGE;
 117                 *ap = (second_lvl_descriptor & 0x30) >> 4;
 118                 return (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 119         }
 120
 121         /* should not happen */
 122         *type = -1;
 123         LOG_ERROR("Address translation failure");
 124         return ERROR_TARGET_TRANSLATION_FAULT;
 125 }
 126
 127 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 128 {
 129         int retval;
 130
 131         if (target->state != TARGET_HALTED)
 132                 return ERROR_TARGET_NOT_HALTED;
 133
 134         /* disable MMU and data (or unified) cache */
 135         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 136
 137         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 138
 139         /* reenable MMU / cache */
 140         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 141                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 142                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 143
 144         return retval;
 145 }
 146
 147 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 148 {
 149         int retval;
 150
 151         if (target->state != TARGET_HALTED)
 152                 return ERROR_TARGET_NOT_HALTED;
 153
 154         /* disable MMU and data (or unified) cache */
 155         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 156
 157         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 158
 159         /* reenable MMU / cache */
 160         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 161                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 162                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 163
 164         return retval;
 165 }