git.sur5r.net Git - openocd/blob - src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "log.h"
  25 #include "armv4_5_mmu.h"
  26
  27
  28 uint32_t armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
  29
  30 char* armv4_5_mmu_page_type_names[] =
  31 {
  32         "section", "large page", "small page", "tiny page"
  33 };
  34
  35 uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
  36 {
  37         uint32_t first_lvl_descriptor = 0x0;
  38         uint32_t second_lvl_descriptor = 0x0;
  39         uint32_t ttb = armv4_5_mmu->get_ttb(target);
  40
  41         armv4_5_mmu_read_physical(target, armv4_5_mmu,
  42                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  43                 4, 1, (uint8_t*)&first_lvl_descriptor);
  44         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  45
  46         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  47
  48         if ((first_lvl_descriptor & 0x3) == 0)
  49         {
  50                 *type = -1;
  51                 LOG_ERROR("Address translation failure");
  52                 return ERROR_TARGET_TRANSLATION_FAULT;
  53         }
  54
  55         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  56         {
  57                 *type = -1;
  58                 LOG_ERROR("Address translation failure");
  59                 return ERROR_TARGET_TRANSLATION_FAULT;
  60         }
  61
  62         /* domain is always specified in bits 8-5 */
  63         *domain = (first_lvl_descriptor & 0x1e0) >> 5;
  64
  65         if ((first_lvl_descriptor & 0x3) == 2)
  66         {
  67                 /* section descriptor */
  68                 *type = ARMV4_5_SECTION;
  69                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  70                 *ap = (first_lvl_descriptor & 0xc00) >> 10;
  71                 return (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  72         }
  73
  74         if ((first_lvl_descriptor & 0x3) == 1)
  75         {
  76                 /* coarse page table */
  77                 armv4_5_mmu_read_physical(target, armv4_5_mmu,
  78                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  79                         4, 1, (uint8_t*)&second_lvl_descriptor);
  80         }
  81         else if ((first_lvl_descriptor & 0x3) == 3)
  82         {
  83                 /* fine page table */
  84                 armv4_5_mmu_read_physical(target, armv4_5_mmu,
  85                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  86                         4, 1, (uint8_t*)&second_lvl_descriptor);
  87         }
  88
  89         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  90
  91         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  92
  93         if ((second_lvl_descriptor & 0x3) == 0)
  94         {
  95                 *type = -1;
  96                 LOG_ERROR("Address translation failure");
  97                 return ERROR_TARGET_TRANSLATION_FAULT;
  98         }
  99
 100         /* cacheable/bufferable is always specified in bits 3-2 */
 101         *cb = (second_lvl_descriptor & 0xc) >> 2;
 102
 103         if ((second_lvl_descriptor & 0x3) == 1)
 104         {
 105                 /* large page descriptor */
 106                 *type = ARMV4_5_LARGE_PAGE;
 107                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 108                 return (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 109         }
 110
 111         if ((second_lvl_descriptor & 0x3) == 2)
 112         {
 113                 /* small page descriptor */
 114                 *type = ARMV4_5_SMALL_PAGE;
 115                 *ap = (second_lvl_descriptor & 0xff0) >> 4;
 116                 return (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 117         }
 118
 119         if ((second_lvl_descriptor & 0x3) == 3)
 120         {
 121                 /* tiny page descriptor */
 122                 *type = ARMV4_5_TINY_PAGE;
 123                 *ap = (second_lvl_descriptor & 0x30) >> 4;
 124                 return (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 125         }
 126
 127         /* should not happen */
 128         *type = -1;
 129         LOG_ERROR("Address translation failure");
 130         return ERROR_TARGET_TRANSLATION_FAULT;
 131 }
 132
 133 int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 134 {
 135         int retval;
 136
 137         if (target->state != TARGET_HALTED)
 138                 return ERROR_TARGET_NOT_HALTED;
 139
 140         /* disable MMU and data (or unified) cache */
 141         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 142
 143         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 144
 145         /* reenable MMU / cache */
 146         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 147                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 148                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 149
 150         return retval;
 151 }
 152
 153 int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 154 {
 155         int retval;
 156
 157         if (target->state != TARGET_HALTED)
 158                 return ERROR_TARGET_NOT_HALTED;
 159
 160         /* disable MMU and data (or unified) cache */
 161         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 162
 163         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 164
 165         /* reenable MMU / cache */
 166         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 167                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 168                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 169
 170         return retval;
 171 }
 172
 173 int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
 174 {
 175         int count = 1;
 176         int size = 4;
 177         uint32_t address = 0;
 178         int i;
 179
 180         char output[128];
 181         int output_len;
 182
 183         int retval;
 184
 185         uint8_t *buffer;
 186
 187         if (target->state != TARGET_HALTED)
 188         {
 189                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 190                 return ERROR_OK;
 191         }
 192
 193         if (argc < 1)
 194                 return ERROR_OK;
 195
 196         if (argc == 2)
 197                 count = strtoul(args[1], NULL, 0);
 198
 199         address = strtoul(args[0], NULL, 0);
 200
 201         switch (cmd[2])
 202         {
 203                 case 'w':
 204                         size = 4;
 205                         break;
 206                 case 'h':
 207                         size = 2;
 208                         break;
 209                 case 'b':
 210                         size = 1;
 211                         break;
 212                 default:
 213                         return ERROR_OK;
 214         }
 215
 216         buffer = calloc(count, size);
 217         if ((retval  = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK)
 218         {
 219                 switch (retval)
 220                 {
 221                         case ERROR_TARGET_UNALIGNED_ACCESS:
 222                                 command_print(cmd_ctx, "error: address not aligned");
 223                                 break;
 224                         case ERROR_TARGET_NOT_HALTED:
 225                                 command_print(cmd_ctx, "error: target must be halted for memory accesses");
 226                                 break;
 227                         case ERROR_TARGET_DATA_ABORT:
 228                                 command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
 229                                 break;
 230                         default:
 231                                 command_print(cmd_ctx, "error: unknown error");
 232                 }
 233         }
 234
 235         output_len = 0;
 236
 237         for (i = 0; i < count; i++)
 238         {
 239                 if (i%8 == 0)
 240                         output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8" PRIx32 ": ", address + (i*size));
 241
 242                 switch (size)
 243                 {
 244                         case 4:
 245                                 output_len += snprintf(output + output_len, 128 - output_len, "%8.8" PRIx32 " ", target_buffer_get_u32(target, &buffer[i*4]));
 246                                 break;
 247                         case 2:
 248                                 output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));
 249                                 break;
 250                         case 1:
 251                                 output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]);
 252                                 break;
 253                 }
 254
 255                 if ((i % 8 == 7) || (i == count - 1))
 256                 {
 257                         command_print(cmd_ctx, "%s", output);
 258                         output_len = 0;
 259                 }
 260         }
 261
 262         free(buffer);
 263
 264         return ERROR_OK;
 265 }
 266
 267 int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
 268 {
 269         uint32_t address = 0;
 270         uint32_t value = 0;
 271         int retval;
 272         uint8_t value_buf[4];
 273
 274         if (target->state != TARGET_HALTED)
 275         {
 276                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 277                 return ERROR_OK;
 278         }
 279
 280         if (argc < 2)
 281                 return ERROR_OK;
 282
 283         address = strtoul(args[0], NULL, 0);
 284         value = strtoul(args[1], NULL, 0);
 285
 286         switch (cmd[2])
 287         {
 288                 case 'w':
 289                         target_buffer_set_u32(target, value_buf, value);
 290                         retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf);
 291                         break;
 292                 case 'h':
 293                         target_buffer_set_u16(target, value_buf, value);
 294                         retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf);
 295                         break;
 296                 case 'b':
 297                         value_buf[0] = value;
 298                         retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf);
 299                         break;
 300                 default:
 301                         return ERROR_OK;
 302         }
 303
 304         switch (retval)
 305         {
 306                 case ERROR_TARGET_UNALIGNED_ACCESS:
 307                         command_print(cmd_ctx, "error: address not aligned");
 308                         break;
 309                 case ERROR_TARGET_DATA_ABORT:
 310                         command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
 311                         break;
 312                 case ERROR_TARGET_NOT_HALTED:
 313                         command_print(cmd_ctx, "error: target must be halted for memory accesses");
 314                         break;
 315                 case ERROR_OK:
 316                         break;
 317                 default:
 318                         command_print(cmd_ctx, "error: unknown error");
 319         }
 320
 321         return ERROR_OK;
 322 }