git.sur5r.net Git - openocd/blob - src/target/armv4_5_mmu.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/log.h>
  25 #include "target.h"
  26 #include "armv4_5_mmu.h"
  27
  28
  29 int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
  30 {
  31         uint32_t first_lvl_descriptor = 0x0;
  32         uint32_t second_lvl_descriptor = 0x0;
  33         uint32_t ttb = armv4_5_mmu->get_ttb(target);
  34         int retval;
  35
  36         retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  37                 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
  38                 4, 1, (uint8_t*)&first_lvl_descriptor);
  39         if (retval != ERROR_OK)
  40           return retval;
  41         first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
  42
  43         LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
  44
  45         if ((first_lvl_descriptor & 0x3) == 0)
  46         {
  47                 LOG_ERROR("Address translation failure");
  48                 return ERROR_TARGET_TRANSLATION_FAULT;
  49         }
  50
  51         if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
  52         {
  53                 LOG_ERROR("Address translation failure");
  54                 return ERROR_TARGET_TRANSLATION_FAULT;
  55         }
  56
  57         if ((first_lvl_descriptor & 0x3) == 2)
  58         {
  59                 /* section descriptor */
  60                 *cb = (first_lvl_descriptor & 0xc) >> 2;
  61                 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
  62                 return ERROR_OK;
  63         }
  64
  65         if ((first_lvl_descriptor & 0x3) == 1)
  66         {
  67                 /* coarse page table */
  68                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  69                         (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
  70                         4, 1, (uint8_t*)&second_lvl_descriptor);
  71                 if (retval != ERROR_OK)
  72                         return retval;
  73         }
  74         else if ((first_lvl_descriptor & 0x3) == 3)
  75         {
  76                 /* fine page table */
  77                 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
  78                         (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
  79                         4, 1, (uint8_t*)&second_lvl_descriptor);
  80                 if (retval != ERROR_OK)
  81                         return retval;
  82         }
  83
  84         second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
  85
  86         LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
  87
  88         if ((second_lvl_descriptor & 0x3) == 0)
  89         {
  90                 LOG_ERROR("Address translation failure");
  91                 return ERROR_TARGET_TRANSLATION_FAULT;
  92         }
  93
  94         /* cacheable/bufferable is always specified in bits 3-2 */
  95         *cb = (second_lvl_descriptor & 0xc) >> 2;
  96
  97         if ((second_lvl_descriptor & 0x3) == 1)
  98         {
  99                 /* large page descriptor */
 100                 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 101                 return ERROR_OK;
 102         }
 103
 104         if ((second_lvl_descriptor & 0x3) == 2)
 105         {
 106                 /* small page descriptor */
 107                 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 108                 return ERROR_OK;
 109         }
 110
 111         if ((second_lvl_descriptor & 0x3) == 3)
 112         {
 113                 /* tiny page descriptor */
 114                 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 115                 return ERROR_OK;
 116         }
 117
 118         /* should not happen */
 119         LOG_ERROR("Address translation failure");
 120         return ERROR_TARGET_TRANSLATION_FAULT;
 121 }
 122
 123 int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 124 {
 125         int retval;
 126
 127         if (target->state != TARGET_HALTED)
 128                 return ERROR_TARGET_NOT_HALTED;
 129
 130         /* disable MMU and data (or unified) cache */
 131         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 132
 133         retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
 134
 135         /* reenable MMU / cache */
 136         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 137                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 138                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 139
 140         return retval;
 141 }
 142
 143 int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 144 {
 145         int retval;
 146
 147         if (target->state != TARGET_HALTED)
 148                 return ERROR_TARGET_NOT_HALTED;
 149
 150         /* disable MMU and data (or unified) cache */
 151         armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
 152
 153         retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
 154
 155         /* reenable MMU / cache */
 156         armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 157                 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 158                 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
 159
 160         return retval;
 161 }