git.sur5r.net Git - openocd/blob - src/target/armv4_5_mmu.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifndef ARMV4_5_MMU_H
  21 #define ARMV4_5_MMU_H
  22
  23 #include "armv4_5_cache.h"
  24
  25 typedef struct armv4_5_mmu_common_s
  26 {
  27         u32 (*get_ttb)(target_t *target);
  28         int (*read_memory)(target_t *target, u32 address, u32 size, u32 count, u8 *buffer);
  29         int (*write_memory)(target_t *target, u32 address, u32 size, u32 count, u8 *buffer);
  30         void (*disable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
  31         void (*enable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
  32         armv4_5_cache_common_t armv4_5_cache;
  33         int has_tiny_pages;
  34         int mmu_enabled;
  35 } armv4_5_mmu_common_t;
  36
  37 enum
  38 {
  39         ARMV4_5_SECTION, ARMV4_5_LARGE_PAGE, ARMV4_5_SMALL_PAGE, ARMV4_5_TINY_PAGE
  40 };
  41
  42 extern char* armv4_5_page_type_names[];
  43
  44 extern u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap);
  45 extern int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
  46 extern int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
  47
  48 extern int armv4_5_mmu_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
  49 extern int armv4_5_mmu_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
  50 extern int armv4_5_mmu_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
  51
  52 enum
  53 {
  54         ARMV4_5_MMU_ENABLED = 0x1,
  55         ARMV4_5_ALIGNMENT_CHECK = 0x2,
  56         ARMV4_5_MMU_S_BIT = 0x100,
  57         ARMV4_5_MMU_R_BIT = 0x200
  58 };
  59
  60 #endif /* ARMV4_5_MMU_H */