git.sur5r.net Git - openocd/blob - src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual               *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "breakpoints.h"
  38 #include "armv7m.h"
  39 #include "algorithm.h"
  40 #include "register.h"
  41
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
  48 char *armv7m_mode_strings[] =
  49 {
  50         "Thread", "Thread (User)", "Handler",
  51 };
  52
  53 static char *armv7m_exception_strings[] =
  54 {
  55         "", "Reset", "NMI", "HardFault",
  56         "MemManage", "BusFault", "UsageFault", "RESERVED",
  57         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  58         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  59 };
  60
  61 #ifdef ARMV7_GDB_HACKS
  62 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  63
  64 struct reg armv7m_gdb_dummy_cpsr_reg =
  65 {
  66         .name = "GDB dummy cpsr register",
  67         .value = armv7m_gdb_dummy_cpsr_value,
  68         .dirty = 0,
  69         .valid = 1,
  70         .size = 32,
  71         .arch_info = NULL,
  72 };
  73 #endif
  74
  75 /*
  76  * These registers are not memory-mapped.  The ARMv7-M profile includes
  77  * memory mapped registers too, such as for the NVIC (interrupt controller)
  78  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  79  *
  80  * The ARMv6-M profile is almost identical in this respect, except that it
  81  * doesn't include basepri or faultmask registers.
  82  */
  83 static const struct {
  84         unsigned id;
  85         const char *name;
  86         unsigned bits;
  87 } armv7m_regs[] = {
  88         { ARMV7M_R0, "r0", 32 },
  89         { ARMV7M_R1, "r1", 32 },
  90         { ARMV7M_R2, "r2", 32 },
  91         { ARMV7M_R3, "r3", 32 },
  92
  93         { ARMV7M_R4, "r4", 32 },
  94         { ARMV7M_R5, "r5", 32 },
  95         { ARMV7M_R6, "r6", 32 },
  96         { ARMV7M_R7, "r7", 32 },
  97
  98         { ARMV7M_R8, "r8", 32 },
  99         { ARMV7M_R9, "r9", 32 },
 100         { ARMV7M_R10, "r10", 32 },
 101         { ARMV7M_R11, "r11", 32 },
 102
 103         { ARMV7M_R12, "r12", 32 },
 104         { ARMV7M_R13, "sp", 32 },
 105         { ARMV7M_R14, "lr", 32 },
 106         { ARMV7M_PC, "pc", 32 },
 107
 108         { ARMV7M_xPSR, "xPSR", 32 },
 109         { ARMV7M_MSP, "msp", 32 },
 110         { ARMV7M_PSP, "psp", 32 },
 111
 112         { ARMV7M_PRIMASK, "primask", 1 },
 113         { ARMV7M_BASEPRI, "basepri", 8 },
 114         { ARMV7M_FAULTMASK, "faultmask", 1 },
 115         { ARMV7M_CONTROL, "control", 2 },
 116 };
 117
 118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 119
 120 /**
 121  * Restores target context using the cache of core registers set up
 122  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 123  */
 124 int armv7m_restore_context(struct target *target)
 125 {
 126         int i;
 127         struct armv7m_common *armv7m = target_to_armv7m(target);
 128
 129         LOG_DEBUG(" ");
 130
 131         if (armv7m->pre_restore_context)
 132                 armv7m->pre_restore_context(target);
 133
 134         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 135         {
 136                 if (armv7m->core_cache->reg_list[i].dirty)
 137                 {
 138                         armv7m->write_core_reg(target, i);
 139                 }
 140         }
 141
 142         return ERROR_OK;
 143 }
 144
 145 /* Core state functions */
 146
 147 /**
 148  * Maps ISR number (from xPSR) to name.
 149  * Note that while names and meanings for the first sixteen are standardized
 150  * (with zero not a true exception), external interrupts are only numbered.
 151  * They are assigned by vendors, which generally assign different numbers to
 152  * peripherals (such as UART0 or a USB peripheral controller).
 153  */
 154 char *armv7m_exception_string(int number)
 155 {
 156         static char enamebuf[32];
 157
 158         if ((number < 0) | (number > 511))
 159                 return "Invalid exception";
 160         if (number < 16)
 161                 return armv7m_exception_strings[number];
 162         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 163         return enamebuf;
 164 }
 165
 166 static int armv7m_get_core_reg(struct reg *reg)
 167 {
 168         int retval;
 169         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 170         struct target *target = armv7m_reg->target;
 171         struct armv7m_common *armv7m = target_to_armv7m(target);
 172
 173         if (target->state != TARGET_HALTED)
 174         {
 175                 return ERROR_TARGET_NOT_HALTED;
 176         }
 177
 178         retval = armv7m->read_core_reg(target, armv7m_reg->num);
 179
 180         return retval;
 181 }
 182
 183 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 184 {
 185         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 186         struct target *target = armv7m_reg->target;
 187         uint32_t value = buf_get_u32(buf, 0, 32);
 188
 189         if (target->state != TARGET_HALTED)
 190         {
 191                 return ERROR_TARGET_NOT_HALTED;
 192         }
 193
 194         buf_set_u32(reg->value, 0, 32, value);
 195         reg->dirty = 1;
 196         reg->valid = 1;
 197
 198         return ERROR_OK;
 199 }
 200
 201 static int armv7m_read_core_reg(struct target *target, unsigned num)
 202 {
 203         uint32_t reg_value;
 204         int retval;
 205         struct armv7m_core_reg * armv7m_core_reg;
 206         struct armv7m_common *armv7m = target_to_armv7m(target);
 207
 208         if (num >= ARMV7M_NUM_REGS)
 209                 return ERROR_INVALID_ARGUMENTS;
 210
 211         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 212         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 213         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 214         armv7m->core_cache->reg_list[num].valid = 1;
 215         armv7m->core_cache->reg_list[num].dirty = 0;
 216
 217         return retval;
 218 }
 219
 220 static int armv7m_write_core_reg(struct target *target, unsigned num)
 221 {
 222         int retval;
 223         uint32_t reg_value;
 224         struct armv7m_core_reg *armv7m_core_reg;
 225         struct armv7m_common *armv7m = target_to_armv7m(target);
 226
 227         if (num >= ARMV7M_NUM_REGS)
 228                 return ERROR_INVALID_ARGUMENTS;
 229
 230         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 231         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 232         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 233         if (retval != ERROR_OK)
 234         {
 235                 LOG_ERROR("JTAG failure");
 236                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 237                 return ERROR_JTAG_DEVICE_ERROR;
 238         }
 239         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 240         armv7m->core_cache->reg_list[num].valid = 1;
 241         armv7m->core_cache->reg_list[num].dirty = 0;
 242
 243         return ERROR_OK;
 244 }
 245
 246 /**
 247  * Returns generic ARM userspace registers to GDB.
 248  * GDB doesn't quite understand that most ARMs don't have floating point
 249  * hardware, so this also fakes a set of long-obsolete FPA registers that
 250  * are not used in EABI based software stacks.
 251  */
 252 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 253 {
 254         struct armv7m_common *armv7m = target_to_armv7m(target);
 255         int i;
 256
 257         *reg_list_size = 26;
 258         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 259
 260         /*
 261          * GDB register packet format for ARM:
 262          *  - the first 16 registers are r0..r15
 263          *  - (obsolete) 8 FPA registers
 264          *  - (obsolete) FPA status
 265          *  - CPSR
 266          */
 267         for (i = 0; i < 16; i++)
 268         {
 269                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 270         }
 271
 272         for (i = 16; i < 24; i++)
 273                 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 274         (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 275
 276 #ifdef ARMV7_GDB_HACKS
 277         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 278         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 279
 280         /* ARMV7M is always in thumb mode, try to make GDB understand this
 281          * if it does not support this arch */
 282         *((char*)armv7m->arm.pc->value) |= 1;
 283 #else
 284         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 285 #endif
 286
 287         return ERROR_OK;
 288 }
 289
 290 /* run to exit point. return error if exit point was not reached. */
 291 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
 292 {
 293         uint32_t pc;
 294         int retval;
 295         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 296          * sequence to write register values to the processor and the read them back */
 297         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 298         {
 299                 return retval;
 300         }
 301
 302         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 303         /* If the target fails to halt due to the breakpoint, force a halt */
 304         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 305         {
 306                 if ((retval = target_halt(target)) != ERROR_OK)
 307                         return retval;
 308                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 309                 {
 310                         return retval;
 311                 }
 312                 return ERROR_TARGET_TIMEOUT;
 313         }
 314
 315         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 316         if (exit_point && (pc != exit_point))
 317         {
 318                 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
 319                 return ERROR_TARGET_TIMEOUT;
 320         }
 321
 322         return ERROR_OK;
 323 }
 324
 325 /** Runs a Thumb algorithm in the target. */
 326 int armv7m_run_algorithm(struct target *target,
 327         int num_mem_params, struct mem_param *mem_params,
 328         int num_reg_params, struct reg_param *reg_params,
 329         uint32_t entry_point, uint32_t exit_point,
 330         int timeout_ms, void *arch_info)
 331 {
 332         struct armv7m_common *armv7m = target_to_armv7m(target);
 333         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 334         enum armv7m_mode core_mode = armv7m->core_mode;
 335         int retval = ERROR_OK;
 336         uint32_t context[ARMV7M_NUM_REGS];
 337
 338         /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
 339          * at the exit point */
 340
 341         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 342         {
 343                 LOG_ERROR("current target isn't an ARMV7M target");
 344                 return ERROR_TARGET_INVALID;
 345         }
 346
 347         if (target->state != TARGET_HALTED)
 348         {
 349                 LOG_WARNING("target not halted");
 350                 return ERROR_TARGET_NOT_HALTED;
 351         }
 352
 353         /* refresh core register cache */
 354         /* Not needed if core register cache is always consistent with target process state */
 355         for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
 356         {
 357                 if (!armv7m->core_cache->reg_list[i].valid)
 358                         armv7m->read_core_reg(target, i);
 359                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 360         }
 361
 362         for (int i = 0; i < num_mem_params; i++)
 363         {
 364                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 365                         return retval;
 366         }
 367
 368         for (int i = 0; i < num_reg_params; i++)
 369         {
 370                 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 371 //              uint32_t regvalue;
 372
 373                 if (!reg)
 374                 {
 375                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 376                         return ERROR_INVALID_ARGUMENTS;
 377                 }
 378
 379                 if (reg->size != reg_params[i].size)
 380                 {
 381                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 382                         return ERROR_INVALID_ARGUMENTS;
 383                 }
 384
 385 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 386                 armv7m_set_core_reg(reg, reg_params[i].value);
 387         }
 388
 389         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 390         {
 391                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 392                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 393                                 0, 1, armv7m_algorithm_info->core_mode);
 394                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 395                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 396         }
 397
 398         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 399
 400         if (retval != ERROR_OK)
 401         {
 402                 return retval;
 403         }
 404
 405         /* Read memory values to mem_params[] */
 406         for (int i = 0; i < num_mem_params; i++)
 407         {
 408                 if (mem_params[i].direction != PARAM_OUT)
 409                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 410                         {
 411                                 return retval;
 412                         }
 413         }
 414
 415         /* Copy core register values to reg_params[] */
 416         for (int i = 0; i < num_reg_params; i++)
 417         {
 418                 if (reg_params[i].direction != PARAM_OUT)
 419                 {
 420                         struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 421
 422                         if (!reg)
 423                         {
 424                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 425                                 return ERROR_INVALID_ARGUMENTS;
 426                         }
 427
 428                         if (reg->size != reg_params[i].size)
 429                         {
 430                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 431                                 return ERROR_INVALID_ARGUMENTS;
 432                         }
 433
 434                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 435                 }
 436         }
 437
 438         for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 439         {
 440                 uint32_t regvalue;
 441                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 442                 if (regvalue != context[i])
 443                 {
 444                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 445                                 armv7m->core_cache->reg_list[i].name, context[i]);
 446                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 447                                         0, 32, context[i]);
 448                         armv7m->core_cache->reg_list[i].valid = 1;
 449                         armv7m->core_cache->reg_list[i].dirty = 1;
 450                 }
 451         }
 452
 453         armv7m->core_mode = core_mode;
 454
 455         return retval;
 456 }
 457
 458 /** Logs summary of ARMv7-M state for a halted target. */
 459 int armv7m_arch_state(struct target *target)
 460 {
 461         struct armv7m_common *armv7m = target_to_armv7m(target);
 462         struct arm *arm = &armv7m->arm;
 463         uint32_t ctrl, sp;
 464
 465         ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 466         sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 467
 468         LOG_USER("target halted due to %s, current mode: %s %s\n"
 469                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
 470                 debug_reason_name(target),
 471                 armv7m_mode_strings[armv7m->core_mode],
 472                 armv7m_exception_string(armv7m->exception_number),
 473                 buf_get_u32(arm->cpsr->value, 0, 32),
 474                 buf_get_u32(arm->pc->value, 0, 32),
 475                 (ctrl & 0x02) ? 'p' : 'm',
 476                 sp,
 477                 arm->is_semihosting ? ", semihosting" : "");
 478
 479         return ERROR_OK;
 480 }
 481 static const struct reg_arch_type armv7m_reg_type = {
 482         .get = armv7m_get_core_reg,
 483         .set = armv7m_set_core_reg,
 484 };
 485
 486 /** Builds cache of architecturally defined registers.  */
 487 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 488 {
 489         struct armv7m_common *armv7m = target_to_armv7m(target);
 490         struct arm *arm = &armv7m->arm;
 491         int num_regs = ARMV7M_NUM_REGS;
 492         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 493         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 494         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 495         struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 496         int i;
 497
 498 #ifdef ARMV7_GDB_HACKS
 499         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 500 #endif
 501
 502         /* Build the process context cache */
 503         cache->name = "arm v7m registers";
 504         cache->next = NULL;
 505         cache->reg_list = reg_list;
 506         cache->num_regs = num_regs;
 507         (*cache_p) = cache;
 508         armv7m->core_cache = cache;
 509
 510         for (i = 0; i < num_regs; i++)
 511         {
 512                 arch_info[i].num = armv7m_regs[i].id;
 513                 arch_info[i].target = target;
 514                 arch_info[i].armv7m_common = armv7m;
 515                 reg_list[i].name = armv7m_regs[i].name;
 516                 reg_list[i].size = armv7m_regs[i].bits;
 517                 reg_list[i].value = calloc(1, 4);
 518                 reg_list[i].dirty = 0;
 519                 reg_list[i].valid = 0;
 520                 reg_list[i].type = &armv7m_reg_type;
 521                 reg_list[i].arch_info = &arch_info[i];
 522         }
 523
 524         arm->cpsr = reg_list + ARMV7M_xPSR;
 525         arm->pc = reg_list + ARMV7M_PC;
 526         arm->core_cache = cache;
 527         return cache;
 528 }
 529
 530 static int armv7m_setup_semihosting(struct target *target, int enable)
 531 {
 532         /* nothing todo for armv7m */
 533         return ERROR_OK;
 534 }
 535
 536 /** Sets up target as a generic ARMv7-M core */
 537 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 538 {
 539         struct arm *arm = &armv7m->arm;
 540
 541         armv7m->common_magic = ARMV7M_COMMON_MAGIC;
 542
 543         arm->core_type = ARM_MODE_THREAD;
 544         arm->arch_info = armv7m;
 545         arm->setup_semihosting = armv7m_setup_semihosting;
 546
 547         /* FIXME remove v7m-specific r/w core_reg functions;
 548          * use the generic ARM core support..
 549          */
 550         armv7m->read_core_reg = armv7m_read_core_reg;
 551         armv7m->write_core_reg = armv7m_write_core_reg;
 552
 553         return arm_init_arch_info(target, arm);
 554 }
 555
 556 /** Generates a CRC32 checksum of a memory region. */
 557 int armv7m_checksum_memory(struct target *target,
 558                 uint32_t address, uint32_t count, uint32_t* checksum)
 559 {
 560         struct working_area *crc_algorithm;
 561         struct armv7m_algorithm armv7m_info;
 562         struct reg_param reg_params[2];
 563         int retval;
 564
 565         /* see contib/loaders/checksum/armv7m_crc.s for src */
 566
 567         static const uint16_t cortex_m3_crc_code[] = {
 568                 0x4602,                                 /* mov  r2, r0 */
 569                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 570                 0x460B,                                 /* mov  r3, r1 */
 571                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 572                 0xE013,                                 /* b    ncomp */
 573                                                                 /* nbyte: */
 574                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 575                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 576                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 577
 578                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 579                                                                 /* loop: */
 580                 0x2800,                                 /* cmp          r0, #0 */
 581                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 582                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 583                 0x4630,                                 /* mov          r0, r6 */
 584                 0xBFB8,                                 /* it           lt */
 585                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 586                 0x2D08,                                 /* cmp          r5, #8 */
 587                 0xD1F4,                                 /* bne          loop */
 588
 589                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 590                                                                 /* ncomp: */
 591                 0x429C,                                 /* cmp  r4, r3 */
 592                 0xD1E9,                                 /* bne  nbyte */
 593                 0xBE00,                         /* bkpt #0 */
 594                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 595         };
 596
 597         uint32_t i;
 598
 599         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 600         {
 601                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 602         }
 603
 604         /* convert flash writing code into a buffer in target endianness */
 605         for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++)
 606                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 607                 {
 608                         return retval;
 609                 }
 610
 611         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 612         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 613
 614         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 615         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 616
 617         buf_set_u32(reg_params[0].value, 0, 32, address);
 618         buf_set_u32(reg_params[1].value, 0, 32, count);
 619
 620         int timeout = 20000 * (1 + (count / (1024 * 1024)));
 621
 622         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 623                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), timeout, &armv7m_info)) != ERROR_OK)
 624         {
 625                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 626                 destroy_reg_param(&reg_params[0]);
 627                 destroy_reg_param(&reg_params[1]);
 628                 target_free_working_area(target, crc_algorithm);
 629                 return retval;
 630         }
 631
 632         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 633
 634         destroy_reg_param(&reg_params[0]);
 635         destroy_reg_param(&reg_params[1]);
 636
 637         target_free_working_area(target, crc_algorithm);
 638
 639         return ERROR_OK;
 640 }
 641
 642 /** Checks whether a memory region is zeroed. */
 643 int armv7m_blank_check_memory(struct target *target,
 644                 uint32_t address, uint32_t count, uint32_t* blank)
 645 {
 646         struct working_area *erase_check_algorithm;
 647         struct reg_param reg_params[3];
 648         struct armv7m_algorithm armv7m_info;
 649         int retval;
 650         uint32_t i;
 651
 652         static const uint16_t erase_check_code[] =
 653         {
 654                 /* loop: */
 655                 0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
 656                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 657                 0x3901,                         /* subs r1, r1, #1 */
 658                 0xD1F9,                         /* bne  loop */
 659                 0xBE00,                 /* bkpt #0 */
 660         };
 661
 662         /* make sure we have a working area */
 663         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 664         {
 665                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 666         }
 667
 668         /* convert flash writing code into a buffer in target endianness */
 669         for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
 670                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 671
 672         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 673         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 674
 675         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 676         buf_set_u32(reg_params[0].value, 0, 32, address);
 677
 678         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 679         buf_set_u32(reg_params[1].value, 0, 32, count);
 680
 681         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 682         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 683
 684         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 685                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 686         {
 687                 destroy_reg_param(&reg_params[0]);
 688                 destroy_reg_param(&reg_params[1]);
 689                 destroy_reg_param(&reg_params[2]);
 690                 target_free_working_area(target, erase_check_algorithm);
 691                 return 0;
 692         }
 693
 694         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 695
 696         destroy_reg_param(&reg_params[0]);
 697         destroy_reg_param(&reg_params[1]);
 698         destroy_reg_param(&reg_params[2]);
 699
 700         target_free_working_area(target, erase_check_algorithm);
 701
 702         return ERROR_OK;
 703 }
 704
 705 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 706 {
 707         struct armv7m_common *armv7m = target_to_armv7m(target);
 708         struct reg *r = armv7m->arm.pc;
 709         bool result = false;
 710
 711
 712         /* if we halted last time due to a bkpt instruction
 713          * then we have to manually step over it, otherwise
 714          * the core will break again */
 715
 716         if (target->debug_reason == DBG_REASON_BREAKPOINT)
 717         {
 718                 uint16_t op;
 719                 uint32_t pc = buf_get_u32(r->value, 0, 32);
 720
 721                 pc &= ~1;
 722                 if (target_read_u16(target, pc, &op) == ERROR_OK)
 723                 {
 724                         if ((op & 0xFF00) == 0xBE00)
 725                         {
 726                                 pc = buf_get_u32(r->value, 0, 32) + 2;
 727                                 buf_set_u32(r->value, 0, 32, pc);
 728                                 r->dirty = true;
 729                                 r->valid = true;
 730                                 result = true;
 731                                 LOG_DEBUG("Skipping over BKPT instruction");
 732                         }
 733                 }
 734         }
 735
 736         if (inst_found) {
 737                 *inst_found = result;
 738         }
 739
 740         return ERROR_OK;
 741 }
 742
 743 const struct command_registration armv7m_command_handlers[] = {
 744         {
 745                 .chain = arm_command_handlers,
 746         },
 747         {
 748                 .chain = dap_command_handlers,
 749         },
 750         COMMAND_REGISTRATION_DONE
 751 };