git.sur5r.net Git - openocd/blob - src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual           *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "armv7m.h"
  38
  39
  40 #if 0
  41 #define _DEBUG_INSTRUCTION_EXECUTION_
  42 #endif
  43
  44 char* armv7m_mode_strings[] =
  45 {
  46         "Thread", "Thread (User)", "Handler",
  47 };
  48
  49 char* armv7m_exception_strings[] =
  50 {
  51         "", "Reset", "NMI", "HardFault",
  52         "MemManage", "BusFault", "UsageFault", "RESERVED",
  53         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  54         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  55 };
  56
  57 char* armv7m_core_reg_list[] =
  58 {
  59         /* Registers accessed through core debug */
  60         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  61         "sp", "lr", "pc",
  62         "xPSR", "msp", "psp",
  63         /* Registers accessed through special reg 20 */
  64         "primask", "basepri", "faultmask", "control"
  65 };
  66
  67 uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  68
  69 reg_t armv7m_gdb_dummy_fp_reg =
  70 {
  71         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  72 };
  73
  74 uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  75
  76 reg_t armv7m_gdb_dummy_fps_reg =
  77 {
  78         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  79 };
  80
  81 #ifdef ARMV7_GDB_HACKS
  82 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  83
  84 reg_t armv7m_gdb_dummy_cpsr_reg =
  85 {
  86         "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  87 };
  88 #endif
  89
  90 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  91 {
  92         /*  CORE_GP are accesible using the core debug registers */
  93         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 107         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 108         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 109
 110         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 111         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 112         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 113
 114         /*  CORE_SP are accesible using coreregister 20 */
 115         {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 116         {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 117         {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 118         {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 119 };
 120
 121 int armv7m_core_reg_arch_type = -1;
 122 int armv7m_dummy_core_reg_arch_type = -1;
 123
 124 int armv7m_restore_context(target_t *target)
 125 {
 126         int i;
 127
 128         /* get pointers to arch-specific information */
 129         armv7m_common_t *armv7m = target->arch_info;
 130
 131         LOG_DEBUG(" ");
 132
 133         if (armv7m->pre_restore_context)
 134                 armv7m->pre_restore_context(target);
 135
 136         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 137         {
 138                 if (armv7m->core_cache->reg_list[i].dirty)
 139                 {
 140                         armv7m->write_core_reg(target, i);
 141                 }
 142         }
 143
 144         if (armv7m->post_restore_context)
 145                 armv7m->post_restore_context(target);
 146
 147         return ERROR_OK;
 148 }
 149
 150 /* Core state functions */
 151 char *armv7m_exception_string(int number)
 152 {
 153         static char enamebuf[32];
 154
 155         if ((number < 0) | (number > 511))
 156                 return "Invalid exception";
 157         if (number < 16)
 158                 return armv7m_exception_strings[number];
 159         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 160         return enamebuf;
 161 }
 162
 163 int armv7m_get_core_reg(reg_t *reg)
 164 {
 165         int retval;
 166         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 167         target_t *target = armv7m_reg->target;
 168         armv7m_common_t *armv7m_target = target->arch_info;
 169
 170         if (target->state != TARGET_HALTED)
 171         {
 172                 return ERROR_TARGET_NOT_HALTED;
 173         }
 174
 175         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 176
 177         return retval;
 178 }
 179
 180 int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
 181 {
 182         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 183         target_t *target = armv7m_reg->target;
 184         uint32_t value = buf_get_u32(buf, 0, 32);
 185
 186         if (target->state != TARGET_HALTED)
 187         {
 188                 return ERROR_TARGET_NOT_HALTED;
 189         }
 190
 191         buf_set_u32(reg->value, 0, 32, value);
 192         reg->dirty = 1;
 193         reg->valid = 1;
 194
 195         return ERROR_OK;
 196 }
 197
 198 int armv7m_read_core_reg(struct target_s *target, int num)
 199 {
 200         uint32_t reg_value;
 201         int retval;
 202         armv7m_core_reg_t * armv7m_core_reg;
 203
 204         /* get pointers to arch-specific information */
 205         armv7m_common_t *armv7m = target->arch_info;
 206
 207         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 208                 return ERROR_INVALID_ARGUMENTS;
 209
 210         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 211         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 212         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 213         armv7m->core_cache->reg_list[num].valid = 1;
 214         armv7m->core_cache->reg_list[num].dirty = 0;
 215
 216         return retval;
 217 }
 218
 219 int armv7m_write_core_reg(struct target_s *target, int num)
 220 {
 221         int retval;
 222         uint32_t reg_value;
 223         armv7m_core_reg_t *armv7m_core_reg;
 224
 225         /* get pointers to arch-specific information */
 226         armv7m_common_t *armv7m = target->arch_info;
 227
 228         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 229                 return ERROR_INVALID_ARGUMENTS;
 230
 231         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 232         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 233         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 234         if (retval != ERROR_OK)
 235         {
 236                 LOG_ERROR("JTAG failure");
 237                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 238                 return ERROR_JTAG_DEVICE_ERROR;
 239         }
 240         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 241         armv7m->core_cache->reg_list[num].valid = 1;
 242         armv7m->core_cache->reg_list[num].dirty = 0;
 243
 244         return ERROR_OK;
 245 }
 246
 247 int armv7m_invalidate_core_regs(target_t *target)
 248 {
 249         /* get pointers to arch-specific information */
 250         armv7m_common_t *armv7m = target->arch_info;
 251         int i;
 252
 253         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 254         {
 255                 armv7m->core_cache->reg_list[i].valid = 0;
 256                 armv7m->core_cache->reg_list[i].dirty = 0;
 257         }
 258
 259         return ERROR_OK;
 260 }
 261
 262 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 263 {
 264         /* get pointers to arch-specific information */
 265         armv7m_common_t *armv7m = target->arch_info;
 266         int i;
 267
 268         *reg_list_size = 26;
 269         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 270
 271         for (i = 0; i < 16; i++)
 272         {
 273                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 274         }
 275
 276         for (i = 16; i < 24; i++)
 277         {
 278                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 279         }
 280
 281         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 282
 283 #ifdef ARMV7_GDB_HACKS
 284         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 285         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 286
 287         /* ARMV7M is always in thumb mode, try to make GDB understand this
 288          * if it does not support this arch */
 289         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 290 #else
 291         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 292 #endif
 293
 294         return ERROR_OK;
 295 }
 296
 297 /* run to exit point. return error if exit point was not reached. */
 298 static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
 299 {
 300         uint32_t pc;
 301         int retval;
 302         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 303          * sequence to write register values to the processor and the read them back */
 304         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 305         {
 306                 return retval;
 307         }
 308
 309         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 310         /* If the target fails to halt due to the breakpoint, force a halt */
 311         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 312         {
 313                 if ((retval = target_halt(target)) != ERROR_OK)
 314                         return retval;
 315                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 316                 {
 317                         return retval;
 318                 }
 319                 return ERROR_TARGET_TIMEOUT;
 320         }
 321
 322         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 323         if (pc != exit_point)
 324         {
 325                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 326                 return ERROR_TARGET_TIMEOUT;
 327         }
 328
 329         return ERROR_OK;
 330 }
 331
 332 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 333 {
 334         /* get pointers to arch-specific information */
 335         armv7m_common_t *armv7m = target->arch_info;
 336         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 337         enum armv7m_mode core_mode = armv7m->core_mode;
 338         int retval = ERROR_OK;
 339         int i;
 340         uint32_t context[ARMV7NUMCOREREGS];
 341
 342         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 343         {
 344                 LOG_ERROR("current target isn't an ARMV7M target");
 345                 return ERROR_TARGET_INVALID;
 346         }
 347
 348         if (target->state != TARGET_HALTED)
 349         {
 350                 LOG_WARNING("target not halted");
 351                 return ERROR_TARGET_NOT_HALTED;
 352         }
 353
 354         /* refresh core register cache */
 355         /* Not needed if core register cache is always consistent with target process state */
 356         for (i = 0; i < ARMV7NUMCOREREGS; i++)
 357         {
 358                 if (!armv7m->core_cache->reg_list[i].valid)
 359                         armv7m->read_core_reg(target, i);
 360                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 361         }
 362
 363         for (i = 0; i < num_mem_params; i++)
 364         {
 365                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 366                         return retval;
 367         }
 368
 369         for (i = 0; i < num_reg_params; i++)
 370         {
 371                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 372 //              uint32_t regvalue;
 373
 374                 if (!reg)
 375                 {
 376                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 377                         exit(-1);
 378                 }
 379
 380                 if (reg->size != reg_params[i].size)
 381                 {
 382                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 383                         exit(-1);
 384                 }
 385
 386 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 387                 armv7m_set_core_reg(reg, reg_params[i].value);
 388         }
 389
 390         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 391         {
 392                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 393                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
 394                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 395                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 396         }
 397
 398         /* ARMV7M always runs in Thumb state */
 399         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 400         {
 401                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 402                 return ERROR_TARGET_FAILURE;
 403         }
 404
 405         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 406
 407         breakpoint_remove(target, exit_point);
 408
 409         if (retval != ERROR_OK)
 410         {
 411                 return retval;
 412         }
 413
 414         /* Read memory values to mem_params[] */
 415         for (i = 0; i < num_mem_params; i++)
 416         {
 417                 if (mem_params[i].direction != PARAM_OUT)
 418                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 419                         {
 420                                 return retval;
 421                         }
 422         }
 423
 424         /* Copy core register values to reg_params[] */
 425         for (i = 0; i < num_reg_params; i++)
 426         {
 427                 if (reg_params[i].direction != PARAM_OUT)
 428                 {
 429                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 430
 431                         if (!reg)
 432                         {
 433                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 434                                 exit(-1);
 435                         }
 436
 437                         if (reg->size != reg_params[i].size)
 438                         {
 439                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 440                                 exit(-1);
 441                         }
 442
 443                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 444                 }
 445         }
 446
 447         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 448         {
 449                 uint32_t regvalue;
 450                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 451                 if (regvalue != context[i])
 452                 {
 453                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
 454                         buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 455                         armv7m->core_cache->reg_list[i].valid = 1;
 456                         armv7m->core_cache->reg_list[i].dirty = 1;
 457                 }
 458         }
 459
 460         armv7m->core_mode = core_mode;
 461
 462         return retval;
 463 }
 464
 465 int armv7m_arch_state(struct target_s *target)
 466 {
 467         /* get pointers to arch-specific information */
 468         armv7m_common_t *armv7m = target->arch_info;
 469
 470         LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 471                  Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
 472                 armv7m_mode_strings[armv7m->core_mode],
 473                 armv7m_exception_string(armv7m->exception_number),
 474                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 475                 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 476
 477         return ERROR_OK;
 478 }
 479
 480 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 481 {
 482         /* get pointers to arch-specific information */
 483         armv7m_common_t *armv7m = target->arch_info;
 484
 485         int num_regs = ARMV7NUMCOREREGS;
 486         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 487         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 488         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 489         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 490         int i;
 491
 492         if (armv7m_core_reg_arch_type == -1)
 493         {
 494                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 495         }
 496
 497         register_init_dummy(&armv7m_gdb_dummy_fps_reg);
 498 #ifdef ARMV7_GDB_HACKS
 499         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 500 #endif
 501         register_init_dummy(&armv7m_gdb_dummy_fp_reg);
 502
 503         /* Build the process context cache */
 504         cache->name = "arm v7m registers";
 505         cache->next = NULL;
 506         cache->reg_list = reg_list;
 507         cache->num_regs = num_regs;
 508         (*cache_p) = cache;
 509         armv7m->core_cache = cache;
 510
 511         for (i = 0; i < num_regs; i++)
 512         {
 513                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 514                 arch_info[i].target = target;
 515                 arch_info[i].armv7m_common = armv7m;
 516                 reg_list[i].name = armv7m_core_reg_list[i];
 517                 reg_list[i].size = 32;
 518                 reg_list[i].value = calloc(1, 4);
 519                 reg_list[i].dirty = 0;
 520                 reg_list[i].valid = 0;
 521                 reg_list[i].bitfield_desc = NULL;
 522                 reg_list[i].num_bitfields = 0;
 523                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 524                 reg_list[i].arch_info = &arch_info[i];
 525         }
 526
 527         return cache;
 528 }
 529
 530 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 531 {
 532         armv7m_build_reg_cache(target);
 533
 534         return ERROR_OK;
 535 }
 536
 537 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 538 {
 539         /* register arch-specific functions */
 540
 541         target->arch_info = armv7m;
 542         armv7m->read_core_reg = armv7m_read_core_reg;
 543         armv7m->write_core_reg = armv7m_write_core_reg;
 544
 545         return ERROR_OK;
 546 }
 547
 548 int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 549 {
 550         working_area_t *crc_algorithm;
 551         armv7m_algorithm_t armv7m_info;
 552         reg_param_t reg_params[2];
 553         int retval;
 554
 555         uint16_t cortex_m3_crc_code[] = {
 556                 0x4602,                                 /* mov  r2, r0 */
 557                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 558                 0x460B,                                 /* mov  r3, r1 */
 559                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 560                 0xE013,                                 /* b    ncomp */
 561                                                                 /* nbyte: */
 562                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 563                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 564                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 565
 566                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 567                                                                 /* loop: */
 568                 0x2800,                                 /* cmp          r0, #0 */
 569                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 570                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 571                 0x4630,                                 /* mov          r0, r6 */
 572                 0xBFB8,                                 /* it           lt */
 573                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 574                 0x2D08,                                 /* cmp          r5, #8 */
 575                 0xD1F4,                                 /* bne          loop */
 576
 577                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 578                                                                 /* ncomp: */
 579                 0x429C,                                 /* cmp  r4, r3 */
 580                 0xD1E9,                                 /* bne  nbyte */
 581                                                                 /* end: */
 582                 0xE7FE,                                 /* b    end */
 583                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 584         };
 585
 586         uint32_t i;
 587
 588         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 589         {
 590                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 591         }
 592
 593         /* convert flash writing code into a buffer in target endianness */
 594         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 595                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 596                 {
 597                         return retval;
 598                 }
 599
 600         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 601         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 602
 603         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 604         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 605
 606         buf_set_u32(reg_params[0].value, 0, 32, address);
 607         buf_set_u32(reg_params[1].value, 0, 32, count);
 608
 609         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 610                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 611         {
 612                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 613                 destroy_reg_param(&reg_params[0]);
 614                 destroy_reg_param(&reg_params[1]);
 615                 target_free_working_area(target, crc_algorithm);
 616                 return retval;
 617         }
 618
 619         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 620
 621         destroy_reg_param(&reg_params[0]);
 622         destroy_reg_param(&reg_params[1]);
 623
 624         target_free_working_area(target, crc_algorithm);
 625
 626         return ERROR_OK;
 627 }
 628
 629 int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 630 {
 631         working_area_t *erase_check_algorithm;
 632         reg_param_t reg_params[3];
 633         armv7m_algorithm_t armv7m_info;
 634         int retval;
 635         uint32_t i;
 636
 637         uint16_t erase_check_code[] =
 638         {
 639                                                         /* loop: */
 640                 0xF810, 0x3B01,         /* ldrb         r3, [r0], #1 */
 641                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 642                 0x3901,                         /* subs         r1, r1, #1 */
 643                 0xD1F9,                         /* bne          loop */
 644                                                         /* end: */
 645                 0xE7FE,                         /* b            end */
 646         };
 647
 648         /* make sure we have a working area */
 649         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 650         {
 651                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 652         }
 653
 654         /* convert flash writing code into a buffer in target endianness */
 655         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 656                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 657
 658         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 659         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 660
 661         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 662         buf_set_u32(reg_params[0].value, 0, 32, address);
 663
 664         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 665         buf_set_u32(reg_params[1].value, 0, 32, count);
 666
 667         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 668         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 669
 670         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 671                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 672         {
 673                 destroy_reg_param(&reg_params[0]);
 674                 destroy_reg_param(&reg_params[1]);
 675                 destroy_reg_param(&reg_params[2]);
 676                 target_free_working_area(target, erase_check_algorithm);
 677                 return 0;
 678         }
 679
 680         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 681
 682         destroy_reg_param(&reg_params[0]);
 683         destroy_reg_param(&reg_params[1]);
 684         destroy_reg_param(&reg_params[2]);
 685
 686         target_free_working_area(target, erase_check_algorithm);
 687
 688         return ERROR_OK;
 689 }
 690
 691 /*
 692  * Return the debug ap baseaddress in hexadecimal;
 693  * no extra output to simplify script processing
 694  */
 695 static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
 696                 char *cmd, char **args, int argc)
 697 {
 698         target_t *target = get_current_target(cmd_ctx);
 699         armv7m_common_t *armv7m = target->arch_info;
 700         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 701         uint32_t apsel, apselsave, baseaddr;
 702         int retval;
 703
 704         apsel = swjdp->apsel;
 705         apselsave = swjdp->apsel;
 706         if (argc > 0)
 707         {
 708                 apsel = strtoul(args[0], NULL, 0);
 709         }
 710         if (apselsave != apsel)
 711         {
 712                 dap_ap_select(swjdp, apsel);
 713         }
 714
 715         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 716         retval = swjdp_transaction_endcheck(swjdp);
 717         command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
 718
 719         if (apselsave != apsel)
 720         {
 721                 dap_ap_select(swjdp, apselsave);
 722         }
 723
 724         return retval;
 725 }
 726
 727
 728 /*
 729  * Return the debug ap id in hexadecimal;
 730  * no extra output to simplify script processing
 731  */
 732 extern int handle_dap_apid_command(struct command_context_s *cmd_ctx,
 733                 char *cmd, char **args, int argc)
 734 {
 735         target_t *target = get_current_target(cmd_ctx);
 736         armv7m_common_t *armv7m = target->arch_info;
 737         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 738
 739         return dap_apid_command(cmd_ctx, swjdp, args, argc);
 740 }
 741
 742 static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
 743                 char *cmd, char **args, int argc)
 744 {
 745         target_t *target = get_current_target(cmd_ctx);
 746         armv7m_common_t *armv7m = target->arch_info;
 747         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 748
 749         return dap_apsel_command(cmd_ctx, swjdp, args, argc);
 750 }
 751
 752 static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
 753                 char *cmd, char **args, int argc)
 754 {
 755         target_t *target = get_current_target(cmd_ctx);
 756         armv7m_common_t *armv7m = target->arch_info;
 757         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 758
 759         return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
 760 }
 761
 762
 763 static int handle_dap_info_command(struct command_context_s *cmd_ctx,
 764                 char *cmd, char **args, int argc)
 765 {
 766         target_t *target = get_current_target(cmd_ctx);
 767         armv7m_common_t *armv7m = target->arch_info;
 768         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 769         uint32_t apsel;
 770
 771         apsel =  swjdp->apsel;
 772         if (argc > 0)
 773                 apsel = strtoul(args[0], NULL, 0);
 774
 775         return dap_info_command(cmd_ctx, swjdp, apsel);
 776 }
 777
 778 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 779 {
 780         command_t *arm_adi_v5_dap_cmd;
 781
 782         arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
 783                         NULL, COMMAND_ANY,
 784                         "cortex dap specific commands");
 785
 786         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
 787                         handle_dap_info_command, COMMAND_EXEC,
 788                         "Displays dap info for ap [num],"
 789                         "default currently selected AP");
 790         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
 791                         handle_dap_apsel_command, COMMAND_EXEC,
 792                         "Select a different AP [num] (default 0)");
 793         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
 794                         handle_dap_apid_command, COMMAND_EXEC,
 795                         "Displays id reg from AP [num], "
 796                         "default currently selected AP");
 797         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
 798                         handle_dap_baseaddr_command, COMMAND_EXEC,
 799                         "Displays debug base address from AP [num],"
 800                         "default currently selected AP");
 801         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
 802                         handle_dap_memaccess_command, COMMAND_EXEC,
 803                         "set/get number of extra tck for mem-ap "
 804                         "memory bus access [0-255]");
 805
 806         return ERROR_OK;
 807 }