git.sur5r.net Git - openocd/blob - src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual               *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "breakpoints.h"
  38 #include "armv7m.h"
  39 #include "algorithm.h"
  40 #include "register.h"
  41
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
  48 char *armv7m_mode_strings[] =
  49 {
  50         "Thread", "Thread (User)", "Handler",
  51 };
  52
  53 static char *armv7m_exception_strings[] =
  54 {
  55         "", "Reset", "NMI", "HardFault",
  56         "MemManage", "BusFault", "UsageFault", "RESERVED",
  57         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  58         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  59 };
  60
  61 #ifdef ARMV7_GDB_HACKS
  62 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  63
  64 struct reg armv7m_gdb_dummy_cpsr_reg =
  65 {
  66         .name = "GDB dummy cpsr register",
  67         .value = armv7m_gdb_dummy_cpsr_value,
  68         .dirty = 0,
  69         .valid = 1,
  70         .size = 32,
  71         .arch_info = NULL,
  72 };
  73 #endif
  74
  75 /*
  76  * These registers are not memory-mapped.  The ARMv7-M profile includes
  77  * memory mapped registers too, such as for the NVIC (interrupt controller)
  78  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  79  *
  80  * The ARMv6-M profile is almost identical in this respect, except that it
  81  * doesn't include basepri or faultmask registers.
  82  */
  83 static const struct {
  84         unsigned id;
  85         char *name;
  86         unsigned bits;
  87 } armv7m_regs[] = {
  88         { ARMV7M_R0, "r0", 32 },
  89         { ARMV7M_R1, "r1", 32 },
  90         { ARMV7M_R2, "r2", 32 },
  91         { ARMV7M_R3, "r3", 32 },
  92
  93         { ARMV7M_R4, "r4", 32 },
  94         { ARMV7M_R5, "r5", 32 },
  95         { ARMV7M_R6, "r6", 32 },
  96         { ARMV7M_R7, "r7", 32 },
  97
  98         { ARMV7M_R8, "r8", 32 },
  99         { ARMV7M_R9, "r9", 32 },
 100         { ARMV7M_R10, "r10", 32 },
 101         { ARMV7M_R11, "r11", 32 },
 102
 103         { ARMV7M_R12, "r12", 32 },
 104         { ARMV7M_R13, "sp", 32 },
 105         { ARMV7M_R14, "lr", 32 },
 106         { ARMV7M_PC, "pc", 32 },
 107
 108         { ARMV7M_xPSR, "xPSR", 32 },
 109         { ARMV7M_MSP, "msp", 32 },
 110         { ARMV7M_PSP, "psp", 32 },
 111
 112         { ARMV7M_PRIMASK, "primask", 1 },
 113         { ARMV7M_BASEPRI, "basepri", 8 },
 114         { ARMV7M_FAULTMASK, "faultmask", 1 },
 115         { ARMV7M_CONTROL, "control", 2 },
 116 };
 117
 118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 119
 120 /**
 121  * Restores target context using the cache of core registers set up
 122  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 123  */
 124 int armv7m_restore_context(struct target *target)
 125 {
 126         int i;
 127         struct armv7m_common *armv7m = target_to_armv7m(target);
 128
 129         LOG_DEBUG(" ");
 130
 131         if (armv7m->pre_restore_context)
 132                 armv7m->pre_restore_context(target);
 133
 134         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 135         {
 136                 if (armv7m->core_cache->reg_list[i].dirty)
 137                 {
 138                         armv7m->write_core_reg(target, i);
 139                 }
 140         }
 141
 142         if (armv7m->post_restore_context)
 143                 armv7m->post_restore_context(target);
 144
 145         return ERROR_OK;
 146 }
 147
 148 /* Core state functions */
 149
 150 /**
 151  * Maps ISR number (from xPSR) to name.
 152  * Note that while names and meanings for the first sixteen are standardized
 153  * (with zero not a true exception), external interrupts are only numbered.
 154  * They are assigned by vendors, which generally assign different numbers to
 155  * peripherals (such as UART0 or a USB peripheral controller).
 156  */
 157 char *armv7m_exception_string(int number)
 158 {
 159         static char enamebuf[32];
 160
 161         if ((number < 0) | (number > 511))
 162                 return "Invalid exception";
 163         if (number < 16)
 164                 return armv7m_exception_strings[number];
 165         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 166         return enamebuf;
 167 }
 168
 169 static int armv7m_get_core_reg(struct reg *reg)
 170 {
 171         int retval;
 172         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 173         struct target *target = armv7m_reg->target;
 174         struct armv7m_common *armv7m = target_to_armv7m(target);
 175
 176         if (target->state != TARGET_HALTED)
 177         {
 178                 return ERROR_TARGET_NOT_HALTED;
 179         }
 180
 181         retval = armv7m->read_core_reg(target, armv7m_reg->num);
 182
 183         return retval;
 184 }
 185
 186 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 187 {
 188         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 189         struct target *target = armv7m_reg->target;
 190         uint32_t value = buf_get_u32(buf, 0, 32);
 191
 192         if (target->state != TARGET_HALTED)
 193         {
 194                 return ERROR_TARGET_NOT_HALTED;
 195         }
 196
 197         buf_set_u32(reg->value, 0, 32, value);
 198         reg->dirty = 1;
 199         reg->valid = 1;
 200
 201         return ERROR_OK;
 202 }
 203
 204 static int armv7m_read_core_reg(struct target *target, unsigned num)
 205 {
 206         uint32_t reg_value;
 207         int retval;
 208         struct armv7m_core_reg * armv7m_core_reg;
 209         struct armv7m_common *armv7m = target_to_armv7m(target);
 210
 211         if (num >= ARMV7M_NUM_REGS)
 212                 return ERROR_INVALID_ARGUMENTS;
 213
 214         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 215         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 216         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 217         armv7m->core_cache->reg_list[num].valid = 1;
 218         armv7m->core_cache->reg_list[num].dirty = 0;
 219
 220         return retval;
 221 }
 222
 223 static int armv7m_write_core_reg(struct target *target, unsigned num)
 224 {
 225         int retval;
 226         uint32_t reg_value;
 227         struct armv7m_core_reg *armv7m_core_reg;
 228         struct armv7m_common *armv7m = target_to_armv7m(target);
 229
 230         if (num >= ARMV7M_NUM_REGS)
 231                 return ERROR_INVALID_ARGUMENTS;
 232
 233         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 234         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 235         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 236         if (retval != ERROR_OK)
 237         {
 238                 LOG_ERROR("JTAG failure");
 239                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 240                 return ERROR_JTAG_DEVICE_ERROR;
 241         }
 242         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 243         armv7m->core_cache->reg_list[num].valid = 1;
 244         armv7m->core_cache->reg_list[num].dirty = 0;
 245
 246         return ERROR_OK;
 247 }
 248
 249 /**
 250  * Returns generic ARM userspace registers to GDB.
 251  * GDB doesn't quite understand that most ARMs don't have floating point
 252  * hardware, so this also fakes a set of long-obsolete FPA registers that
 253  * are not used in EABI based software stacks.
 254  */
 255 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 256 {
 257         struct armv7m_common *armv7m = target_to_armv7m(target);
 258         int i;
 259
 260         *reg_list_size = 26;
 261         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 262
 263         /*
 264          * GDB register packet format for ARM:
 265          *  - the first 16 registers are r0..r15
 266          *  - (obsolete) 8 FPA registers
 267          *  - (obsolete) FPA status
 268          *  - CPSR
 269          */
 270         for (i = 0; i < 16; i++)
 271         {
 272                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 273         }
 274
 275         for (i = 16; i < 24; i++)
 276                 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 277         (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 278
 279 #ifdef ARMV7_GDB_HACKS
 280         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 281         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 282
 283         /* ARMV7M is always in thumb mode, try to make GDB understand this
 284          * if it does not support this arch */
 285         *((char*)armv7m->arm.pc->value) |= 1;
 286 #else
 287         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 288 #endif
 289
 290         return ERROR_OK;
 291 }
 292
 293 /* run to exit point. return error if exit point was not reached. */
 294 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
 295 {
 296         uint32_t pc;
 297         int retval;
 298         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 299          * sequence to write register values to the processor and the read them back */
 300         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 301         {
 302                 return retval;
 303         }
 304
 305         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 306         /* If the target fails to halt due to the breakpoint, force a halt */
 307         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 308         {
 309                 if ((retval = target_halt(target)) != ERROR_OK)
 310                         return retval;
 311                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 312                 {
 313                         return retval;
 314                 }
 315                 return ERROR_TARGET_TIMEOUT;
 316         }
 317
 318         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 319         if (pc != exit_point)
 320         {
 321                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 322                 return ERROR_TARGET_TIMEOUT;
 323         }
 324
 325         return ERROR_OK;
 326 }
 327
 328 /** Runs a Thumb algorithm in the target. */
 329 int armv7m_run_algorithm(struct target *target,
 330         int num_mem_params, struct mem_param *mem_params,
 331         int num_reg_params, struct reg_param *reg_params,
 332         uint32_t entry_point, uint32_t exit_point,
 333         int timeout_ms, void *arch_info)
 334 {
 335         struct armv7m_common *armv7m = target_to_armv7m(target);
 336         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 337         enum armv7m_mode core_mode = armv7m->core_mode;
 338         int retval = ERROR_OK;
 339         uint32_t context[ARMV7M_NUM_REGS];
 340
 341         /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
 342          * at the exit point */
 343
 344         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 345         {
 346                 LOG_ERROR("current target isn't an ARMV7M target");
 347                 return ERROR_TARGET_INVALID;
 348         }
 349
 350         if (target->state != TARGET_HALTED)
 351         {
 352                 LOG_WARNING("target not halted");
 353                 return ERROR_TARGET_NOT_HALTED;
 354         }
 355
 356         /* refresh core register cache */
 357         /* Not needed if core register cache is always consistent with target process state */
 358         for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
 359         {
 360                 if (!armv7m->core_cache->reg_list[i].valid)
 361                         armv7m->read_core_reg(target, i);
 362                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 363         }
 364
 365         for (int i = 0; i < num_mem_params; i++)
 366         {
 367                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 368                         return retval;
 369         }
 370
 371         for (int i = 0; i < num_reg_params; i++)
 372         {
 373                 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 374 //              uint32_t regvalue;
 375
 376                 if (!reg)
 377                 {
 378                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 379                         return ERROR_INVALID_ARGUMENTS;
 380                 }
 381
 382                 if (reg->size != reg_params[i].size)
 383                 {
 384                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 385                         return ERROR_INVALID_ARGUMENTS;
 386                 }
 387
 388 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 389                 armv7m_set_core_reg(reg, reg_params[i].value);
 390         }
 391
 392         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 393         {
 394                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 395                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 396                                 0, 1, armv7m_algorithm_info->core_mode);
 397                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 398                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 399         }
 400
 401         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 402
 403         if (retval != ERROR_OK)
 404         {
 405                 return retval;
 406         }
 407
 408         /* Read memory values to mem_params[] */
 409         for (int i = 0; i < num_mem_params; i++)
 410         {
 411                 if (mem_params[i].direction != PARAM_OUT)
 412                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 413                         {
 414                                 return retval;
 415                         }
 416         }
 417
 418         /* Copy core register values to reg_params[] */
 419         for (int i = 0; i < num_reg_params; i++)
 420         {
 421                 if (reg_params[i].direction != PARAM_OUT)
 422                 {
 423                         struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 424
 425                         if (!reg)
 426                         {
 427                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 428                                 return ERROR_INVALID_ARGUMENTS;
 429                         }
 430
 431                         if (reg->size != reg_params[i].size)
 432                         {
 433                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 434                                 return ERROR_INVALID_ARGUMENTS;
 435                         }
 436
 437                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 438                 }
 439         }
 440
 441         for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 442         {
 443                 uint32_t regvalue;
 444                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 445                 if (regvalue != context[i])
 446                 {
 447                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 448                                 armv7m->core_cache->reg_list[i].name, context[i]);
 449                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 450                                         0, 32, context[i]);
 451                         armv7m->core_cache->reg_list[i].valid = 1;
 452                         armv7m->core_cache->reg_list[i].dirty = 1;
 453                 }
 454         }
 455
 456         armv7m->core_mode = core_mode;
 457
 458         return retval;
 459 }
 460
 461 /** Logs summary of ARMv7-M state for a halted target. */
 462 int armv7m_arch_state(struct target *target)
 463 {
 464         struct armv7m_common *armv7m = target_to_armv7m(target);
 465         struct arm *arm = &armv7m->arm;
 466         uint32_t ctrl, sp;
 467
 468         ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 469         sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 470
 471         LOG_USER("target halted due to %s, current mode: %s %s\n"
 472                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
 473                 debug_reason_name(target),
 474                 armv7m_mode_strings[armv7m->core_mode],
 475                 armv7m_exception_string(armv7m->exception_number),
 476                 buf_get_u32(arm->cpsr->value, 0, 32),
 477                 buf_get_u32(arm->pc->value, 0, 32),
 478                 (ctrl & 0x02) ? 'p' : 'm',
 479                 sp,
 480                 arm->is_semihosting ? ", semihosting" : "");
 481
 482         return ERROR_OK;
 483 }
 484 static const struct reg_arch_type armv7m_reg_type = {
 485         .get = armv7m_get_core_reg,
 486         .set = armv7m_set_core_reg,
 487 };
 488
 489 /** Builds cache of architecturally defined registers.  */
 490 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 491 {
 492         struct armv7m_common *armv7m = target_to_armv7m(target);
 493         struct arm *arm = &armv7m->arm;
 494         int num_regs = ARMV7M_NUM_REGS;
 495         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 496         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 497         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 498         struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 499         int i;
 500
 501 #ifdef ARMV7_GDB_HACKS
 502         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 503 #endif
 504
 505         /* Build the process context cache */
 506         cache->name = "arm v7m registers";
 507         cache->next = NULL;
 508         cache->reg_list = reg_list;
 509         cache->num_regs = num_regs;
 510         (*cache_p) = cache;
 511         armv7m->core_cache = cache;
 512
 513         for (i = 0; i < num_regs; i++)
 514         {
 515                 arch_info[i].num = armv7m_regs[i].id;
 516                 arch_info[i].target = target;
 517                 arch_info[i].armv7m_common = armv7m;
 518                 reg_list[i].name = armv7m_regs[i].name;
 519                 reg_list[i].size = armv7m_regs[i].bits;
 520                 reg_list[i].value = calloc(1, 4);
 521                 reg_list[i].dirty = 0;
 522                 reg_list[i].valid = 0;
 523                 reg_list[i].type = &armv7m_reg_type;
 524                 reg_list[i].arch_info = &arch_info[i];
 525         }
 526
 527         arm->cpsr = reg_list + ARMV7M_xPSR;
 528         arm->pc = reg_list + ARMV7M_PC;
 529         arm->core_cache = cache;
 530         return cache;
 531 }
 532
 533 int armv7m_setup_semihosting(struct target *target, int enable)
 534 {
 535         /* nothing todo for armv7m */
 536         return ERROR_OK;
 537 }
 538
 539 /** Sets up target as a generic ARMv7-M core */
 540 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 541 {
 542         struct arm *arm = &armv7m->arm;
 543
 544         armv7m->common_magic = ARMV7M_COMMON_MAGIC;
 545
 546         arm->core_type = ARM_MODE_THREAD;
 547         arm->arch_info = armv7m;
 548         arm->setup_semihosting = armv7m_setup_semihosting;
 549
 550         /* FIXME remove v7m-specific r/w core_reg functions;
 551          * use the generic ARM core support..
 552          */
 553         armv7m->read_core_reg = armv7m_read_core_reg;
 554         armv7m->write_core_reg = armv7m_write_core_reg;
 555
 556         return arm_init_arch_info(target, arm);
 557 }
 558
 559 /** Generates a CRC32 checksum of a memory region. */
 560 int armv7m_checksum_memory(struct target *target,
 561                 uint32_t address, uint32_t count, uint32_t* checksum)
 562 {
 563         struct working_area *crc_algorithm;
 564         struct armv7m_algorithm armv7m_info;
 565         struct reg_param reg_params[2];
 566         int retval;
 567
 568         static const uint16_t cortex_m3_crc_code[] = {
 569                 0x4602,                                 /* mov  r2, r0 */
 570                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 571                 0x460B,                                 /* mov  r3, r1 */
 572                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 573                 0xE013,                                 /* b    ncomp */
 574                                                                 /* nbyte: */
 575                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 576                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 577                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 578
 579                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 580                                                                 /* loop: */
 581                 0x2800,                                 /* cmp          r0, #0 */
 582                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 583                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 584                 0x4630,                                 /* mov          r0, r6 */
 585                 0xBFB8,                                 /* it           lt */
 586                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 587                 0x2D08,                                 /* cmp          r5, #8 */
 588                 0xD1F4,                                 /* bne          loop */
 589
 590                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 591                                                                 /* ncomp: */
 592                 0x429C,                                 /* cmp  r4, r3 */
 593                 0xD1E9,                                 /* bne  nbyte */
 594                 0xBE00,                         /* bkpt #0 */
 595                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 596         };
 597
 598         uint32_t i;
 599
 600         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 601         {
 602                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 603         }
 604
 605         /* convert flash writing code into a buffer in target endianness */
 606         for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++)
 607                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 608                 {
 609                         return retval;
 610                 }
 611
 612         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 613         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 614
 615         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 616         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 617
 618         buf_set_u32(reg_params[0].value, 0, 32, address);
 619         buf_set_u32(reg_params[1].value, 0, 32, count);
 620
 621         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 622                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 623         {
 624                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 625                 destroy_reg_param(&reg_params[0]);
 626                 destroy_reg_param(&reg_params[1]);
 627                 target_free_working_area(target, crc_algorithm);
 628                 return retval;
 629         }
 630
 631         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 632
 633         destroy_reg_param(&reg_params[0]);
 634         destroy_reg_param(&reg_params[1]);
 635
 636         target_free_working_area(target, crc_algorithm);
 637
 638         return ERROR_OK;
 639 }
 640
 641 /** Checks whether a memory region is zeroed. */
 642 int armv7m_blank_check_memory(struct target *target,
 643                 uint32_t address, uint32_t count, uint32_t* blank)
 644 {
 645         struct working_area *erase_check_algorithm;
 646         struct reg_param reg_params[3];
 647         struct armv7m_algorithm armv7m_info;
 648         int retval;
 649         uint32_t i;
 650
 651         static const uint16_t erase_check_code[] =
 652         {
 653                 /* loop: */
 654                 0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
 655                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 656                 0x3901,                         /* subs r1, r1, #1 */
 657                 0xD1F9,                         /* bne  loop */
 658                 0xBE00,                 /* bkpt #0 */
 659         };
 660
 661         /* make sure we have a working area */
 662         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 663         {
 664                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 665         }
 666
 667         /* convert flash writing code into a buffer in target endianness */
 668         for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
 669                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 670
 671         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 672         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 673
 674         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 675         buf_set_u32(reg_params[0].value, 0, 32, address);
 676
 677         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 678         buf_set_u32(reg_params[1].value, 0, 32, count);
 679
 680         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 681         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 682
 683         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 684                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 685         {
 686                 destroy_reg_param(&reg_params[0]);
 687                 destroy_reg_param(&reg_params[1]);
 688                 destroy_reg_param(&reg_params[2]);
 689                 target_free_working_area(target, erase_check_algorithm);
 690                 return 0;
 691         }
 692
 693         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 694
 695         destroy_reg_param(&reg_params[0]);
 696         destroy_reg_param(&reg_params[1]);
 697         destroy_reg_param(&reg_params[2]);
 698
 699         target_free_working_area(target, erase_check_algorithm);
 700
 701         return ERROR_OK;
 702 }
 703
 704 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 705 {
 706         struct armv7m_common *armv7m = target_to_armv7m(target);
 707         struct reg *r = armv7m->arm.pc;
 708         bool result = false;
 709
 710
 711         /* if we halted last time due to a bkpt instruction
 712          * then we have to manually step over it, otherwise
 713          * the core will break again */
 714
 715         if (target->debug_reason == DBG_REASON_BREAKPOINT)
 716         {
 717                 uint16_t op;
 718                 uint32_t pc = buf_get_u32(r->value, 0, 32);
 719
 720                 pc &= ~1;
 721                 if (target_read_u16(target, pc, &op) == ERROR_OK)
 722                 {
 723                         if ((op & 0xFF00) == 0xBE00)
 724                         {
 725                                 pc = buf_get_u32(r->value, 0, 32) + 2;
 726                                 buf_set_u32(r->value, 0, 32, pc);
 727                                 r->dirty = true;
 728                                 r->valid = true;
 729                                 result = true;
 730                                 LOG_DEBUG("Skipping over BKPT instruction");
 731                         }
 732                 }
 733         }
 734
 735         if (inst_found) {
 736                 *inst_found = result;
 737         }
 738
 739         return ERROR_OK;
 740 }
 741
 742 const struct command_registration armv7m_command_handlers[] = {
 743         {
 744                 .chain = arm_command_handlers,
 745         },
 746         {
 747                 .chain = dap_command_handlers,
 748         },
 749         COMMAND_REGISTRATION_DONE
 750 };