git.sur5r.net Git - openocd/blob - src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual               *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "breakpoints.h"
  38 #include "armv7m.h"
  39 #include "algorithm.h"
  40 #include "register.h"
  41
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
  48 char *armv7m_mode_strings[] =
  49 {
  50         "Thread", "Thread (User)", "Handler",
  51 };
  52
  53 static char *armv7m_exception_strings[] =
  54 {
  55         "", "Reset", "NMI", "HardFault",
  56         "MemManage", "BusFault", "UsageFault", "RESERVED",
  57         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  58         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  59 };
  60
  61 #ifdef ARMV7_GDB_HACKS
  62 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  63
  64 struct reg armv7m_gdb_dummy_cpsr_reg =
  65 {
  66         .name = "GDB dummy cpsr register",
  67         .value = armv7m_gdb_dummy_cpsr_value,
  68         .dirty = 0,
  69         .valid = 1,
  70         .size = 32,
  71         .arch_info = NULL,
  72 };
  73 #endif
  74
  75 /*
  76  * These registers are not memory-mapped.  The ARMv7-M profile includes
  77  * memory mapped registers too, such as for the NVIC (interrupt controller)
  78  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  79  *
  80  * The ARMv6-M profile is almost identical in this respect, except that it
  81  * doesn't include basepri or faultmask registers.
  82  */
  83 static const struct {
  84         unsigned id;
  85         char *name;
  86         unsigned bits;
  87 } armv7m_regs[] = {
  88         { ARMV7M_R0, "r0", 32 },
  89         { ARMV7M_R1, "r1", 32 },
  90         { ARMV7M_R2, "r2", 32 },
  91         { ARMV7M_R3, "r3", 32 },
  92
  93         { ARMV7M_R4, "r4", 32 },
  94         { ARMV7M_R5, "r5", 32 },
  95         { ARMV7M_R6, "r6", 32 },
  96         { ARMV7M_R7, "r7", 32 },
  97
  98         { ARMV7M_R8, "r8", 32 },
  99         { ARMV7M_R9, "r9", 32 },
 100         { ARMV7M_R10, "r10", 32 },
 101         { ARMV7M_R11, "r11", 32 },
 102
 103         { ARMV7M_R12, "r12", 32 },
 104         { ARMV7M_R13, "sp", 32 },
 105         { ARMV7M_R14, "lr", 32 },
 106         { ARMV7M_PC, "pc", 32 },
 107
 108         { ARMV7M_xPSR, "xPSR", 32 },
 109         { ARMV7M_MSP, "msp", 32 },
 110         { ARMV7M_PSP, "psp", 32 },
 111
 112         { ARMV7M_PRIMASK, "primask", 1 },
 113         { ARMV7M_BASEPRI, "basepri", 8 },
 114         { ARMV7M_FAULTMASK, "faultmask", 1 },
 115         { ARMV7M_CONTROL, "control", 2 },
 116 };
 117
 118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 119
 120 /**
 121  * Restores target context using the cache of core registers set up
 122  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 123  */
 124 int armv7m_restore_context(struct target *target)
 125 {
 126         int i;
 127         struct armv7m_common *armv7m = target_to_armv7m(target);
 128
 129         LOG_DEBUG(" ");
 130
 131         if (armv7m->pre_restore_context)
 132                 armv7m->pre_restore_context(target);
 133
 134         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 135         {
 136                 if (armv7m->core_cache->reg_list[i].dirty)
 137                 {
 138                         armv7m->write_core_reg(target, i);
 139                 }
 140         }
 141
 142         if (armv7m->post_restore_context)
 143                 armv7m->post_restore_context(target);
 144
 145         return ERROR_OK;
 146 }
 147
 148 /* Core state functions */
 149
 150 /**
 151  * Maps ISR number (from xPSR) to name.
 152  * Note that while names and meanings for the first sixteen are standardized
 153  * (with zero not a true exception), external interrupts are only numbered.
 154  * They are assigned by vendors, which generally assign different numbers to
 155  * peripherals (such as UART0 or a USB peripheral controller).
 156  */
 157 char *armv7m_exception_string(int number)
 158 {
 159         static char enamebuf[32];
 160
 161         if ((number < 0) | (number > 511))
 162                 return "Invalid exception";
 163         if (number < 16)
 164                 return armv7m_exception_strings[number];
 165         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 166         return enamebuf;
 167 }
 168
 169 static int armv7m_get_core_reg(struct reg *reg)
 170 {
 171         int retval;
 172         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 173         struct target *target = armv7m_reg->target;
 174         struct armv7m_common *armv7m = target_to_armv7m(target);
 175
 176         if (target->state != TARGET_HALTED)
 177         {
 178                 return ERROR_TARGET_NOT_HALTED;
 179         }
 180
 181         retval = armv7m->read_core_reg(target, armv7m_reg->num);
 182
 183         return retval;
 184 }
 185
 186 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 187 {
 188         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 189         struct target *target = armv7m_reg->target;
 190         uint32_t value = buf_get_u32(buf, 0, 32);
 191
 192         if (target->state != TARGET_HALTED)
 193         {
 194                 return ERROR_TARGET_NOT_HALTED;
 195         }
 196
 197         buf_set_u32(reg->value, 0, 32, value);
 198         reg->dirty = 1;
 199         reg->valid = 1;
 200
 201         return ERROR_OK;
 202 }
 203
 204 static int armv7m_read_core_reg(struct target *target, unsigned num)
 205 {
 206         uint32_t reg_value;
 207         int retval;
 208         struct armv7m_core_reg * armv7m_core_reg;
 209         struct armv7m_common *armv7m = target_to_armv7m(target);
 210
 211         if (num >= ARMV7M_NUM_REGS)
 212                 return ERROR_INVALID_ARGUMENTS;
 213
 214         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 215         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 216         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 217         armv7m->core_cache->reg_list[num].valid = 1;
 218         armv7m->core_cache->reg_list[num].dirty = 0;
 219
 220         return retval;
 221 }
 222
 223 static int armv7m_write_core_reg(struct target *target, unsigned num)
 224 {
 225         int retval;
 226         uint32_t reg_value;
 227         struct armv7m_core_reg *armv7m_core_reg;
 228         struct armv7m_common *armv7m = target_to_armv7m(target);
 229
 230         if (num >= ARMV7M_NUM_REGS)
 231                 return ERROR_INVALID_ARGUMENTS;
 232
 233         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 234         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 235         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 236         if (retval != ERROR_OK)
 237         {
 238                 LOG_ERROR("JTAG failure");
 239                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 240                 return ERROR_JTAG_DEVICE_ERROR;
 241         }
 242         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 243         armv7m->core_cache->reg_list[num].valid = 1;
 244         armv7m->core_cache->reg_list[num].dirty = 0;
 245
 246         return ERROR_OK;
 247 }
 248
 249 /** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
 250 int armv7m_invalidate_core_regs(struct target *target)
 251 {
 252         struct armv7m_common *armv7m = target_to_armv7m(target);
 253         int i;
 254
 255         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 256         {
 257                 armv7m->core_cache->reg_list[i].valid = 0;
 258                 armv7m->core_cache->reg_list[i].dirty = 0;
 259         }
 260
 261         return ERROR_OK;
 262 }
 263
 264 /**
 265  * Returns generic ARM userspace registers to GDB.
 266  * GDB doesn't quite understand that most ARMs don't have floating point
 267  * hardware, so this also fakes a set of long-obsolete FPA registers that
 268  * are not used in EABI based software stacks.
 269  */
 270 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 271 {
 272         struct armv7m_common *armv7m = target_to_armv7m(target);
 273         int i;
 274
 275         *reg_list_size = 26;
 276         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 277
 278         /*
 279          * GDB register packet format for ARM:
 280          *  - the first 16 registers are r0..r15
 281          *  - (obsolete) 8 FPA registers
 282          *  - (obsolete) FPA status
 283          *  - CPSR
 284          */
 285         for (i = 0; i < 16; i++)
 286         {
 287                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 288         }
 289
 290         for (i = 16; i < 24; i++)
 291                 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 292         (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 293
 294 #ifdef ARMV7_GDB_HACKS
 295         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 296         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 297
 298         /* ARMV7M is always in thumb mode, try to make GDB understand this
 299          * if it does not support this arch */
 300         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 301 #else
 302         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 303 #endif
 304
 305         return ERROR_OK;
 306 }
 307
 308 /* run to exit point. return error if exit point was not reached. */
 309 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
 310 {
 311         uint32_t pc;
 312         int retval;
 313         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 314          * sequence to write register values to the processor and the read them back */
 315         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 316         {
 317                 return retval;
 318         }
 319
 320         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 321         /* If the target fails to halt due to the breakpoint, force a halt */
 322         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 323         {
 324                 if ((retval = target_halt(target)) != ERROR_OK)
 325                         return retval;
 326                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 327                 {
 328                         return retval;
 329                 }
 330                 return ERROR_TARGET_TIMEOUT;
 331         }
 332
 333         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 334         if (pc != exit_point)
 335         {
 336                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 337                 return ERROR_TARGET_TIMEOUT;
 338         }
 339
 340         return ERROR_OK;
 341 }
 342
 343 /** Runs a Thumb algorithm in the target. */
 344 int armv7m_run_algorithm(struct target *target,
 345         int num_mem_params, struct mem_param *mem_params,
 346         int num_reg_params, struct reg_param *reg_params,
 347         uint32_t entry_point, uint32_t exit_point,
 348         int timeout_ms, void *arch_info)
 349 {
 350         struct armv7m_common *armv7m = target_to_armv7m(target);
 351         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 352         enum armv7m_mode core_mode = armv7m->core_mode;
 353         int retval = ERROR_OK;
 354         uint32_t context[ARMV7M_NUM_REGS];
 355
 356         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 357         {
 358                 LOG_ERROR("current target isn't an ARMV7M target");
 359                 return ERROR_TARGET_INVALID;
 360         }
 361
 362         if (target->state != TARGET_HALTED)
 363         {
 364                 LOG_WARNING("target not halted");
 365                 return ERROR_TARGET_NOT_HALTED;
 366         }
 367
 368         /* refresh core register cache */
 369         /* Not needed if core register cache is always consistent with target process state */
 370         for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
 371         {
 372                 if (!armv7m->core_cache->reg_list[i].valid)
 373                         armv7m->read_core_reg(target, i);
 374                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 375         }
 376
 377         for (int i = 0; i < num_mem_params; i++)
 378         {
 379                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 380                         return retval;
 381         }
 382
 383         for (int i = 0; i < num_reg_params; i++)
 384         {
 385                 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 386 //              uint32_t regvalue;
 387
 388                 if (!reg)
 389                 {
 390                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 391                         return ERROR_INVALID_ARGUMENTS;
 392                 }
 393
 394                 if (reg->size != reg_params[i].size)
 395                 {
 396                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 397                         return ERROR_INVALID_ARGUMENTS;
 398                 }
 399
 400 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 401                 armv7m_set_core_reg(reg, reg_params[i].value);
 402         }
 403
 404         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 405         {
 406                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 407                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 408                                 0, 1, armv7m_algorithm_info->core_mode);
 409                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 410                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 411         }
 412
 413         /* REVISIT speed things up (3% or so in one case) by requiring
 414          * algorithms to include a BKPT instruction at each exit point.
 415          * This eliminates overheads of adding/removing a breakpoint.
 416          */
 417
 418         /* ARMV7M always runs in Thumb state */
 419         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 420         {
 421                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 422                 return ERROR_TARGET_FAILURE;
 423         }
 424
 425         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 426
 427         breakpoint_remove(target, exit_point);
 428
 429         if (retval != ERROR_OK)
 430         {
 431                 return retval;
 432         }
 433
 434         /* Read memory values to mem_params[] */
 435         for (int i = 0; i < num_mem_params; i++)
 436         {
 437                 if (mem_params[i].direction != PARAM_OUT)
 438                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 439                         {
 440                                 return retval;
 441                         }
 442         }
 443
 444         /* Copy core register values to reg_params[] */
 445         for (int i = 0; i < num_reg_params; i++)
 446         {
 447                 if (reg_params[i].direction != PARAM_OUT)
 448                 {
 449                         struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 450
 451                         if (!reg)
 452                         {
 453                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 454                                 return ERROR_INVALID_ARGUMENTS;
 455                         }
 456
 457                         if (reg->size != reg_params[i].size)
 458                         {
 459                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 460                                 return ERROR_INVALID_ARGUMENTS;
 461                         }
 462
 463                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 464                 }
 465         }
 466
 467         for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 468         {
 469                 uint32_t regvalue;
 470                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 471                 if (regvalue != context[i])
 472                 {
 473                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 474                                 armv7m->core_cache->reg_list[i].name, context[i]);
 475                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 476                                         0, 32, context[i]);
 477                         armv7m->core_cache->reg_list[i].valid = 1;
 478                         armv7m->core_cache->reg_list[i].dirty = 1;
 479                 }
 480         }
 481
 482         armv7m->core_mode = core_mode;
 483
 484         return retval;
 485 }
 486
 487 /** Logs summary of ARMv7-M state for a halted target. */
 488 int armv7m_arch_state(struct target *target)
 489 {
 490         struct armv7m_common *armv7m = target_to_armv7m(target);
 491         uint32_t ctrl, sp;
 492
 493         ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 494         sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 495
 496         LOG_USER("target halted due to %s, current mode: %s %s\n"
 497                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
 498                 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 499                                 target->debug_reason)->name,
 500                 armv7m_mode_strings[armv7m->core_mode],
 501                 armv7m_exception_string(armv7m->exception_number),
 502                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 503                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
 504                 (ctrl & 0x02) ? 'p' : 'm',
 505                 sp);
 506
 507         return ERROR_OK;
 508 }
 509 static const struct reg_arch_type armv7m_reg_type = {
 510         .get = armv7m_get_core_reg,
 511         .set = armv7m_set_core_reg,
 512 };
 513
 514 /** Builds cache of architecturally defined registers.  */
 515 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 516 {
 517         struct armv7m_common *armv7m = target_to_armv7m(target);
 518         int num_regs = ARMV7M_NUM_REGS;
 519         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 520         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 521         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 522         struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 523         int i;
 524
 525 #ifdef ARMV7_GDB_HACKS
 526         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 527 #endif
 528
 529         /* Build the process context cache */
 530         cache->name = "arm v7m registers";
 531         cache->next = NULL;
 532         cache->reg_list = reg_list;
 533         cache->num_regs = num_regs;
 534         (*cache_p) = cache;
 535         armv7m->core_cache = cache;
 536
 537         for (i = 0; i < num_regs; i++)
 538         {
 539                 arch_info[i].num = armv7m_regs[i].id;
 540                 arch_info[i].target = target;
 541                 arch_info[i].armv7m_common = armv7m;
 542                 reg_list[i].name = armv7m_regs[i].name;
 543                 reg_list[i].size = armv7m_regs[i].bits;
 544                 reg_list[i].value = calloc(1, 4);
 545                 reg_list[i].dirty = 0;
 546                 reg_list[i].valid = 0;
 547                 reg_list[i].type = &armv7m_reg_type;
 548                 reg_list[i].arch_info = &arch_info[i];
 549         }
 550
 551         return cache;
 552 }
 553
 554 /** Sets up target as a generic ARMv7-M core */
 555 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 556 {
 557         /* register arch-specific functions */
 558
 559         target->arch_info = armv7m;
 560         armv7m->read_core_reg = armv7m_read_core_reg;
 561         armv7m->write_core_reg = armv7m_write_core_reg;
 562
 563         return ERROR_OK;
 564 }
 565
 566 /** Generates a CRC32 checksum of a memory region. */
 567 int armv7m_checksum_memory(struct target *target,
 568                 uint32_t address, uint32_t count, uint32_t* checksum)
 569 {
 570         struct working_area *crc_algorithm;
 571         struct armv7m_algorithm armv7m_info;
 572         struct reg_param reg_params[2];
 573         int retval;
 574
 575         static const uint16_t cortex_m3_crc_code[] = {
 576                 0x4602,                                 /* mov  r2, r0 */
 577                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 578                 0x460B,                                 /* mov  r3, r1 */
 579                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 580                 0xE013,                                 /* b    ncomp */
 581                                                                 /* nbyte: */
 582                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 583                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 584                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 585
 586                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 587                                                                 /* loop: */
 588                 0x2800,                                 /* cmp          r0, #0 */
 589                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 590                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 591                 0x4630,                                 /* mov          r0, r6 */
 592                 0xBFB8,                                 /* it           lt */
 593                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 594                 0x2D08,                                 /* cmp          r5, #8 */
 595                 0xD1F4,                                 /* bne          loop */
 596
 597                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 598                                                                 /* ncomp: */
 599                 0x429C,                                 /* cmp  r4, r3 */
 600                 0xD1E9,                                 /* bne  nbyte */
 601                                                                 /* end: */
 602                 0xE7FE,                                 /* b    end */
 603                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 604         };
 605
 606         uint32_t i;
 607
 608         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 609         {
 610                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 611         }
 612
 613         /* convert flash writing code into a buffer in target endianness */
 614         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 615                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 616                 {
 617                         return retval;
 618                 }
 619
 620         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 621         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 622
 623         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 624         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 625
 626         buf_set_u32(reg_params[0].value, 0, 32, address);
 627         buf_set_u32(reg_params[1].value, 0, 32, count);
 628
 629         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 630                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 631         {
 632                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 633                 destroy_reg_param(&reg_params[0]);
 634                 destroy_reg_param(&reg_params[1]);
 635                 target_free_working_area(target, crc_algorithm);
 636                 return retval;
 637         }
 638
 639         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 640
 641         destroy_reg_param(&reg_params[0]);
 642         destroy_reg_param(&reg_params[1]);
 643
 644         target_free_working_area(target, crc_algorithm);
 645
 646         return ERROR_OK;
 647 }
 648
 649 /** Checks whether a memory region is zeroed. */
 650 int armv7m_blank_check_memory(struct target *target,
 651                 uint32_t address, uint32_t count, uint32_t* blank)
 652 {
 653         struct working_area *erase_check_algorithm;
 654         struct reg_param reg_params[3];
 655         struct armv7m_algorithm armv7m_info;
 656         int retval;
 657         uint32_t i;
 658
 659         static const uint16_t erase_check_code[] =
 660         {
 661                 /* loop: */
 662                 0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
 663                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 664                 0x3901,                         /* subs r1, r1, #1 */
 665                 0xD1F9,                         /* bne  loop */
 666                 /* end: */
 667                 0xE7FE,                         /* b    end */
 668         };
 669
 670         /* make sure we have a working area */
 671         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 672         {
 673                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 674         }
 675
 676         /* convert flash writing code into a buffer in target endianness */
 677         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 678                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 679
 680         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 681         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 682
 683         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 684         buf_set_u32(reg_params[0].value, 0, 32, address);
 685
 686         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 687         buf_set_u32(reg_params[1].value, 0, 32, count);
 688
 689         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 690         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 691
 692         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 693                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 694         {
 695                 destroy_reg_param(&reg_params[0]);
 696                 destroy_reg_param(&reg_params[1]);
 697                 destroy_reg_param(&reg_params[2]);
 698                 target_free_working_area(target, erase_check_algorithm);
 699                 return 0;
 700         }
 701
 702         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 703
 704         destroy_reg_param(&reg_params[0]);
 705         destroy_reg_param(&reg_params[1]);
 706         destroy_reg_param(&reg_params[2]);
 707
 708         target_free_working_area(target, erase_check_algorithm);
 709
 710         return ERROR_OK;
 711 }
 712
 713 /*--------------------------------------------------------------------------*/
 714
 715 /*
 716  * Only stuff below this line should need to verify that its target
 717  * is an ARMv7-M node.
 718  *
 719  * FIXME yet none of it _does_ verify target types yet!
 720  */
 721
 722
 723 /*
 724  * Return the debug ap baseaddress in hexadecimal;
 725  * no extra output to simplify script processing
 726  */
 727 COMMAND_HANDLER(handle_dap_baseaddr_command)
 728 {
 729         struct target *target = get_current_target(CMD_CTX);
 730         struct armv7m_common *armv7m = target_to_armv7m(target);
 731         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 732         uint32_t apsel, apselsave, baseaddr;
 733         int retval;
 734
 735         apselsave = swjdp->apsel;
 736         switch (CMD_ARGC) {
 737         case 0:
 738                 apsel = swjdp->apsel;
 739                 break;
 740         case 1:
 741                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
 742                 break;
 743         default:
 744                 return ERROR_COMMAND_SYNTAX_ERROR;
 745         }
 746
 747         if (apselsave != apsel)
 748                 dap_ap_select(swjdp, apsel);
 749
 750         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 751         retval = swjdp_transaction_endcheck(swjdp);
 752         command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr);
 753
 754         if (apselsave != apsel)
 755                 dap_ap_select(swjdp, apselsave);
 756
 757         return retval;
 758 }
 759
 760 /*
 761  * Return the debug ap id in hexadecimal;
 762  * no extra output to simplify script processing
 763  */
 764 COMMAND_HANDLER(handle_dap_apid_command)
 765 {
 766         struct target *target = get_current_target(CMD_CTX);
 767         struct armv7m_common *armv7m = target_to_armv7m(target);
 768         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 769
 770         return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 771 }
 772
 773 COMMAND_HANDLER(handle_dap_apsel_command)
 774 {
 775         struct target *target = get_current_target(CMD_CTX);
 776         struct armv7m_common *armv7m = target_to_armv7m(target);
 777         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 778
 779         return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 780 }
 781
 782 COMMAND_HANDLER(handle_dap_memaccess_command)
 783 {
 784         struct target *target = get_current_target(CMD_CTX);
 785         struct armv7m_common *armv7m = target_to_armv7m(target);
 786         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 787
 788         return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 789 }
 790
 791
 792 COMMAND_HANDLER(handle_dap_info_command)
 793 {
 794         struct target *target = get_current_target(CMD_CTX);
 795         struct armv7m_common *armv7m = target_to_armv7m(target);
 796         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 797         uint32_t apsel;
 798
 799         switch (CMD_ARGC) {
 800         case 0:
 801                 apsel = swjdp->apsel;
 802                 break;
 803         case 1:
 804                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
 805                 break;
 806         default:
 807                 return ERROR_COMMAND_SYNTAX_ERROR;
 808         }
 809
 810         return dap_info_command(CMD_CTX, swjdp, apsel);
 811 }
 812
 813 /** Registers commands used to access DAP resources. */
 814 int armv7m_register_commands(struct command_context *cmd_ctx)
 815 {
 816         struct command *arm_adi_v5_dap_cmd;
 817
 818         arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
 819                         NULL, COMMAND_ANY,
 820                         "cortex dap specific commands");
 821
 822         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
 823                         handle_dap_info_command, COMMAND_EXEC,
 824                         "Displays dap info for ap [num],"
 825                         "default currently selected AP");
 826         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
 827                         handle_dap_apsel_command, COMMAND_EXEC,
 828                         "Select a different AP [num] (default 0)");
 829         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
 830                         handle_dap_apid_command, COMMAND_EXEC,
 831                         "Displays id reg from AP [num], "
 832                         "default currently selected AP");
 833         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
 834                         handle_dap_baseaddr_command, COMMAND_EXEC,
 835                         "Displays debug base address from AP [num],"
 836                         "default currently selected AP");
 837         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
 838                         handle_dap_memaccess_command, COMMAND_EXEC,
 839                         "set/get number of extra tck for mem-ap "
 840                         "memory bus access [0-255]");
 841
 842         return ERROR_OK;
 843 }