1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
23 #include <helper/replacements.h>
26 #include "arm_disassembler.h"
29 #include <helper/binarybuffer.h>
30 #include <helper/command.h>
36 #include "armv8_opcodes.h"
38 #include "target_type.h"
40 static const char * const armv8_state_strings[] = {
41 "ARM", "Thumb", "Jazelle", "ThumbEE", "ARM64",
47 /* For user and system modes, these list indices for all registers.
48 * otherwise they're just indices for the shadow registers and SPSR.
50 unsigned short n_indices;
51 const uint8_t *indices;
52 } armv8_mode_data[] = {
53 /* These special modes are currently only supported
54 * by ARMv6M and ARMv7M profiles */
85 /** Map PSR mode bits to the name of an ARM processor operating mode. */
86 const char *armv8_mode_name(unsigned psr_mode)
88 for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
89 if (armv8_mode_data[i].psr == psr_mode)
90 return armv8_mode_data[i].name;
92 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
93 return "UNRECOGNIZED";
96 int armv8_mode_to_number(enum arm_mode mode)
100 /* map MODE_ANY to user mode */
133 LOG_ERROR("invalid mode value encountered %d", mode);
139 static int armv8_read_core_reg(struct target *target, struct reg *r,
140 int num, enum arm_mode mode)
144 struct arm_reg *armv8_core_reg;
145 struct armv8_common *armv8 = target_to_armv8(target);
147 assert(num < (int)armv8->arm.core_cache->num_regs);
149 armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
150 retval = armv8->load_core_reg_u64(target,
151 armv8_core_reg->num, ®_value);
153 buf_set_u64(armv8->arm.core_cache->reg_list[num].value, 0, 64, reg_value);
154 armv8->arm.core_cache->reg_list[num].valid = 1;
155 armv8->arm.core_cache->reg_list[num].dirty = 0;
161 static int armv8_write_core_reg(struct target *target, struct reg *r,
162 int num, enum arm_mode mode, target_addr_t value)
165 struct arm_reg *armv8_core_reg;
166 struct armv8_common *armv8 = target_to_armv8(target);
168 assert(num < (int)armv8->arm.core_cache->num_regs);
170 armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
171 retval = armv8->store_core_reg_u64(target,
174 if (retval != ERROR_OK) {
175 LOG_ERROR("JTAG failure");
176 armv8->arm.core_cache->reg_list[num].dirty = armv8->arm.core_cache->reg_list[num].valid;
177 return ERROR_JTAG_DEVICE_ERROR;
180 LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, value);
181 armv8->arm.core_cache->reg_list[num].valid = 1;
182 armv8->arm.core_cache->reg_list[num].dirty = 0;
188 * Configures host-side ARM records to reflect the specified CPSR.
189 * Later, code can use arm_reg_current() to map register numbers
190 * according to how they are exposed by this mode.
192 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
194 uint32_t mode = cpsr & 0x1F;
196 /* NOTE: this may be called very early, before the register
197 * cache is set up. We can't defend against many errors, in
198 * particular against CPSRs that aren't valid *here* ...
201 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
202 arm->cpsr->valid = 1;
203 arm->cpsr->dirty = 0;
206 /* Older ARMs won't have the J bit */
207 enum arm_state state = 0xFF;
209 if (((cpsr & 0x10) >> 4) == 0) {
210 state = ARM_STATE_AARCH64;
212 if (cpsr & (1 << 5)) { /* T */
213 if (cpsr & (1 << 24)) { /* J */
214 LOG_WARNING("ThumbEE -- incomplete support");
215 state = ARM_STATE_THUMB_EE;
217 state = ARM_STATE_THUMB;
219 if (cpsr & (1 << 24)) { /* J */
220 LOG_ERROR("Jazelle state handling is BROKEN!");
221 state = ARM_STATE_JAZELLE;
223 state = ARM_STATE_ARM;
226 arm->core_state = state;
227 if (arm->core_state == ARM_STATE_AARCH64) {
229 case SYSTEM_AAR64_MODE_EL0t:
230 arm->core_mode = ARMV8_64_EL0T;
232 case SYSTEM_AAR64_MODE_EL1t:
233 arm->core_mode = ARMV8_64_EL0T;
235 case SYSTEM_AAR64_MODE_EL1h:
236 arm->core_mode = ARMV8_64_EL1H;
238 case SYSTEM_AAR64_MODE_EL2t:
239 arm->core_mode = ARMV8_64_EL2T;
241 case SYSTEM_AAR64_MODE_EL2h:
242 arm->core_mode = ARMV8_64_EL2H;
244 case SYSTEM_AAR64_MODE_EL3t:
245 arm->core_mode = ARMV8_64_EL3T;
247 case SYSTEM_AAR64_MODE_EL3h:
248 arm->core_mode = ARMV8_64_EL3H;
251 LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
255 arm->core_mode = mode;
258 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
259 armv8_mode_name(arm->core_mode),
260 armv8_state_strings[arm->core_state]);
263 static void armv8_show_fault_registers(struct target *target)
268 static uint8_t armv8_pa_size(uint32_t ps)
291 LOG_INFO("Unknow physicall address size");
297 static int armv8_read_ttbcr(struct target *target)
299 struct armv8_common *armv8 = target_to_armv8(target);
300 struct arm_dpm *dpm = armv8->arm.dpm;
301 struct arm *arm = &armv8->arm;
305 int retval = dpm->prepare(dpm);
306 if (retval != ERROR_OK)
309 /* claaer ttrr1_used and ttbr0_mask */
310 memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
311 memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
313 switch (arm->core_mode) {
316 retval = dpm->instr_read_data_r0(dpm,
317 ARMV8_MRS(SYSTEM_TCR_EL3, 0),
319 retval += dpm->instr_read_data_r0_64(dpm,
320 ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
322 if (retval != ERROR_OK)
324 armv8->va_size = 64 - (ttbcr & 0x3F);
325 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
326 armv8->page_size = (ttbcr >> 14) & 3;
330 retval = dpm->instr_read_data_r0(dpm,
331 ARMV8_MRS(SYSTEM_TCR_EL2, 0),
333 retval += dpm->instr_read_data_r0_64(dpm,
334 ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
336 if (retval != ERROR_OK)
338 armv8->va_size = 64 - (ttbcr & 0x3F);
339 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
340 armv8->page_size = (ttbcr >> 14) & 3;
345 retval = dpm->instr_read_data_r0_64(dpm,
346 ARMV8_MRS(SYSTEM_TCR_EL1, 0),
348 armv8->va_size = 64 - (ttbcr_64 & 0x3F);
349 armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
350 armv8->page_size = (ttbcr_64 >> 14) & 3;
351 armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
352 armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
353 retval += dpm->instr_read_data_r0_64(dpm,
354 ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
356 if (retval != ERROR_OK)
360 LOG_ERROR("unknow core state");
364 if (retval != ERROR_OK)
368 LOG_INFO("ttb1 %s ,ttb0_mask %llx",
369 armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
370 armv8->armv8_mmu.ttbr0_mask);
372 if (armv8->armv8_mmu.ttbr1_used == 1) {
373 LOG_INFO("TTBR0 access above %" PRIx64,
374 (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
375 armv8->armv8_mmu.os_border = armv8->armv8_mmu.ttbr0_mask;
377 /* fix me , default is hard coded LINUX border */
378 armv8->armv8_mmu.os_border = 0xc0000000;
385 static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
387 LOG_ERROR("4K page Address translation need to add");
392 /* method adapted to cortex A : reused arm v4 v5 method*/
393 int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
395 int retval = ERROR_FAIL;
396 struct armv8_common *armv8 = target_to_armv8(target);
397 struct arm_dpm *dpm = armv8->arm.dpm;
399 retval = dpm->prepare(dpm);
400 retval += armv8_read_ttbcr(target);
401 if (retval != ERROR_OK)
403 if (armv8->page_size == 0)
404 return armv8_4K_translate(target, va, val);
411 /* V8 method VA TO PA */
412 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
413 target_addr_t *val, int meminfo)
418 static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
419 struct armv8_cache_common *armv8_cache)
421 if (armv8_cache->ctype == -1) {
422 command_print(cmd_ctx, "cache not yet identified");
426 command_print(cmd_ctx,
427 "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
428 armv8_cache->d_u_size.linelen,
429 armv8_cache->d_u_size.associativity,
430 armv8_cache->d_u_size.nsets,
431 armv8_cache->d_u_size.cachesize);
433 command_print(cmd_ctx,
434 "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
435 armv8_cache->i_size.linelen,
436 armv8_cache->i_size.associativity,
437 armv8_cache->i_size.nsets,
438 armv8_cache->i_size.cachesize);
443 static int _armv8_flush_all_data(struct target *target)
445 struct armv8_common *armv8 = target_to_armv8(target);
446 struct arm_dpm *dpm = armv8->arm.dpm;
447 struct armv8_cachesize *d_u_size =
448 &(armv8->armv8_mmu.armv8_cache.d_u_size);
449 int32_t c_way, c_index = d_u_size->index;
451 /* check that cache data is on at target halt */
452 if (!armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
453 LOG_INFO("flushed not performed :cache not on at target halt");
456 retval = dpm->prepare(dpm);
457 if (retval != ERROR_OK)
460 c_way = d_u_size->way;
462 uint32_t value = (c_index << d_u_size->index_shift)
463 | (c_way << d_u_size->way_shift);
465 /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
466 retval = dpm->instr_write_data_r0(dpm,
467 ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
469 if (retval != ERROR_OK)
472 } while (c_way >= 0);
474 } while (c_index >= 0);
477 LOG_ERROR("flushed failed");
482 static int armv8_flush_all_data(struct target *target)
484 int retval = ERROR_FAIL;
485 /* check that armv8_cache is correctly identify */
486 struct armv8_common *armv8 = target_to_armv8(target);
487 if (armv8->armv8_mmu.armv8_cache.ctype == -1) {
488 LOG_ERROR("trying to flush un-identified cache");
493 /* look if all the other target have been flushed in order to flush level
495 struct target_list *head;
498 while (head != (struct target_list *)NULL) {
500 if (curr->state == TARGET_HALTED) {
501 LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
502 retval = _armv8_flush_all_data(curr);
507 retval = _armv8_flush_all_data(target);
511 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
512 struct armv8_cache_common *armv8_cache)
514 if (armv8_cache->ctype == -1) {
515 command_print(cmd_ctx, "cache not yet identified");
519 if (armv8_cache->display_cache_info)
520 armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
524 /* retrieve core id cluster id */
525 static int armv8_read_mpidr(struct target *target)
527 int retval = ERROR_FAIL;
528 struct armv8_common *armv8 = target_to_armv8(target);
529 struct arm_dpm *dpm = armv8->arm.dpm;
531 retval = dpm->prepare(dpm);
532 if (retval != ERROR_OK)
534 /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
536 retval = dpm->instr_read_data_r0(dpm,
537 ARMV8_MRS(SYSTEM_MPIDR, 0),
539 if (retval != ERROR_OK)
542 armv8->multi_processor_system = (mpidr >> 30) & 1;
543 armv8->cluster_id = (mpidr >> 8) & 0xf;
544 armv8->cpu_id = mpidr & 0x3;
545 LOG_INFO("%s cluster %x core %x %s", target_name(target),
548 armv8->multi_processor_system == 0 ? "multi core" : "mono core");
551 LOG_ERROR("mpdir not in multiprocessor format");
560 int armv8_identify_cache(struct target *target)
562 /* read cache descriptor */
563 int retval = ERROR_FAIL;
564 struct armv8_common *armv8 = target_to_armv8(target);
565 struct arm_dpm *dpm = armv8->arm.dpm;
566 uint32_t cache_selected, clidr;
567 uint32_t cache_i_reg, cache_d_reg;
568 struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
569 armv8_read_ttbcr(target);
570 retval = dpm->prepare(dpm);
572 if (retval != ERROR_OK)
575 * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
576 retval = dpm->instr_read_data_r0(dpm,
577 ARMV8_MRS(SYSTEM_CLIDR, 0),
579 if (retval != ERROR_OK)
581 clidr = (clidr & 0x7000000) >> 23;
582 LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
583 if ((clidr / 2) > 1) {
584 /* FIXME not supported present in cortex A8 and later */
585 /* in cortex A7, A15 */
586 LOG_ERROR("cache l2 present :not supported");
588 /* retrieve selected cache*/
589 retval = dpm->instr_read_data_r0(dpm,
590 ARMV8_MRS(SYSTEM_CSSELR, 0),
592 if (retval != ERROR_OK)
596 /* select instruction cache
597 * [0] : 1 instruction cache selection , 0 data cache selection */
598 retval = dpm->instr_write_data_r0(dpm,
599 ARMV8_MRS(SYSTEM_CSSELR, 0),
601 if (retval != ERROR_OK)
605 * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
606 * [2:0] line size 001 eight word per line
607 * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
608 retval = dpm->instr_read_data_r0(dpm,
609 ARMV8_MRS(SYSTEM_CCSIDR, 0),
611 if (retval != ERROR_OK)
614 /* select data cache*/
615 retval = dpm->instr_write_data_r0(dpm,
616 ARMV8_MRS(SYSTEM_CSSELR, 0),
618 if (retval != ERROR_OK)
621 retval = dpm->instr_read_data_r0(dpm,
622 ARMV8_MRS(SYSTEM_CCSIDR, 0),
624 if (retval != ERROR_OK)
627 /* restore selected cache */
628 dpm->instr_write_data_r0(dpm,
629 ARMV8_MRS(SYSTEM_CSSELR, 0),
632 if (retval != ERROR_OK)
637 cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
638 cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
639 cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
640 cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
641 /* compute info for set way operation on cache */
642 cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
643 cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
644 cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
645 cache->d_u_size.way_shift = cache->d_u_size.way + 1;
648 while (((cache->d_u_size.way_shift >> i) & 1) != 1)
650 cache->d_u_size.way_shift = 32-i;
653 LOG_INFO("data cache index %d << %d, way %d << %d",
654 cache->d_u_size.index, cache->d_u_size.index_shift,
656 cache->d_u_size.way_shift);
658 LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
659 cache->d_u_size.linelen,
660 cache->d_u_size.cachesize,
661 cache->d_u_size.associativity);
663 cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
664 cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
665 cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
666 cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
667 /* compute info for set way operation on cache */
668 cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
669 cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
670 cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
671 cache->i_size.way_shift = cache->i_size.way + 1;
674 while (((cache->i_size.way_shift >> i) & 1) != 1)
676 cache->i_size.way_shift = 32-i;
679 LOG_INFO("instruction cache index %d << %d, way %d << %d",
680 cache->i_size.index, cache->i_size.index_shift,
681 cache->i_size.way, cache->i_size.way_shift);
683 LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
684 cache->i_size.linelen,
685 cache->i_size.cachesize,
686 cache->i_size.associativity);
688 /* if no l2 cache initialize l1 data cache flush function function */
689 if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
690 armv8->armv8_mmu.armv8_cache.display_cache_info =
691 armv8_handle_inner_cache_info_command;
692 armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
693 armv8_flush_all_data;
695 armv8->armv8_mmu.armv8_cache.ctype = 0;
699 armv8_read_mpidr(target);
704 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
706 struct arm *arm = &armv8->arm;
707 arm->arch_info = armv8;
708 target->arch_info = &armv8->arm;
709 /* target is useful in all function arm v4 5 compatible */
710 armv8->arm.target = target;
711 armv8->arm.common_magic = ARM_COMMON_MAGIC;
712 armv8->common_magic = ARMV8_COMMON_MAGIC;
714 arm->read_core_reg = armv8_read_core_reg;
716 arm->write_core_reg = armv8_write_core_reg;
719 armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
720 armv8->armv8_mmu.armv8_cache.ctype = -1;
721 armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
722 armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
726 int armv8_aarch64_state(struct target *target)
728 struct arm *arm = target_to_arm(target);
730 if (arm->common_magic != ARM_COMMON_MAGIC) {
731 LOG_ERROR("BUG: called for a non-ARM target");
735 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
736 "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
737 armv8_state_strings[arm->core_state],
738 debug_reason_name(target),
739 armv8_mode_name(arm->core_mode),
740 buf_get_u32(arm->cpsr->value, 0, 32),
741 buf_get_u64(arm->pc->value, 0, 64),
742 arm->is_semihosting ? ", semihosting" : "");
747 int armv8_arch_state(struct target *target)
749 static const char * const state[] = {
750 "disabled", "enabled"
753 struct armv8_common *armv8 = target_to_armv8(target);
754 struct arm *arm = &armv8->arm;
756 if (armv8->common_magic != ARMV8_COMMON_MAGIC) {
757 LOG_ERROR("BUG: called for a non-Armv8 target");
758 return ERROR_COMMAND_SYNTAX_ERROR;
761 if (arm->core_state == ARM_STATE_AARCH64)
762 armv8_aarch64_state(target);
764 arm_arch_state(target);
766 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
767 state[armv8->armv8_mmu.mmu_enabled],
768 state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
769 state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
771 if (arm->core_mode == ARM_MODE_ABT)
772 armv8_show_fault_registers(target);
773 if (target->debug_reason == DBG_REASON_WATCHPOINT)
774 LOG_USER("Watchpoint triggered at PC %#08x",
775 (unsigned) armv8->dpm.wp_pc);
780 static const struct {
788 { ARMV8_R0, "x0", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
789 { ARMV8_R1, "x1", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
790 { ARMV8_R2, "x2", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
791 { ARMV8_R3, "x3", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
792 { ARMV8_R4, "x4", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
793 { ARMV8_R5, "x5", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
794 { ARMV8_R6, "x6", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
795 { ARMV8_R7, "x7", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
796 { ARMV8_R8, "x8", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
797 { ARMV8_R9, "x9", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
798 { ARMV8_R10, "x10", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
799 { ARMV8_R11, "x11", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
800 { ARMV8_R12, "x12", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
801 { ARMV8_R13, "x13", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
802 { ARMV8_R14, "x14", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
803 { ARMV8_R15, "x15", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
804 { ARMV8_R16, "x16", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
805 { ARMV8_R17, "x17", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
806 { ARMV8_R18, "x18", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
807 { ARMV8_R19, "x19", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
808 { ARMV8_R20, "x20", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
809 { ARMV8_R21, "x21", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
810 { ARMV8_R22, "x22", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
811 { ARMV8_R23, "x23", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
812 { ARMV8_R24, "x24", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
813 { ARMV8_R25, "x25", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
814 { ARMV8_R26, "x26", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
815 { ARMV8_R27, "x27", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
816 { ARMV8_R28, "x28", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
817 { ARMV8_R29, "x29", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
818 { ARMV8_R30, "x30", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
820 { ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
821 { ARMV8_PC, "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
823 { ARMV8_xPSR, "CPSR", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
826 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
829 static int armv8_get_core_reg(struct reg *reg)
832 struct arm_reg *armv8_reg = reg->arch_info;
833 struct target *target = armv8_reg->target;
834 struct arm *arm = target_to_arm(target);
836 if (target->state != TARGET_HALTED)
837 return ERROR_TARGET_NOT_HALTED;
839 retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
844 static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
846 struct arm_reg *armv8_reg = reg->arch_info;
847 struct target *target = armv8_reg->target;
848 uint64_t value = buf_get_u64(buf, 0, 64);
850 if (target->state != TARGET_HALTED)
851 return ERROR_TARGET_NOT_HALTED;
853 buf_set_u64(reg->value, 0, 64, value);
860 static const struct reg_arch_type armv8_reg_type = {
861 .get = armv8_get_core_reg,
862 .set = armv8_set_core_reg,
865 /** Builds cache of architecturally defined registers. */
866 struct reg_cache *armv8_build_reg_cache(struct target *target)
868 struct armv8_common *armv8 = target_to_armv8(target);
869 struct arm *arm = &armv8->arm;
870 int num_regs = ARMV8_NUM_REGS;
871 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
872 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
873 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
874 struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
875 struct reg_feature *feature;
878 /* Build the process context cache */
879 cache->name = "arm v8 registers";
881 cache->reg_list = reg_list;
882 cache->num_regs = num_regs;
885 for (i = 0; i < num_regs; i++) {
886 arch_info[i].num = armv8_regs[i].id;
887 arch_info[i].target = target;
888 arch_info[i].arm = arm;
890 reg_list[i].name = armv8_regs[i].name;
891 reg_list[i].size = armv8_regs[i].bits;
892 reg_list[i].value = calloc(1, 4);
893 reg_list[i].dirty = 0;
894 reg_list[i].valid = 0;
895 reg_list[i].type = &armv8_reg_type;
896 reg_list[i].arch_info = &arch_info[i];
898 reg_list[i].group = armv8_regs[i].group;
899 reg_list[i].number = i;
900 reg_list[i].exist = true;
901 reg_list[i].caller_save = true; /* gdb defaults to true */
903 feature = calloc(1, sizeof(struct reg_feature));
905 feature->name = armv8_regs[i].feature;
906 reg_list[i].feature = feature;
908 LOG_ERROR("unable to allocate feature list");
910 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
911 if (reg_list[i].reg_data_type)
912 reg_list[i].reg_data_type->type = armv8_regs[i].type;
914 LOG_ERROR("unable to allocate reg type list");
917 arm->cpsr = reg_list + ARMV8_xPSR;
918 arm->pc = reg_list + ARMV8_PC;
919 arm->core_cache = cache;
924 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
928 if (regnum > (ARMV8_LAST_REG - 1))
931 r = arm->core_cache->reg_list + regnum;
935 const struct command_registration armv8_command_handlers[] = {
937 .chain = dap_command_handlers,
939 COMMAND_REGISTRATION_DONE
943 int armv8_get_gdb_reg_list(struct target *target,
944 struct reg **reg_list[], int *reg_list_size,
945 enum target_register_class reg_class)
947 struct arm *arm = target_to_arm(target);
951 case REG_CLASS_GENERAL:
953 *reg_list_size = ARMV8_LAST_REG;
954 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
956 for (i = 0; i < ARMV8_LAST_REG; i++)
957 (*reg_list)[i] = armv8_reg_current(arm, i);
962 LOG_ERROR("not a valid register class type in query.");