1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
116 enum run_control_op {
117 ARMV8_RUNCONTROL_UNKNOWN = 0,
118 ARMV8_RUNCONTROL_RESUME = 1,
119 ARMV8_RUNCONTROL_HALT = 2,
120 ARMV8_RUNCONTROL_STEP = 3,
123 #define ARMV8_COMMON_MAGIC 0x0A450AAA
125 /* VA to PA translation operations opc2 values*/
134 /* L210/L220 cache controller support */
135 struct armv8_l2x_cache {
140 struct armv8_cachesize {
142 /* cache dimensionning */
144 uint32_t associativity;
147 /* info for set way operation on cache */
149 uint32_t index_shift;
154 /* information about one architecture cache at any level */
155 struct armv8_arch_cache {
156 int ctype; /* cache type, CLIDR encoding */
157 struct armv8_cachesize d_u_size; /* data cache */
158 struct armv8_cachesize i_size; /* instruction cache */
161 struct armv8_cache_common {
166 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
168 int d_u_cache_enabled;
170 /* l2 external unified cache if some */
172 int (*flush_all_data_cache)(struct target *target);
173 int (*display_cache_info)(struct command_context *cmd_ctx,
174 struct armv8_cache_common *armv8_cache);
177 struct armv8_mmu_common {
178 /* following field mmu working way */
179 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
180 uint64_t ttbr0_mask;/* masked to be used */
182 uint32_t ttbcr; /* cache for ttbcr register */
183 uint32_t ttbr_mask[2];
184 uint32_t ttbr_range[2];
186 int (*read_physical_memory)(struct target *target, target_addr_t address,
187 uint32_t size, uint32_t count, uint8_t *buffer);
188 struct armv8_cache_common armv8_cache;
189 uint32_t mmu_enabled;
192 struct armv8_common {
195 struct reg_cache *core_cache;
197 /* Core Debug Unit */
200 struct adiv5_ap *debug_ap;
202 const uint32_t *opcodes;
205 uint8_t multi_processor_system;
209 /* armv8 aarch64 need below information for page translation */
215 struct armv8_mmu_common armv8_mmu;
219 /* last run-control command issued to this target (resume, halt, step) */
220 enum run_control_op last_run_control_op;
222 /* Direct processor core register read and writes */
223 int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
224 int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
226 /* SIMD/FPU registers read/write interface */
227 int (*read_reg_u128)(struct armv8_common *armv8, int num,
228 uint64_t *lvalue, uint64_t *hvalue);
229 int (*write_reg_u128)(struct armv8_common *armv8, int num,
230 uint64_t lvalue, uint64_t hvalue);
232 int (*examine_debug_reason)(struct target *target);
233 int (*post_debug_entry)(struct target *target);
235 void (*pre_restore_context)(struct target *target);
238 static inline struct armv8_common *
239 target_to_armv8(struct target *target)
241 return container_of(target->arch_info, struct armv8_common, arm);
244 static inline bool is_armv8(struct armv8_common *armv8)
246 return armv8->common_magic == ARMV8_COMMON_MAGIC;
249 /* register offsets from armv8.debug_base */
250 #define CPUV8_DBG_MAINID0 0xD00
251 #define CPUV8_DBG_CPUFEATURE0 0xD20
252 #define CPUV8_DBG_DBGFEATURE0 0xD28
253 #define CPUV8_DBG_MEMFEATURE0 0xD38
255 #define CPUV8_DBG_LOCKACCESS 0xFB0
256 #define CPUV8_DBG_LOCKSTATUS 0xFB4
258 #define CPUV8_DBG_EDESR 0x20
259 #define CPUV8_DBG_EDECR 0x24
260 #define CPUV8_DBG_WFAR0 0x30
261 #define CPUV8_DBG_WFAR1 0x34
262 #define CPUV8_DBG_DSCR 0x088
263 #define CPUV8_DBG_DRCR 0x090
264 #define CPUV8_DBG_PRCR 0x310
265 #define CPUV8_DBG_PRSR 0x314
267 #define CPUV8_DBG_DTRRX 0x080
268 #define CPUV8_DBG_ITR 0x084
269 #define CPUV8_DBG_SCR 0x088
270 #define CPUV8_DBG_DTRTX 0x08c
272 #define CPUV8_DBG_BVR_BASE 0x400
273 #define CPUV8_DBG_BCR_BASE 0x408
274 #define CPUV8_DBG_WVR_BASE 0x800
275 #define CPUV8_DBG_WCR_BASE 0x808
276 #define CPUV8_DBG_VCR 0x01C
278 #define CPUV8_DBG_OSLAR 0x300
280 #define CPUV8_DBG_AUTHSTATUS 0xFB8
282 #define PAGE_SIZE_4KB 0x1000
283 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
284 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
285 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
286 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
288 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
289 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
290 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
291 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
293 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
295 int armv8_arch_state(struct target *target);
296 int armv8_read_mpidr(struct armv8_common *armv8);
297 int armv8_identify_cache(struct armv8_common *armv8);
298 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
299 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
300 target_addr_t *val, int meminfo);
301 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
303 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
304 struct armv8_cache_common *armv8_cache);
306 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
308 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
315 case ARM_MODE_ABT: /* FIXME: EL3? */
316 case ARM_MODE_IRQ: /* FIXME: EL3? */
317 case ARM_MODE_FIQ: /* FIXME: EL3? */
318 case ARM_MODE_UND: /* FIXME: EL3? */
319 case ARM_MODE_SYS: /* FIXME: EL3? */
321 /* case ARM_MODE_HYP:
326 /* all Aarch64 modes */
328 return (core_mode >> 2) & 3;
332 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
333 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
335 extern void armv8_free_reg_cache(struct target *target);
337 extern const struct command_registration armv8_command_handlers[];
339 #endif /* OPENOCD_TARGET_ARMV8_H */