1 # The IMX31PDK eval board has a single IMX31 chip
2 source [find target/imx31.cfg]
3 $_TARGETNAME configure -event gdb-attach { reset init }
4 $_TARGETNAME configure -event reset-init { imx31pdk_init }
6 proc imx31pdk_init { } {
7 # This setup puts RAM at 0x80000000
9 # reset the board correctly
13 # ========================================
15 # ========================================
17 mww 0x53F80000 0x074B0B7D
21 # ========================================
22 # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
23 # ========================================
24 mww 0x53F80004 0xFF871D50
25 mww 0x53F80010 0x00271C1B
27 # ========================================
28 # Configure CPLD on CS5
29 # ========================================
30 mww 0xb8002050 0x0000DCF6
31 mww 0xb8002054 0x444A4541
32 mww 0xb8002058 0x44443302
34 # ========================================
36 # ========================================
39 # ========================================
41 # ========================================
44 # ========================================
46 # ========================================
49 # ========================================
51 # ========================================
54 # ========================================
56 # ========================================
59 # ========================================
60 # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
61 # ========================================
85 # ========================================
86 # Initialization script for 32 bit DDR on MX31 PDK
87 # ========================================
88 mww 0xB8001010 0x00000004
89 mww 0xB8001004 0x006ac73a
90 mww 0xB8001000 0x92100000
91 mww 0x80000f00 0x12344321
92 mww 0xB8001000 0xa2100000
93 mww 0x80000000 0x12344321
94 mww 0x80000000 0x12344321
95 mww 0xB8001000 0xb2100000
98 mww 0xB8001000 0x82226080
99 mww 0x80000000 0xDEADBEEF
100 mww 0xB8001010 0x0000000c