git.sur5r.net Git - openocd/blob - src/target/cortex_a.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   Copyright (C) 2010 Øyvind Harboe                                      *
  15  *   oyvind.harboe@zylin.com                                               *
  16  *                                                                         *
  17  *   Copyright (C) ST-Ericsson SA 2011                                     *
  18  *   michel.jaouen@stericsson.com : smp minimum support                    *
  19  *                                                                         *
  20  *   Copyright (C) Broadcom 2012                                           *
  21  *   ehunter@broadcom.com : Cortex R4 support                              *
  22  *                                                                         *
  23  *   Copyright (C) 2013 Kamal Dasu                                         *
  24  *   kdasu.kdev@gmail.com                                                  *
  25  *                                                                         *
  26  *   This program is free software; you can redistribute it and/or modify  *
  27  *   it under the terms of the GNU General Public License as published by  *
  28  *   the Free Software Foundation; either version 2 of the License, or     *
  29  *   (at your option) any later version.                                   *
  30  *                                                                         *
  31  *   This program is distributed in the hope that it will be useful,       *
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  34  *   GNU General Public License for more details.                          *
  35  *                                                                         *
  36  *   You should have received a copy of the GNU General Public License     *
  37  *   along with this program; if not, write to the                         *
  38  *   Free Software Foundation, Inc.,                                       *
  39  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  40  *                                                                         *
  41  *   Cortex-A8(tm) TRM, ARM DDI 0344H                                      *
  42  *   Cortex-A9(tm) TRM, ARM DDI 0407F                                      *
  43  *   Cortex-A4(tm) TRM, ARM DDI 0363E                                      *
  44  *   Cortex-A15(tm)TRM, ARM DDI 0438C                                      *
  45  *                                                                         *
  46  ***************************************************************************/
  47
  48 #ifdef HAVE_CONFIG_H
  49 #include "config.h"
  50 #endif
  51
  52 #include "breakpoints.h"
  53 #include "cortex_a.h"
  54 #include "register.h"
  55 #include "target_request.h"
  56 #include "target_type.h"
  57 #include "arm_opcodes.h"
  58 #include <helper/time_support.h>
  59
  60 static int cortex_a_poll(struct target *target);
  61 static int cortex_a_debug_entry(struct target *target);
  62 static int cortex_a_restore_context(struct target *target, bool bpwp);
  63 static int cortex_a_set_breakpoint(struct target *target,
  64         struct breakpoint *breakpoint, uint8_t matchmode);
  65 static int cortex_a_set_context_breakpoint(struct target *target,
  66         struct breakpoint *breakpoint, uint8_t matchmode);
  67 static int cortex_a_set_hybrid_breakpoint(struct target *target,
  68         struct breakpoint *breakpoint);
  69 static int cortex_a_unset_breakpoint(struct target *target,
  70         struct breakpoint *breakpoint);
  71 static int cortex_a_dap_read_coreregister_u32(struct target *target,
  72         uint32_t *value, int regnum);
  73 static int cortex_a_dap_write_coreregister_u32(struct target *target,
  74         uint32_t value, int regnum);
  75 static int cortex_a_mmu(struct target *target, int *enabled);
  76 static int cortex_a_virt2phys(struct target *target,
  77         uint32_t virt, uint32_t *phys);
  78 static int cortex_a_read_apb_ab_memory(struct target *target,
  79         uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  80
  81
  82 /*  restore cp15_control_reg at resume */
  83 static int cortex_a_restore_cp15_control_reg(struct target *target)
  84 {
  85         int retval = ERROR_OK;
  86         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
  87         struct armv7a_common *armv7a = target_to_armv7a(target);
  88
  89         if (cortex_a->cp15_control_reg != cortex_a->cp15_control_reg_curr) {
  90                 cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
  91                 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
  92                 retval = armv7a->arm.mcr(target, 15,
  93                                 0, 0,   /* op1, op2 */
  94                                 1, 0,   /* CRn, CRm */
  95                                 cortex_a->cp15_control_reg);
  96         }
  97         return retval;
  98 }
  99
 100 /*  check address before cortex_a_apb read write access with mmu on
 101  *  remove apb predictible data abort */
 102 static int cortex_a_check_address(struct target *target, uint32_t address)
 103 {
 104         struct armv7a_common *armv7a = target_to_armv7a(target);
 105         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 106         uint32_t os_border = armv7a->armv7a_mmu.os_border;
 107         if ((address < os_border) &&
 108                 (armv7a->arm.core_mode == ARM_MODE_SVC)) {
 109                 LOG_ERROR("%" PRIx32 " access in userspace and target in supervisor", address);
 110                 return ERROR_FAIL;
 111         }
 112         if ((address >= os_border) &&
 113                 (cortex_a->curr_mode != ARM_MODE_SVC)) {
 114                 dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
 115                 cortex_a->curr_mode = ARM_MODE_SVC;
 116                 LOG_INFO("%" PRIx32 " access in kernel space and target not in supervisor",
 117                         address);
 118                 return ERROR_OK;
 119         }
 120         if ((address < os_border) &&
 121                 (cortex_a->curr_mode == ARM_MODE_SVC)) {
 122                 dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
 123                 cortex_a->curr_mode = ARM_MODE_ANY;
 124         }
 125         return ERROR_OK;
 126 }
 127 /*  modify cp15_control_reg in order to enable or disable mmu for :
 128  *  - virt2phys address conversion
 129  *  - read or write memory in phys or virt address */
 130 static int cortex_a_mmu_modify(struct target *target, int enable)
 131 {
 132         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 133         struct armv7a_common *armv7a = target_to_armv7a(target);
 134         int retval = ERROR_OK;
 135         if (enable) {
 136                 /*  if mmu enabled at target stop and mmu not enable */
 137                 if (!(cortex_a->cp15_control_reg & 0x1U)) {
 138                         LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
 139                         return ERROR_FAIL;
 140                 }
 141                 if (!(cortex_a->cp15_control_reg_curr & 0x1U)) {
 142                         cortex_a->cp15_control_reg_curr |= 0x1U;
 143                         retval = armv7a->arm.mcr(target, 15,
 144                                         0, 0,   /* op1, op2 */
 145                                         1, 0,   /* CRn, CRm */
 146                                         cortex_a->cp15_control_reg_curr);
 147                 }
 148         } else {
 149                 if ((cortex_a->cp15_control_reg_curr & 0x1U)) {
 150                         if (cortex_a->cp15_control_reg_curr & 0x4U) {
 151                                 /* data cache is active */
 152                                 cortex_a->cp15_control_reg_curr &= ~0x4U;
 153                                 /* flush data cache armv7 function to be called */
 154                                 if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
 155                                         armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
 156                         }
 157                         cortex_a->cp15_control_reg_curr &= ~0x1U;
 158                         retval = armv7a->arm.mcr(target, 15,
 159                                         0, 0,   /* op1, op2 */
 160                                         1, 0,   /* CRn, CRm */
 161                                         cortex_a->cp15_control_reg_curr);
 162                 }
 163         }
 164         return retval;
 165 }
 166
 167 /*
 168  * Cortex-A Basic debug access, very low level assumes state is saved
 169  */
 170 static int cortex_a8_init_debug_access(struct target *target)
 171 {
 172         struct armv7a_common *armv7a = target_to_armv7a(target);
 173         struct adiv5_dap *swjdp = armv7a->arm.dap;
 174         int retval;
 175
 176         LOG_DEBUG(" ");
 177
 178         /* Unlocking the debug registers for modification
 179          * The debugport might be uninitialised so try twice */
 180         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 181                         armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 182         if (retval != ERROR_OK) {
 183                 /* try again */
 184                 retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 185                                 armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 186                 if (retval == ERROR_OK)
 187                         LOG_USER(
 188                                 "Locking debug access failed on first, but succeeded on second try.");
 189         }
 190
 191         return retval;
 192 }
 193
 194 /*
 195  * Cortex-A Basic debug access, very low level assumes state is saved
 196  */
 197 static int cortex_a_init_debug_access(struct target *target)
 198 {
 199         struct armv7a_common *armv7a = target_to_armv7a(target);
 200         struct adiv5_dap *swjdp = armv7a->arm.dap;
 201         int retval;
 202         uint32_t dbg_osreg;
 203         uint32_t cortex_part_num;
 204         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 205
 206         LOG_DEBUG(" ");
 207         cortex_part_num = (cortex_a->cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >>
 208                 CORTEX_A_MIDR_PARTNUM_SHIFT;
 209
 210         switch (cortex_part_num) {
 211         case CORTEX_A7_PARTNUM:
 212         case CORTEX_A15_PARTNUM:
 213                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 214                                                     armv7a->debug_base + CPUDBG_OSLSR,
 215                                                     &dbg_osreg);
 216                 if (retval != ERROR_OK)
 217                         return retval;
 218
 219                 LOG_DEBUG("DBGOSLSR  0x%" PRIx32, dbg_osreg);
 220
 221                 if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
 222                         /* Unlocking the DEBUG OS registers for modification */
 223                         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 224                                                              armv7a->debug_base + CPUDBG_OSLAR,
 225                                                              0);
 226                 break;
 227
 228         case CORTEX_A5_PARTNUM:
 229         case CORTEX_A8_PARTNUM:
 230         case CORTEX_A9_PARTNUM:
 231         default:
 232                 retval = cortex_a8_init_debug_access(target);
 233         }
 234
 235         if (retval != ERROR_OK)
 236                 return retval;
 237         /* Clear Sticky Power Down status Bit in PRSR to enable access to
 238            the registers in the Core Power Domain */
 239         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 240                         armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
 241         LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR  0x%" PRIx32, target->coreid, dbg_osreg);
 242
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         /* Disable cacheline fills and force cache write-through in debug state */
 247         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 248                         armv7a->debug_base + CPUDBG_DSCCR, 0);
 249         if (retval != ERROR_OK)
 250                 return retval;
 251
 252         /* Disable TLB lookup and refill/eviction in debug state */
 253         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 254                         armv7a->debug_base + CPUDBG_DSMCR, 0);
 255         if (retval != ERROR_OK)
 256                 return retval;
 257
 258         /* Enabling of instruction execution in debug mode is done in debug_entry code */
 259
 260         /* Resync breakpoint registers */
 261
 262         /* Since this is likely called from init or reset, update target state information*/
 263         return cortex_a_poll(target);
 264 }
 265
 266 static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool force)
 267 {
 268         /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
 269          * Writes final value of DSCR into *dscr. Pass force to force always
 270          * reading DSCR at least once. */
 271         struct armv7a_common *armv7a = target_to_armv7a(target);
 272         struct adiv5_dap *swjdp = armv7a->arm.dap;
 273         long long then = timeval_ms();
 274         while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
 275                 force = false;
 276                 int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 277                                 armv7a->debug_base + CPUDBG_DSCR, dscr);
 278                 if (retval != ERROR_OK) {
 279                         LOG_ERROR("Could not read DSCR register");
 280                         return retval;
 281                 }
 282                 if (timeval_ms() > then + 1000) {
 283                         LOG_ERROR("Timeout waiting for InstrCompl=1");
 284                         return ERROR_FAIL;
 285                 }
 286         }
 287         return ERROR_OK;
 288 }
 289
 290 /* To reduce needless round-trips, pass in a pointer to the current
 291  * DSCR value.  Initialize it to zero if you just need to know the
 292  * value on return from this function; or DSCR_INSTR_COMP if you
 293  * happen to know that no instruction is pending.
 294  */
 295 static int cortex_a_exec_opcode(struct target *target,
 296         uint32_t opcode, uint32_t *dscr_p)
 297 {
 298         uint32_t dscr;
 299         int retval;
 300         struct armv7a_common *armv7a = target_to_armv7a(target);
 301         struct adiv5_dap *swjdp = armv7a->arm.dap;
 302
 303         dscr = dscr_p ? *dscr_p : 0;
 304
 305         LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 306
 307         /* Wait for InstrCompl bit to be set */
 308         retval = cortex_a_wait_instrcmpl(target, dscr_p, false);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311
 312         retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
 313                         armv7a->debug_base + CPUDBG_ITR, opcode);
 314         if (retval != ERROR_OK)
 315                 return retval;
 316
 317         long long then = timeval_ms();
 318         do {
 319                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 320                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
 321                 if (retval != ERROR_OK) {
 322                         LOG_ERROR("Could not read DSCR register");
 323                         return retval;
 324                 }
 325                 if (timeval_ms() > then + 1000) {
 326                         LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
 327                         return ERROR_FAIL;
 328                 }
 329         } while ((dscr & DSCR_INSTR_COMP) == 0);        /* Wait for InstrCompl bit to be set */
 330
 331         if (dscr_p)
 332                 *dscr_p = dscr;
 333
 334         return retval;
 335 }
 336
 337 /**************************************************************************
 338 Read core register with very few exec_opcode, fast but needs work_area.
 339 This can cause problems with MMU active.
 340 **************************************************************************/
 341 static int cortex_a_read_regs_through_mem(struct target *target, uint32_t address,
 342         uint32_t *regfile)
 343 {
 344         int retval = ERROR_OK;
 345         struct armv7a_common *armv7a = target_to_armv7a(target);
 346         struct adiv5_dap *swjdp = armv7a->arm.dap;
 347
 348         retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
 349         if (retval != ERROR_OK)
 350                 return retval;
 351         retval = cortex_a_dap_write_coreregister_u32(target, address, 0);
 352         if (retval != ERROR_OK)
 353                 return retval;
 354         retval = cortex_a_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
 355         if (retval != ERROR_OK)
 356                 return retval;
 357
 358         retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap,
 359                         (uint8_t *)(&regfile[1]), 4, 15, address);
 360
 361         return retval;
 362 }
 363
 364 static int cortex_a_dap_read_coreregister_u32(struct target *target,
 365         uint32_t *value, int regnum)
 366 {
 367         int retval = ERROR_OK;
 368         uint8_t reg = regnum&0xFF;
 369         uint32_t dscr = 0;
 370         struct armv7a_common *armv7a = target_to_armv7a(target);
 371         struct adiv5_dap *swjdp = armv7a->arm.dap;
 372
 373         if (reg > 17)
 374                 return retval;
 375
 376         if (reg < 15) {
 377                 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
 378                 retval = cortex_a_exec_opcode(target,
 379                                 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
 380                                 &dscr);
 381                 if (retval != ERROR_OK)
 382                         return retval;
 383         } else if (reg == 15) {
 384                 /* "MOV r0, r15"; then move r0 to DCCTX */
 385                 retval = cortex_a_exec_opcode(target, 0xE1A0000F, &dscr);
 386                 if (retval != ERROR_OK)
 387                         return retval;
 388                 retval = cortex_a_exec_opcode(target,
 389                                 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
 390                                 &dscr);
 391                 if (retval != ERROR_OK)
 392                         return retval;
 393         } else {
 394                 /* "MRS r0, CPSR" or "MRS r0, SPSR"
 395                  * then move r0 to DCCTX
 396                  */
 397                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
 398                 if (retval != ERROR_OK)
 399                         return retval;
 400                 retval = cortex_a_exec_opcode(target,
 401                                 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
 402                                 &dscr);
 403                 if (retval != ERROR_OK)
 404                         return retval;
 405         }
 406
 407         /* Wait for DTRRXfull then read DTRRTX */
 408         long long then = timeval_ms();
 409         while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 410                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 411                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
 412                 if (retval != ERROR_OK)
 413                         return retval;
 414                 if (timeval_ms() > then + 1000) {
 415                         LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
 416                         return ERROR_FAIL;
 417                 }
 418         }
 419
 420         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 421                         armv7a->debug_base + CPUDBG_DTRTX, value);
 422         LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 423
 424         return retval;
 425 }
 426
 427 static int cortex_a_dap_write_coreregister_u32(struct target *target,
 428         uint32_t value, int regnum)
 429 {
 430         int retval = ERROR_OK;
 431         uint8_t Rd = regnum&0xFF;
 432         uint32_t dscr;
 433         struct armv7a_common *armv7a = target_to_armv7a(target);
 434         struct adiv5_dap *swjdp = armv7a->arm.dap;
 435
 436         LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
 437
 438         /* Check that DCCRX is not full */
 439         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 440                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
 441         if (retval != ERROR_OK)
 442                 return retval;
 443         if (dscr & DSCR_DTR_RX_FULL) {
 444                 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 445                 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode  0xEE100E15 */
 446                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
 447                                 &dscr);
 448                 if (retval != ERROR_OK)
 449                         return retval;
 450         }
 451
 452         if (Rd > 17)
 453                 return retval;
 454
 455         /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
 456         LOG_DEBUG("write DCC 0x%08" PRIx32, value);
 457         retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap,
 458                         armv7a->debug_base + CPUDBG_DTRRX, value);
 459         if (retval != ERROR_OK)
 460                 return retval;
 461
 462         if (Rd < 15) {
 463                 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
 464                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
 465                                 &dscr);
 466
 467                 if (retval != ERROR_OK)
 468                         return retval;
 469         } else if (Rd == 15) {
 470                 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
 471                  * then "mov r15, r0"
 472                  */
 473                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
 474                                 &dscr);
 475                 if (retval != ERROR_OK)
 476                         return retval;
 477                 retval = cortex_a_exec_opcode(target, 0xE1A0F000, &dscr);
 478                 if (retval != ERROR_OK)
 479                         return retval;
 480         } else {
 481                 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
 482                  * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
 483                  */
 484                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
 485                                 &dscr);
 486                 if (retval != ERROR_OK)
 487                         return retval;
 488                 retval = cortex_a_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
 489                                 &dscr);
 490                 if (retval != ERROR_OK)
 491                         return retval;
 492
 493                 /* "Prefetch flush" after modifying execution status in CPSR */
 494                 if (Rd == 16) {
 495                         retval = cortex_a_exec_opcode(target,
 496                                         ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
 497                                         &dscr);
 498                         if (retval != ERROR_OK)
 499                                 return retval;
 500                 }
 501         }
 502
 503         return retval;
 504 }
 505
 506 /* Write to memory mapped registers directly with no cache or mmu handling */
 507 static int cortex_a_dap_write_memap_register_u32(struct target *target,
 508         uint32_t address,
 509         uint32_t value)
 510 {
 511         int retval;
 512         struct armv7a_common *armv7a = target_to_armv7a(target);
 513         struct adiv5_dap *swjdp = armv7a->arm.dap;
 514
 515         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, address, value);
 516
 517         return retval;
 518 }
 519
 520 /*
 521  * Cortex-A implementation of Debug Programmer's Model
 522  *
 523  * NOTE the invariant:  these routines return with DSCR_INSTR_COMP set,
 524  * so there's no need to poll for it before executing an instruction.
 525  *
 526  * NOTE that in several of these cases the "stall" mode might be useful.
 527  * It'd let us queue a few operations together... prepare/finish might
 528  * be the places to enable/disable that mode.
 529  */
 530
 531 static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
 532 {
 533         return container_of(dpm, struct cortex_a_common, armv7a_common.dpm);
 534 }
 535
 536 static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
 537 {
 538         LOG_DEBUG("write DCC 0x%08" PRIx32, data);
 539         return mem_ap_sel_write_u32(a->armv7a_common.arm.dap,
 540                 a->armv7a_common.debug_ap, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
 541 }
 542
 543 static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
 544         uint32_t *dscr_p)
 545 {
 546         struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
 547         uint32_t dscr = DSCR_INSTR_COMP;
 548         int retval;
 549
 550         if (dscr_p)
 551                 dscr = *dscr_p;
 552
 553         /* Wait for DTRRXfull */
 554         long long then = timeval_ms();
 555         while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 556                 retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
 557                                 a->armv7a_common.debug_base + CPUDBG_DSCR,
 558                                 &dscr);
 559                 if (retval != ERROR_OK)
 560                         return retval;
 561                 if (timeval_ms() > then + 1000) {
 562                         LOG_ERROR("Timeout waiting for read dcc");
 563                         return ERROR_FAIL;
 564                 }
 565         }
 566
 567         retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
 568                         a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571         /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
 572
 573         if (dscr_p)
 574                 *dscr_p = dscr;
 575
 576         return retval;
 577 }
 578
 579 static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
 580 {
 581         struct cortex_a_common *a = dpm_to_a(dpm);
 582         struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
 583         uint32_t dscr;
 584         int retval;
 585
 586         /* set up invariant:  INSTR_COMP is set after ever DPM operation */
 587         long long then = timeval_ms();
 588         for (;; ) {
 589                 retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
 590                                 a->armv7a_common.debug_base + CPUDBG_DSCR,
 591                                 &dscr);
 592                 if (retval != ERROR_OK)
 593                         return retval;
 594                 if ((dscr & DSCR_INSTR_COMP) != 0)
 595                         break;
 596                 if (timeval_ms() > then + 1000) {
 597                         LOG_ERROR("Timeout waiting for dpm prepare");
 598                         return ERROR_FAIL;
 599                 }
 600         }
 601
 602         /* this "should never happen" ... */
 603         if (dscr & DSCR_DTR_RX_FULL) {
 604                 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 605                 /* Clear DCCRX */
 606                 retval = cortex_a_exec_opcode(
 607                                 a->armv7a_common.arm.target,
 608                                 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
 609                                 &dscr);
 610                 if (retval != ERROR_OK)
 611                         return retval;
 612         }
 613
 614         return retval;
 615 }
 616
 617 static int cortex_a_dpm_finish(struct arm_dpm *dpm)
 618 {
 619         /* REVISIT what could be done here? */
 620         return ERROR_OK;
 621 }
 622
 623 static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
 624         uint32_t opcode, uint32_t data)
 625 {
 626         struct cortex_a_common *a = dpm_to_a(dpm);
 627         int retval;
 628         uint32_t dscr = DSCR_INSTR_COMP;
 629
 630         retval = cortex_a_write_dcc(a, data);
 631         if (retval != ERROR_OK)
 632                 return retval;
 633
 634         return cortex_a_exec_opcode(
 635                         a->armv7a_common.arm.target,
 636                         opcode,
 637                         &dscr);
 638 }
 639
 640 static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
 641         uint32_t opcode, uint32_t data)
 642 {
 643         struct cortex_a_common *a = dpm_to_a(dpm);
 644         uint32_t dscr = DSCR_INSTR_COMP;
 645         int retval;
 646
 647         retval = cortex_a_write_dcc(a, data);
 648         if (retval != ERROR_OK)
 649                 return retval;
 650
 651         /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
 652         retval = cortex_a_exec_opcode(
 653                         a->armv7a_common.arm.target,
 654                         ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
 655                         &dscr);
 656         if (retval != ERROR_OK)
 657                 return retval;
 658
 659         /* then the opcode, taking data from R0 */
 660         retval = cortex_a_exec_opcode(
 661                         a->armv7a_common.arm.target,
 662                         opcode,
 663                         &dscr);
 664
 665         return retval;
 666 }
 667
 668 static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
 669 {
 670         struct target *target = dpm->arm->target;
 671         uint32_t dscr = DSCR_INSTR_COMP;
 672
 673         /* "Prefetch flush" after modifying execution status in CPSR */
 674         return cortex_a_exec_opcode(target,
 675                         ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
 676                         &dscr);
 677 }
 678
 679 static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
 680         uint32_t opcode, uint32_t *data)
 681 {
 682         struct cortex_a_common *a = dpm_to_a(dpm);
 683         int retval;
 684         uint32_t dscr = DSCR_INSTR_COMP;
 685
 686         /* the opcode, writing data to DCC */
 687         retval = cortex_a_exec_opcode(
 688                         a->armv7a_common.arm.target,
 689                         opcode,
 690                         &dscr);
 691         if (retval != ERROR_OK)
 692                 return retval;
 693
 694         return cortex_a_read_dcc(a, data, &dscr);
 695 }
 696
 697
 698 static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
 699         uint32_t opcode, uint32_t *data)
 700 {
 701         struct cortex_a_common *a = dpm_to_a(dpm);
 702         uint32_t dscr = DSCR_INSTR_COMP;
 703         int retval;
 704
 705         /* the opcode, writing data to R0 */
 706         retval = cortex_a_exec_opcode(
 707                         a->armv7a_common.arm.target,
 708                         opcode,
 709                         &dscr);
 710         if (retval != ERROR_OK)
 711                 return retval;
 712
 713         /* write R0 to DCC */
 714         retval = cortex_a_exec_opcode(
 715                         a->armv7a_common.arm.target,
 716                         ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
 717                         &dscr);
 718         if (retval != ERROR_OK)
 719                 return retval;
 720
 721         return cortex_a_read_dcc(a, data, &dscr);
 722 }
 723
 724 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 725         uint32_t addr, uint32_t control)
 726 {
 727         struct cortex_a_common *a = dpm_to_a(dpm);
 728         uint32_t vr = a->armv7a_common.debug_base;
 729         uint32_t cr = a->armv7a_common.debug_base;
 730         int retval;
 731
 732         switch (index_t) {
 733                 case 0 ... 15:  /* breakpoints */
 734                         vr += CPUDBG_BVR_BASE;
 735                         cr += CPUDBG_BCR_BASE;
 736                         break;
 737                 case 16 ... 31: /* watchpoints */
 738                         vr += CPUDBG_WVR_BASE;
 739                         cr += CPUDBG_WCR_BASE;
 740                         index_t -= 16;
 741                         break;
 742                 default:
 743                         return ERROR_FAIL;
 744         }
 745         vr += 4 * index_t;
 746         cr += 4 * index_t;
 747
 748         LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
 749                 (unsigned) vr, (unsigned) cr);
 750
 751         retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
 752                         vr, addr);
 753         if (retval != ERROR_OK)
 754                 return retval;
 755         retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
 756                         cr, control);
 757         return retval;
 758 }
 759
 760 static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 761 {
 762         struct cortex_a_common *a = dpm_to_a(dpm);
 763         uint32_t cr;
 764
 765         switch (index_t) {
 766                 case 0 ... 15:
 767                         cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE;
 768                         break;
 769                 case 16 ... 31:
 770                         cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE;
 771                         index_t -= 16;
 772                         break;
 773                 default:
 774                         return ERROR_FAIL;
 775         }
 776         cr += 4 * index_t;
 777
 778         LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
 779
 780         /* clear control register */
 781         return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
 782 }
 783
 784 static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
 785 {
 786         struct arm_dpm *dpm = &a->armv7a_common.dpm;
 787         int retval;
 788
 789         dpm->arm = &a->armv7a_common.arm;
 790         dpm->didr = didr;
 791
 792         dpm->prepare = cortex_a_dpm_prepare;
 793         dpm->finish = cortex_a_dpm_finish;
 794
 795         dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
 796         dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
 797         dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
 798
 799         dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
 800         dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
 801
 802         dpm->bpwp_enable = cortex_a_bpwp_enable;
 803         dpm->bpwp_disable = cortex_a_bpwp_disable;
 804
 805         retval = arm_dpm_setup(dpm);
 806         if (retval == ERROR_OK)
 807                 retval = arm_dpm_initialize(dpm);
 808
 809         return retval;
 810 }
 811 static struct target *get_cortex_a(struct target *target, int32_t coreid)
 812 {
 813         struct target_list *head;
 814         struct target *curr;
 815
 816         head = target->head;
 817         while (head != (struct target_list *)NULL) {
 818                 curr = head->target;
 819                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 820                         return curr;
 821                 head = head->next;
 822         }
 823         return target;
 824 }
 825 static int cortex_a_halt(struct target *target);
 826
 827 static int cortex_a_halt_smp(struct target *target)
 828 {
 829         int retval = 0;
 830         struct target_list *head;
 831         struct target *curr;
 832         head = target->head;
 833         while (head != (struct target_list *)NULL) {
 834                 curr = head->target;
 835                 if ((curr != target) && (curr->state != TARGET_HALTED))
 836                         retval += cortex_a_halt(curr);
 837                 head = head->next;
 838         }
 839         return retval;
 840 }
 841
 842 static int update_halt_gdb(struct target *target)
 843 {
 844         int retval = 0;
 845         if (target->gdb_service && target->gdb_service->core[0] == -1) {
 846                 target->gdb_service->target = target;
 847                 target->gdb_service->core[0] = target->coreid;
 848                 retval += cortex_a_halt_smp(target);
 849         }
 850         return retval;
 851 }
 852
 853 /*
 854  * Cortex-A Run control
 855  */
 856
 857 static int cortex_a_poll(struct target *target)
 858 {
 859         int retval = ERROR_OK;
 860         uint32_t dscr;
 861         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 862         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
 863         struct adiv5_dap *swjdp = armv7a->arm.dap;
 864         enum target_state prev_target_state = target->state;
 865         /*  toggle to another core is done by gdb as follow */
 866         /*  maint packet J core_id */
 867         /*  continue */
 868         /*  the next polling trigger an halt event sent to gdb */
 869         if ((target->state == TARGET_HALTED) && (target->smp) &&
 870                 (target->gdb_service) &&
 871                 (target->gdb_service->target == NULL)) {
 872                 target->gdb_service->target =
 873                         get_cortex_a(target, target->gdb_service->core[1]);
 874                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 875                 return retval;
 876         }
 877         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 878                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
 879         if (retval != ERROR_OK)
 880                 return retval;
 881         cortex_a->cpudbg_dscr = dscr;
 882
 883         if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
 884                 if (prev_target_state != TARGET_HALTED) {
 885                         /* We have a halting debug event */
 886                         LOG_DEBUG("Target halted");
 887                         target->state = TARGET_HALTED;
 888                         if ((prev_target_state == TARGET_RUNNING)
 889                                 || (prev_target_state == TARGET_UNKNOWN)
 890                                 || (prev_target_state == TARGET_RESET)) {
 891                                 retval = cortex_a_debug_entry(target);
 892                                 if (retval != ERROR_OK)
 893                                         return retval;
 894                                 if (target->smp) {
 895                                         retval = update_halt_gdb(target);
 896                                         if (retval != ERROR_OK)
 897                                                 return retval;
 898                                 }
 899                                 target_call_event_callbacks(target,
 900                                         TARGET_EVENT_HALTED);
 901                         }
 902                         if (prev_target_state == TARGET_DEBUG_RUNNING) {
 903                                 LOG_DEBUG(" ");
 904
 905                                 retval = cortex_a_debug_entry(target);
 906                                 if (retval != ERROR_OK)
 907                                         return retval;
 908                                 if (target->smp) {
 909                                         retval = update_halt_gdb(target);
 910                                         if (retval != ERROR_OK)
 911                                                 return retval;
 912                                 }
 913
 914                                 target_call_event_callbacks(target,
 915                                         TARGET_EVENT_DEBUG_HALTED);
 916                         }
 917                 }
 918         } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
 919                 target->state = TARGET_RUNNING;
 920         else {
 921                 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
 922                 target->state = TARGET_UNKNOWN;
 923         }
 924
 925         return retval;
 926 }
 927
 928 static int cortex_a_halt(struct target *target)
 929 {
 930         int retval = ERROR_OK;
 931         uint32_t dscr;
 932         struct armv7a_common *armv7a = target_to_armv7a(target);
 933         struct adiv5_dap *swjdp = armv7a->arm.dap;
 934
 935         /*
 936          * Tell the core to be halted by writing DRCR with 0x1
 937          * and then wait for the core to be halted.
 938          */
 939         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 940                         armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
 941         if (retval != ERROR_OK)
 942                 return retval;
 943
 944         /*
 945          * enter halting debug mode
 946          */
 947         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 948                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951
 952         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
 953                         armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
 954         if (retval != ERROR_OK)
 955                 return retval;
 956
 957         long long then = timeval_ms();
 958         for (;; ) {
 959                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
 960                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
 961                 if (retval != ERROR_OK)
 962                         return retval;
 963                 if ((dscr & DSCR_CORE_HALTED) != 0)
 964                         break;
 965                 if (timeval_ms() > then + 1000) {
 966                         LOG_ERROR("Timeout waiting for halt");
 967                         return ERROR_FAIL;
 968                 }
 969         }
 970
 971         target->debug_reason = DBG_REASON_DBGRQ;
 972
 973         return ERROR_OK;
 974 }
 975
 976 static int cortex_a_internal_restore(struct target *target, int current,
 977         uint32_t *address, int handle_breakpoints, int debug_execution)
 978 {
 979         struct armv7a_common *armv7a = target_to_armv7a(target);
 980         struct arm *arm = &armv7a->arm;
 981         int retval;
 982         uint32_t resume_pc;
 983
 984         if (!debug_execution)
 985                 target_free_all_working_areas(target);
 986
 987 #if 0
 988         if (debug_execution) {
 989                 /* Disable interrupts */
 990                 /* We disable interrupts in the PRIMASK register instead of
 991                  * masking with C_MASKINTS,
 992                  * This is probably the same issue as Cortex-M3 Errata 377493:
 993                  * C_MASKINTS in parallel with disabled interrupts can cause
 994                  * local faults to not be taken. */
 995                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
 996                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
 997                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
 998
 999                 /* Make sure we are in Thumb mode */
1000                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
1001                         buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
1002                         32) | (1 << 24));
1003                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
1004                 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
1005         }
1006 #endif
1007
1008         /* current = 1: continue on current pc, otherwise continue at <address> */
1009         resume_pc = buf_get_u32(arm->pc->value, 0, 32);
1010         if (!current)
1011                 resume_pc = *address;
1012         else
1013                 *address = resume_pc;
1014
1015         /* Make sure that the Armv7 gdb thumb fixups does not
1016          * kill the return address
1017          */
1018         switch (arm->core_state) {
1019                 case ARM_STATE_ARM:
1020                         resume_pc &= 0xFFFFFFFC;
1021                         break;
1022                 case ARM_STATE_THUMB:
1023                 case ARM_STATE_THUMB_EE:
1024                         /* When the return address is loaded into PC
1025                          * bit 0 must be 1 to stay in Thumb state
1026                          */
1027                         resume_pc |= 0x1;
1028                         break;
1029                 case ARM_STATE_JAZELLE:
1030                         LOG_ERROR("How do I resume into Jazelle state??");
1031                         return ERROR_FAIL;
1032         }
1033         LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
1034         buf_set_u32(arm->pc->value, 0, 32, resume_pc);
1035         arm->pc->dirty = 1;
1036         arm->pc->valid = 1;
1037         /* restore dpm_mode at system halt */
1038         dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
1039         /* called it now before restoring context because it uses cpu
1040          * register r0 for restoring cp15 control register */
1041         retval = cortex_a_restore_cp15_control_reg(target);
1042         if (retval != ERROR_OK)
1043                 return retval;
1044         retval = cortex_a_restore_context(target, handle_breakpoints);
1045         if (retval != ERROR_OK)
1046                 return retval;
1047         target->debug_reason = DBG_REASON_NOTHALTED;
1048         target->state = TARGET_RUNNING;
1049
1050         /* registers are now invalid */
1051         register_cache_invalidate(arm->core_cache);
1052
1053 #if 0
1054         /* the front-end may request us not to handle breakpoints */
1055         if (handle_breakpoints) {
1056                 /* Single step past breakpoint at current address */
1057                 breakpoint = breakpoint_find(target, resume_pc);
1058                 if (breakpoint) {
1059                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1060                         cortex_m3_unset_breakpoint(target, breakpoint);
1061                         cortex_m3_single_step_core(target);
1062                         cortex_m3_set_breakpoint(target, breakpoint);
1063                 }
1064         }
1065
1066 #endif
1067         return retval;
1068 }
1069
1070 static int cortex_a_internal_restart(struct target *target)
1071 {
1072         struct armv7a_common *armv7a = target_to_armv7a(target);
1073         struct arm *arm = &armv7a->arm;
1074         struct adiv5_dap *swjdp = arm->dap;
1075         int retval;
1076         uint32_t dscr;
1077         /*
1078          * * Restart core and wait for it to be started.  Clear ITRen and sticky
1079          * * exception flags: see ARMv7 ARM, C5.9.
1080          *
1081          * REVISIT: for single stepping, we probably want to
1082          * disable IRQs by default, with optional override...
1083          */
1084
1085         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1086                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
1087         if (retval != ERROR_OK)
1088                 return retval;
1089
1090         if ((dscr & DSCR_INSTR_COMP) == 0)
1091                 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1092
1093         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
1094                         armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
1095         if (retval != ERROR_OK)
1096                 return retval;
1097
1098         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
1099                         armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
1100                         DRCR_CLEAR_EXCEPTIONS);
1101         if (retval != ERROR_OK)
1102                 return retval;
1103
1104         long long then = timeval_ms();
1105         for (;; ) {
1106                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1107                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
1108                 if (retval != ERROR_OK)
1109                         return retval;
1110                 if ((dscr & DSCR_CORE_RESTARTED) != 0)
1111                         break;
1112                 if (timeval_ms() > then + 1000) {
1113                         LOG_ERROR("Timeout waiting for resume");
1114                         return ERROR_FAIL;
1115                 }
1116         }
1117
1118         target->debug_reason = DBG_REASON_NOTHALTED;
1119         target->state = TARGET_RUNNING;
1120
1121         /* registers are now invalid */
1122         register_cache_invalidate(arm->core_cache);
1123
1124         return ERROR_OK;
1125 }
1126
1127 static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
1128 {
1129         int retval = 0;
1130         struct target_list *head;
1131         struct target *curr;
1132         uint32_t address;
1133         head = target->head;
1134         while (head != (struct target_list *)NULL) {
1135                 curr = head->target;
1136                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
1137                         /*  resume current address , not in step mode */
1138                         retval += cortex_a_internal_restore(curr, 1, &address,
1139                                         handle_breakpoints, 0);
1140                         retval += cortex_a_internal_restart(curr);
1141                 }
1142                 head = head->next;
1143
1144         }
1145         return retval;
1146 }
1147
1148 static int cortex_a_resume(struct target *target, int current,
1149         uint32_t address, int handle_breakpoints, int debug_execution)
1150 {
1151         int retval = 0;
1152         /* dummy resume for smp toggle in order to reduce gdb impact  */
1153         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
1154                 /*   simulate a start and halt of target */
1155                 target->gdb_service->target = NULL;
1156                 target->gdb_service->core[0] = target->gdb_service->core[1];
1157                 /*  fake resume at next poll we play the  target core[1], see poll*/
1158                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1159                 return 0;
1160         }
1161         cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
1162         if (target->smp) {
1163                 target->gdb_service->core[0] = -1;
1164                 retval = cortex_a_restore_smp(target, handle_breakpoints);
1165                 if (retval != ERROR_OK)
1166                         return retval;
1167         }
1168         cortex_a_internal_restart(target);
1169
1170         if (!debug_execution) {
1171                 target->state = TARGET_RUNNING;
1172                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1173                 LOG_DEBUG("target resumed at 0x%" PRIx32, address);
1174         } else {
1175                 target->state = TARGET_DEBUG_RUNNING;
1176                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1177                 LOG_DEBUG("target debug resumed at 0x%" PRIx32, address);
1178         }
1179
1180         return ERROR_OK;
1181 }
1182
1183 static int cortex_a_debug_entry(struct target *target)
1184 {
1185         int i;
1186         uint32_t regfile[16], cpsr, dscr;
1187         int retval = ERROR_OK;
1188         struct working_area *regfile_working_area = NULL;
1189         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1190         struct armv7a_common *armv7a = target_to_armv7a(target);
1191         struct arm *arm = &armv7a->arm;
1192         struct adiv5_dap *swjdp = armv7a->arm.dap;
1193         struct reg *reg;
1194
1195         LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
1196
1197         /* REVISIT surely we should not re-read DSCR !! */
1198         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1199                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
1200         if (retval != ERROR_OK)
1201                 return retval;
1202
1203         /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1204          * imprecise data aborts get discarded by issuing a Data
1205          * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1206          */
1207
1208         /* Enable the ITR execution once we are in debug mode */
1209         dscr |= DSCR_ITR_EN;
1210         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
1211                         armv7a->debug_base + CPUDBG_DSCR, dscr);
1212         if (retval != ERROR_OK)
1213                 return retval;
1214
1215         /* Examine debug reason */
1216         arm_dpm_report_dscr(&armv7a->dpm, cortex_a->cpudbg_dscr);
1217
1218         /* save address of instruction that triggered the watchpoint? */
1219         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1220                 uint32_t wfar;
1221
1222                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1223                                 armv7a->debug_base + CPUDBG_WFAR,
1224                                 &wfar);
1225                 if (retval != ERROR_OK)
1226                         return retval;
1227                 arm_dpm_report_wfar(&armv7a->dpm, wfar);
1228         }
1229
1230         /* REVISIT fast_reg_read is never set ... */
1231
1232         /* Examine target state and mode */
1233         if (cortex_a->fast_reg_read)
1234                 target_alloc_working_area(target, 64, &regfile_working_area);
1235
1236         /* First load register acessible through core debug port*/
1237         if (!regfile_working_area)
1238                 retval = arm_dpm_read_current_registers(&armv7a->dpm);
1239         else {
1240                 retval = cortex_a_read_regs_through_mem(target,
1241                                 regfile_working_area->address, regfile);
1242
1243                 target_free_working_area(target, regfile_working_area);
1244                 if (retval != ERROR_OK)
1245                         return retval;
1246
1247                 /* read Current PSR */
1248                 retval = cortex_a_dap_read_coreregister_u32(target, &cpsr, 16);
1249                 /*  store current cpsr */
1250                 if (retval != ERROR_OK)
1251                         return retval;
1252
1253                 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
1254
1255                 arm_set_cpsr(arm, cpsr);
1256
1257                 /* update cache */
1258                 for (i = 0; i <= ARM_PC; i++) {
1259                         reg = arm_reg_current(arm, i);
1260
1261                         buf_set_u32(reg->value, 0, 32, regfile[i]);
1262                         reg->valid = 1;
1263                         reg->dirty = 0;
1264                 }
1265
1266                 /* Fixup PC Resume Address */
1267                 if (cpsr & (1 << 5)) {
1268                         /* T bit set for Thumb or ThumbEE state */
1269                         regfile[ARM_PC] -= 4;
1270                 } else {
1271                         /* ARM state */
1272                         regfile[ARM_PC] -= 8;
1273                 }
1274
1275                 reg = arm->pc;
1276                 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
1277                 reg->dirty = reg->valid;
1278         }
1279
1280 #if 0
1281 /* TODO, Move this */
1282         uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
1283         cortex_a_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
1284         LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
1285
1286         cortex_a_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
1287         LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
1288
1289         cortex_a_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
1290         LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
1291 #endif
1292
1293         /* Are we in an exception handler */
1294 /*      armv4_5->exception_number = 0; */
1295         if (armv7a->post_debug_entry) {
1296                 retval = armv7a->post_debug_entry(target);
1297                 if (retval != ERROR_OK)
1298                         return retval;
1299         }
1300
1301         return retval;
1302 }
1303
1304 static int cortex_a_post_debug_entry(struct target *target)
1305 {
1306         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1307         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1308         int retval;
1309
1310         /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1311         retval = armv7a->arm.mrc(target, 15,
1312                         0, 0,   /* op1, op2 */
1313                         1, 0,   /* CRn, CRm */
1314                         &cortex_a->cp15_control_reg);
1315         if (retval != ERROR_OK)
1316                 return retval;
1317         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
1318         cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
1319
1320         if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
1321                 armv7a_identify_cache(target);
1322
1323         if (armv7a->is_armv7r) {
1324                 armv7a->armv7a_mmu.mmu_enabled = 0;
1325         } else {
1326                 armv7a->armv7a_mmu.mmu_enabled =
1327                         (cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
1328         }
1329         armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
1330                 (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
1331         armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
1332                 (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
1333         cortex_a->curr_mode = armv7a->arm.core_mode;
1334
1335         return ERROR_OK;
1336 }
1337
1338 int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
1339 {
1340         struct armv7a_common *armv7a = target_to_armv7a(target);
1341         struct adiv5_dap *swjdp = armv7a->arm.dap;
1342         uint32_t dscr;
1343
1344         /* Read DSCR */
1345         int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1346                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
1347         if (ERROR_OK != retval)
1348                 return retval;
1349
1350         /* clear bitfield */
1351         dscr &= ~bit_mask;
1352         /* put new value */
1353         dscr |= value & bit_mask;
1354
1355         /* write new DSCR */
1356         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
1357                         armv7a->debug_base + CPUDBG_DSCR, dscr);
1358         return retval;
1359 }
1360
1361 static int cortex_a_step(struct target *target, int current, uint32_t address,
1362         int handle_breakpoints)
1363 {
1364         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1365         struct armv7a_common *armv7a = target_to_armv7a(target);
1366         struct arm *arm = &armv7a->arm;
1367         struct breakpoint *breakpoint = NULL;
1368         struct breakpoint stepbreakpoint;
1369         struct reg *r;
1370         int retval;
1371
1372         if (target->state != TARGET_HALTED) {
1373                 LOG_WARNING("target not halted");
1374                 return ERROR_TARGET_NOT_HALTED;
1375         }
1376
1377         /* current = 1: continue on current pc, otherwise continue at <address> */
1378         r = arm->pc;
1379         if (!current)
1380                 buf_set_u32(r->value, 0, 32, address);
1381         else
1382                 address = buf_get_u32(r->value, 0, 32);
1383
1384         /* The front-end may request us not to handle breakpoints.
1385          * But since Cortex-A uses breakpoint for single step,
1386          * we MUST handle breakpoints.
1387          */
1388         handle_breakpoints = 1;
1389         if (handle_breakpoints) {
1390                 breakpoint = breakpoint_find(target, address);
1391                 if (breakpoint)
1392                         cortex_a_unset_breakpoint(target, breakpoint);
1393         }
1394
1395         /* Setup single step breakpoint */
1396         stepbreakpoint.address = address;
1397         stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
1398                 ? 2 : 4;
1399         stepbreakpoint.type = BKPT_HARD;
1400         stepbreakpoint.set = 0;
1401
1402         /* Disable interrupts during single step if requested */
1403         if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1404                 retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, DSCR_INT_DIS);
1405                 if (ERROR_OK != retval)
1406                         return retval;
1407         }
1408
1409         /* Break on IVA mismatch */
1410         cortex_a_set_breakpoint(target, &stepbreakpoint, 0x04);
1411
1412         target->debug_reason = DBG_REASON_SINGLESTEP;
1413
1414         retval = cortex_a_resume(target, 1, address, 0, 0);
1415         if (retval != ERROR_OK)
1416                 return retval;
1417
1418         long long then = timeval_ms();
1419         while (target->state != TARGET_HALTED) {
1420                 retval = cortex_a_poll(target);
1421                 if (retval != ERROR_OK)
1422                         return retval;
1423                 if (timeval_ms() > then + 1000) {
1424                         LOG_ERROR("timeout waiting for target halt");
1425                         return ERROR_FAIL;
1426                 }
1427         }
1428
1429         cortex_a_unset_breakpoint(target, &stepbreakpoint);
1430
1431         /* Re-enable interrupts if they were disabled */
1432         if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) {
1433                 retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, 0);
1434                 if (ERROR_OK != retval)
1435                         return retval;
1436         }
1437
1438
1439         target->debug_reason = DBG_REASON_BREAKPOINT;
1440
1441         if (breakpoint)
1442                 cortex_a_set_breakpoint(target, breakpoint, 0);
1443
1444         if (target->state != TARGET_HALTED)
1445                 LOG_DEBUG("target stepped");
1446
1447         return ERROR_OK;
1448 }
1449
1450 static int cortex_a_restore_context(struct target *target, bool bpwp)
1451 {
1452         struct armv7a_common *armv7a = target_to_armv7a(target);
1453
1454         LOG_DEBUG(" ");
1455
1456         if (armv7a->pre_restore_context)
1457                 armv7a->pre_restore_context(target);
1458
1459         return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1460 }
1461
1462 /*
1463  * Cortex-A Breakpoint and watchpoint functions
1464  */
1465
1466 /* Setup hardware Breakpoint Register Pair */
1467 static int cortex_a_set_breakpoint(struct target *target,
1468         struct breakpoint *breakpoint, uint8_t matchmode)
1469 {
1470         int retval;
1471         int brp_i = 0;
1472         uint32_t control;
1473         uint8_t byte_addr_select = 0x0F;
1474         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1475         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1476         struct cortex_a_brp *brp_list = cortex_a->brp_list;
1477
1478         if (breakpoint->set) {
1479                 LOG_WARNING("breakpoint already set");
1480                 return ERROR_OK;
1481         }
1482
1483         if (breakpoint->type == BKPT_HARD) {
1484                 while (brp_list[brp_i].used && (brp_i < cortex_a->brp_num))
1485                         brp_i++;
1486                 if (brp_i >= cortex_a->brp_num) {
1487                         LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1488                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1489                 }
1490                 breakpoint->set = brp_i + 1;
1491                 if (breakpoint->length == 2)
1492                         byte_addr_select = (3 << (breakpoint->address & 0x02));
1493                 control = ((matchmode & 0x7) << 20)
1494                         | (byte_addr_select << 5)
1495                         | (3 << 1) | 1;
1496                 brp_list[brp_i].used = 1;
1497                 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1498                 brp_list[brp_i].control = control;
1499                 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1500                                 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1501                                 brp_list[brp_i].value);
1502                 if (retval != ERROR_OK)
1503                         return retval;
1504                 retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1505                                 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1506                                 brp_list[brp_i].control);
1507                 if (retval != ERROR_OK)
1508                         return retval;
1509                 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1510                         brp_list[brp_i].control,
1511                         brp_list[brp_i].value);
1512         } else if (breakpoint->type == BKPT_SOFT) {
1513                 uint8_t code[4];
1514                 if (breakpoint->length == 2)
1515                         buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1516                 else
1517                         buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1518                 retval = target_read_memory(target,
1519                                 breakpoint->address & 0xFFFFFFFE,
1520                                 breakpoint->length, 1,
1521                                 breakpoint->orig_instr);
1522                 if (retval != ERROR_OK)
1523                         return retval;
1524
1525                 /* make sure data cache is cleaned & invalidated down to PoC */
1526                 if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
1527                         armv7a_cache_flush_virt(target, breakpoint->address,
1528                                                 breakpoint->length);
1529                 }
1530
1531                 retval = target_write_memory(target,
1532                                 breakpoint->address & 0xFFFFFFFE,
1533                                 breakpoint->length, 1, code);
1534                 if (retval != ERROR_OK)
1535                         return retval;
1536
1537                 /* update i-cache at breakpoint location */
1538                 armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
1539                                         breakpoint->length);
1540                 armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
1541                                                  breakpoint->length);
1542
1543                 breakpoint->set = 0x11; /* Any nice value but 0 */
1544         }
1545
1546         return ERROR_OK;
1547 }
1548
1549 static int cortex_a_set_context_breakpoint(struct target *target,
1550         struct breakpoint *breakpoint, uint8_t matchmode)
1551 {
1552         int retval = ERROR_FAIL;
1553         int brp_i = 0;
1554         uint32_t control;
1555         uint8_t byte_addr_select = 0x0F;
1556         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1557         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1558         struct cortex_a_brp *brp_list = cortex_a->brp_list;
1559
1560         if (breakpoint->set) {
1561                 LOG_WARNING("breakpoint already set");
1562                 return retval;
1563         }
1564         /*check available context BRPs*/
1565         while ((brp_list[brp_i].used ||
1566                 (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a->brp_num))
1567                 brp_i++;
1568
1569         if (brp_i >= cortex_a->brp_num) {
1570                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1571                 return ERROR_FAIL;
1572         }
1573
1574         breakpoint->set = brp_i + 1;
1575         control = ((matchmode & 0x7) << 20)
1576                 | (byte_addr_select << 5)
1577                 | (3 << 1) | 1;
1578         brp_list[brp_i].used = 1;
1579         brp_list[brp_i].value = (breakpoint->asid);
1580         brp_list[brp_i].control = control;
1581         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1582                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1583                         brp_list[brp_i].value);
1584         if (retval != ERROR_OK)
1585                 return retval;
1586         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1587                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1588                         brp_list[brp_i].control);
1589         if (retval != ERROR_OK)
1590                 return retval;
1591         LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1592                 brp_list[brp_i].control,
1593                 brp_list[brp_i].value);
1594         return ERROR_OK;
1595
1596 }
1597
1598 static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1599 {
1600         int retval = ERROR_FAIL;
1601         int brp_1 = 0;  /* holds the contextID pair */
1602         int brp_2 = 0;  /* holds the IVA pair */
1603         uint32_t control_CTX, control_IVA;
1604         uint8_t CTX_byte_addr_select = 0x0F;
1605         uint8_t IVA_byte_addr_select = 0x0F;
1606         uint8_t CTX_machmode = 0x03;
1607         uint8_t IVA_machmode = 0x01;
1608         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1609         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1610         struct cortex_a_brp *brp_list = cortex_a->brp_list;
1611
1612         if (breakpoint->set) {
1613                 LOG_WARNING("breakpoint already set");
1614                 return retval;
1615         }
1616         /*check available context BRPs*/
1617         while ((brp_list[brp_1].used ||
1618                 (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
1619                 brp_1++;
1620
1621         printf("brp(CTX) found num: %d\n", brp_1);
1622         if (brp_1 >= cortex_a->brp_num) {
1623                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1624                 return ERROR_FAIL;
1625         }
1626
1627         while ((brp_list[brp_2].used ||
1628                 (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
1629                 brp_2++;
1630
1631         printf("brp(IVA) found num: %d\n", brp_2);
1632         if (brp_2 >= cortex_a->brp_num) {
1633                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1634                 return ERROR_FAIL;
1635         }
1636
1637         breakpoint->set = brp_1 + 1;
1638         breakpoint->linked_BRP = brp_2;
1639         control_CTX = ((CTX_machmode & 0x7) << 20)
1640                 | (brp_2 << 16)
1641                 | (0 << 14)
1642                 | (CTX_byte_addr_select << 5)
1643                 | (3 << 1) | 1;
1644         brp_list[brp_1].used = 1;
1645         brp_list[brp_1].value = (breakpoint->asid);
1646         brp_list[brp_1].control = control_CTX;
1647         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1648                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
1649                         brp_list[brp_1].value);
1650         if (retval != ERROR_OK)
1651                 return retval;
1652         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1653                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
1654                         brp_list[brp_1].control);
1655         if (retval != ERROR_OK)
1656                 return retval;
1657
1658         control_IVA = ((IVA_machmode & 0x7) << 20)
1659                 | (brp_1 << 16)
1660                 | (IVA_byte_addr_select << 5)
1661                 | (3 << 1) | 1;
1662         brp_list[brp_2].used = 1;
1663         brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
1664         brp_list[brp_2].control = control_IVA;
1665         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1666                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
1667                         brp_list[brp_2].value);
1668         if (retval != ERROR_OK)
1669                 return retval;
1670         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1671                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
1672                         brp_list[brp_2].control);
1673         if (retval != ERROR_OK)
1674                 return retval;
1675
1676         return ERROR_OK;
1677 }
1678
1679 static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1680 {
1681         int retval;
1682         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1683         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
1684         struct cortex_a_brp *brp_list = cortex_a->brp_list;
1685
1686         if (!breakpoint->set) {
1687                 LOG_WARNING("breakpoint not set");
1688                 return ERROR_OK;
1689         }
1690
1691         if (breakpoint->type == BKPT_HARD) {
1692                 if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1693                         int brp_i = breakpoint->set - 1;
1694                         int brp_j = breakpoint->linked_BRP;
1695                         if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
1696                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1697                                 return ERROR_OK;
1698                         }
1699                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1700                                 brp_list[brp_i].control, brp_list[brp_i].value);
1701                         brp_list[brp_i].used = 0;
1702                         brp_list[brp_i].value = 0;
1703                         brp_list[brp_i].control = 0;
1704                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1705                                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1706                                         brp_list[brp_i].control);
1707                         if (retval != ERROR_OK)
1708                                 return retval;
1709                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1710                                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1711                                         brp_list[brp_i].value);
1712                         if (retval != ERROR_OK)
1713                                 return retval;
1714                         if ((brp_j < 0) || (brp_j >= cortex_a->brp_num)) {
1715                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1716                                 return ERROR_OK;
1717                         }
1718                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j,
1719                                 brp_list[brp_j].control, brp_list[brp_j].value);
1720                         brp_list[brp_j].used = 0;
1721                         brp_list[brp_j].value = 0;
1722                         brp_list[brp_j].control = 0;
1723                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1724                                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn,
1725                                         brp_list[brp_j].control);
1726                         if (retval != ERROR_OK)
1727                                 return retval;
1728                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1729                                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn,
1730                                         brp_list[brp_j].value);
1731                         if (retval != ERROR_OK)
1732                                 return retval;
1733                         breakpoint->linked_BRP = 0;
1734                         breakpoint->set = 0;
1735                         return ERROR_OK;
1736
1737                 } else {
1738                         int brp_i = breakpoint->set - 1;
1739                         if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
1740                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1741                                 return ERROR_OK;
1742                         }
1743                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1744                                 brp_list[brp_i].control, brp_list[brp_i].value);
1745                         brp_list[brp_i].used = 0;
1746                         brp_list[brp_i].value = 0;
1747                         brp_list[brp_i].control = 0;
1748                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1749                                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1750                                         brp_list[brp_i].control);
1751                         if (retval != ERROR_OK)
1752                                 return retval;
1753                         retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
1754                                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1755                                         brp_list[brp_i].value);
1756                         if (retval != ERROR_OK)
1757                                 return retval;
1758                         breakpoint->set = 0;
1759                         return ERROR_OK;
1760                 }
1761         } else {
1762
1763                 /* make sure data cache is cleaned & invalidated down to PoC */
1764                 if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
1765                         armv7a_cache_flush_virt(target, breakpoint->address,
1766                                                 breakpoint->length);
1767                 }
1768
1769                 /* restore original instruction (kept in target endianness) */
1770                 if (breakpoint->length == 4) {
1771                         retval = target_write_memory(target,
1772                                         breakpoint->address & 0xFFFFFFFE,
1773                                         4, 1, breakpoint->orig_instr);
1774                         if (retval != ERROR_OK)
1775                                 return retval;
1776                 } else {
1777                         retval = target_write_memory(target,
1778                                         breakpoint->address & 0xFFFFFFFE,
1779                                         2, 1, breakpoint->orig_instr);
1780                         if (retval != ERROR_OK)
1781                                 return retval;
1782                 }
1783
1784                 /* update i-cache at breakpoint location */
1785                 armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
1786                                                  breakpoint->length);
1787                 armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
1788                                                  breakpoint->length);
1789         }
1790         breakpoint->set = 0;
1791
1792         return ERROR_OK;
1793 }
1794
1795 static int cortex_a_add_breakpoint(struct target *target,
1796         struct breakpoint *breakpoint)
1797 {
1798         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1799
1800         if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1801                 LOG_INFO("no hardware breakpoint available");
1802                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1803         }
1804
1805         if (breakpoint->type == BKPT_HARD)
1806                 cortex_a->brp_num_available--;
1807
1808         return cortex_a_set_breakpoint(target, breakpoint, 0x00);       /* Exact match */
1809 }
1810
1811 static int cortex_a_add_context_breakpoint(struct target *target,
1812         struct breakpoint *breakpoint)
1813 {
1814         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1815
1816         if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1817                 LOG_INFO("no hardware breakpoint available");
1818                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1819         }
1820
1821         if (breakpoint->type == BKPT_HARD)
1822                 cortex_a->brp_num_available--;
1823
1824         return cortex_a_set_context_breakpoint(target, breakpoint, 0x02);       /* asid match */
1825 }
1826
1827 static int cortex_a_add_hybrid_breakpoint(struct target *target,
1828         struct breakpoint *breakpoint)
1829 {
1830         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1831
1832         if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
1833                 LOG_INFO("no hardware breakpoint available");
1834                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1835         }
1836
1837         if (breakpoint->type == BKPT_HARD)
1838                 cortex_a->brp_num_available--;
1839
1840         return cortex_a_set_hybrid_breakpoint(target, breakpoint);      /* ??? */
1841 }
1842
1843
1844 static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1845 {
1846         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
1847
1848 #if 0
1849 /* It is perfectly possible to remove breakpoints while the target is running */
1850         if (target->state != TARGET_HALTED) {
1851                 LOG_WARNING("target not halted");
1852                 return ERROR_TARGET_NOT_HALTED;
1853         }
1854 #endif
1855
1856         if (breakpoint->set) {
1857                 cortex_a_unset_breakpoint(target, breakpoint);
1858                 if (breakpoint->type == BKPT_HARD)
1859                         cortex_a->brp_num_available++;
1860         }
1861
1862
1863         return ERROR_OK;
1864 }
1865
1866 /*
1867  * Cortex-A Reset functions
1868  */
1869
1870 static int cortex_a_assert_reset(struct target *target)
1871 {
1872         struct armv7a_common *armv7a = target_to_armv7a(target);
1873
1874         LOG_DEBUG(" ");
1875
1876         /* FIXME when halt is requested, make it work somehow... */
1877
1878         /* Issue some kind of warm reset. */
1879         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
1880                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1881         else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1882                 /* REVISIT handle "pulls" cases, if there's
1883                  * hardware that needs them to work.
1884                  */
1885                 jtag_add_reset(0, 1);
1886         } else {
1887                 LOG_ERROR("%s: how to reset?", target_name(target));
1888                 return ERROR_FAIL;
1889         }
1890
1891         /* registers are now invalid */
1892         register_cache_invalidate(armv7a->arm.core_cache);
1893
1894         target->state = TARGET_RESET;
1895
1896         return ERROR_OK;
1897 }
1898
1899 static int cortex_a_deassert_reset(struct target *target)
1900 {
1901         int retval;
1902
1903         LOG_DEBUG(" ");
1904
1905         /* be certain SRST is off */
1906         jtag_add_reset(0, 0);
1907
1908         retval = cortex_a_poll(target);
1909         if (retval != ERROR_OK)
1910                 return retval;
1911
1912         if (target->reset_halt) {
1913                 if (target->state != TARGET_HALTED) {
1914                         LOG_WARNING("%s: ran after reset and before halt ...",
1915                                 target_name(target));
1916                         retval = target_halt(target);
1917                         if (retval != ERROR_OK)
1918                                 return retval;
1919                 }
1920         }
1921
1922         return ERROR_OK;
1923 }
1924
1925 static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr)
1926 {
1927         /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1928          * New desired mode must be in mode. Current value of DSCR must be in
1929          * *dscr, which is updated with new value.
1930          *
1931          * This function elides actually sending the mode-change over the debug
1932          * interface if the mode is already set as desired.
1933          */
1934         uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
1935         if (new_dscr != *dscr) {
1936                 struct armv7a_common *armv7a = target_to_armv7a(target);
1937                 int retval = mem_ap_sel_write_atomic_u32(armv7a->arm.dap,
1938                                 armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, new_dscr);
1939                 if (retval == ERROR_OK)
1940                         *dscr = new_dscr;
1941                 return retval;
1942         } else {
1943                 return ERROR_OK;
1944         }
1945 }
1946
1947 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
1948         uint32_t value, uint32_t *dscr)
1949 {
1950         /* Waits until the specified bit(s) of DSCR take on a specified value. */
1951         struct armv7a_common *armv7a = target_to_armv7a(target);
1952         struct adiv5_dap *swjdp = armv7a->arm.dap;
1953         long long then = timeval_ms();
1954         int retval;
1955
1956         while ((*dscr & mask) != value) {
1957                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1958                                 armv7a->debug_base + CPUDBG_DSCR, dscr);
1959                 if (retval != ERROR_OK)
1960                         return retval;
1961                 if (timeval_ms() > then + 1000) {
1962                         LOG_ERROR("timeout waiting for DSCR bit change");
1963                         return ERROR_FAIL;
1964                 }
1965         }
1966         return ERROR_OK;
1967 }
1968
1969 static int cortex_a_read_copro(struct target *target, uint32_t opcode,
1970         uint32_t *data, uint32_t *dscr)
1971 {
1972         int retval;
1973         struct armv7a_common *armv7a = target_to_armv7a(target);
1974         struct adiv5_dap *swjdp = armv7a->arm.dap;
1975
1976         /* Move from coprocessor to R0. */
1977         retval = cortex_a_exec_opcode(target, opcode, dscr);
1978         if (retval != ERROR_OK)
1979                 return retval;
1980
1981         /* Move from R0 to DTRTX. */
1982         retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr);
1983         if (retval != ERROR_OK)
1984                 return retval;
1985
1986         /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1987          * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1988          * must also check TXfull_l). Most of the time this will be free
1989          * because TXfull_l will be set immediately and cached in dscr. */
1990         retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
1991                         DSCR_DTRTX_FULL_LATCHED, dscr);
1992         if (retval != ERROR_OK)
1993                 return retval;
1994
1995         /* Read the value transferred to DTRTX. */
1996         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
1997                         armv7a->debug_base + CPUDBG_DTRTX, data);
1998         if (retval != ERROR_OK)
1999                 return retval;
2000
2001         return ERROR_OK;
2002 }
2003
2004 static int cortex_a_read_dfar_dfsr(struct target *target, uint32_t *dfar,
2005         uint32_t *dfsr, uint32_t *dscr)
2006 {
2007         int retval;
2008
2009         if (dfar) {
2010                 retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar, dscr);
2011                 if (retval != ERROR_OK)
2012                         return retval;
2013         }
2014
2015         if (dfsr) {
2016                 retval = cortex_a_read_copro(target, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr, dscr);
2017                 if (retval != ERROR_OK)
2018                         return retval;
2019         }
2020
2021         return ERROR_OK;
2022 }
2023
2024 static int cortex_a_write_copro(struct target *target, uint32_t opcode,
2025         uint32_t data, uint32_t *dscr)
2026 {
2027         int retval;
2028         struct armv7a_common *armv7a = target_to_armv7a(target);
2029         struct adiv5_dap *swjdp = armv7a->arm.dap;
2030
2031         /* Write the value into DTRRX. */
2032         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2033                         armv7a->debug_base + CPUDBG_DTRRX, data);
2034         if (retval != ERROR_OK)
2035                 return retval;
2036
2037         /* Move from DTRRX to R0. */
2038         retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr);
2039         if (retval != ERROR_OK)
2040                 return retval;
2041
2042         /* Move from R0 to coprocessor. */
2043         retval = cortex_a_exec_opcode(target, opcode, dscr);
2044         if (retval != ERROR_OK)
2045                 return retval;
2046
2047         /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2048          * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2049          * check RXfull_l). Most of the time this will be free because RXfull_l
2050          * will be cleared immediately and cached in dscr. */
2051         retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, dscr);
2052         if (retval != ERROR_OK)
2053                 return retval;
2054
2055         return ERROR_OK;
2056 }
2057
2058 static int cortex_a_write_dfar_dfsr(struct target *target, uint32_t dfar,
2059         uint32_t dfsr, uint32_t *dscr)
2060 {
2061         int retval;
2062
2063         retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar, dscr);
2064         if (retval != ERROR_OK)
2065                 return retval;
2066
2067         retval = cortex_a_write_copro(target, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr, dscr);
2068         if (retval != ERROR_OK)
2069                 return retval;
2070
2071         return ERROR_OK;
2072 }
2073
2074 static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
2075 {
2076         uint32_t status, upper4;
2077
2078         if (dfsr & (1 << 9)) {
2079                 /* LPAE format. */
2080                 status = dfsr & 0x3f;
2081                 upper4 = status >> 2;
2082                 if (upper4 == 1 || upper4 == 2 || upper4 == 3 || upper4 == 15)
2083                         return ERROR_TARGET_TRANSLATION_FAULT;
2084                 else if (status == 33)
2085                         return ERROR_TARGET_UNALIGNED_ACCESS;
2086                 else
2087                         return ERROR_TARGET_DATA_ABORT;
2088         } else {
2089                 /* Normal format. */
2090                 status = ((dfsr >> 6) & 0x10) | (dfsr & 0xf);
2091                 if (status == 1)
2092                         return ERROR_TARGET_UNALIGNED_ACCESS;
2093                 else if (status == 5 || status == 7 || status == 3 || status == 6 ||
2094                                 status == 9 || status == 11 || status == 13 || status == 15)
2095                         return ERROR_TARGET_TRANSLATION_FAULT;
2096                 else
2097                         return ERROR_TARGET_DATA_ABORT;
2098         }
2099 }
2100
2101 static int cortex_a_write_apb_ab_memory_slow(struct target *target,
2102         uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2103 {
2104         /* Writes count objects of size size from *buffer. Old value of DSCR must
2105          * be in *dscr; updated to new value. This is slow because it works for
2106          * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2107          * the address is aligned, cortex_a_write_apb_ab_memory_fast should be
2108          * preferred.
2109          * Preconditions:
2110          * - Address is in R0.
2111          * - R0 is marked dirty.
2112          */
2113         struct armv7a_common *armv7a = target_to_armv7a(target);
2114         struct adiv5_dap *swjdp = armv7a->arm.dap;
2115         struct arm *arm = &armv7a->arm;
2116         int retval;
2117
2118         /* Mark register R1 as dirty, to use for transferring data. */
2119         arm_reg_current(arm, 1)->dirty = true;
2120
2121         /* Switch to non-blocking mode if not already in that mode. */
2122         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2123         if (retval != ERROR_OK)
2124                 return retval;
2125
2126         /* Go through the objects. */
2127         while (count) {
2128                 /* Write the value to store into DTRRX. */
2129                 uint32_t data, opcode;
2130                 if (size == 1)
2131                         data = *buffer;
2132                 else if (size == 2)
2133                         data = target_buffer_get_u16(target, buffer);
2134                 else
2135                         data = target_buffer_get_u32(target, buffer);
2136                 retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2137                                 armv7a->debug_base + CPUDBG_DTRRX, data);
2138                 if (retval != ERROR_OK)
2139                         return retval;
2140
2141                 /* Transfer the value from DTRRX to R1. */
2142                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr);
2143                 if (retval != ERROR_OK)
2144                         return retval;
2145
2146                 /* Write the value transferred to R1 into memory. */
2147                 if (size == 1)
2148                         opcode = ARMV4_5_STRB_IP(1, 0);
2149                 else if (size == 2)
2150                         opcode = ARMV4_5_STRH_IP(1, 0);
2151                 else
2152                         opcode = ARMV4_5_STRW_IP(1, 0);
2153                 retval = cortex_a_exec_opcode(target, opcode, dscr);
2154                 if (retval != ERROR_OK)
2155                         return retval;
2156
2157                 /* Check for faults and return early. */
2158                 if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2159                         return ERROR_OK; /* A data fault is not considered a system failure. */
2160
2161                 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2162                  * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2163                  * must also check RXfull_l). Most of the time this will be free
2164                  * because RXfull_l will be cleared immediately and cached in dscr. */
2165                 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, dscr);
2166                 if (retval != ERROR_OK)
2167                         return retval;
2168
2169                 /* Advance. */
2170                 buffer += size;
2171                 --count;
2172         }
2173
2174         return ERROR_OK;
2175 }
2176
2177 static int cortex_a_write_apb_ab_memory_fast(struct target *target,
2178         uint32_t count, const uint8_t *buffer, uint32_t *dscr)
2179 {
2180         /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2181          * in *dscr; updated to new value. This is fast but only works for
2182          * word-sized objects at aligned addresses.
2183          * Preconditions:
2184          * - Address is in R0 and must be a multiple of 4.
2185          * - R0 is marked dirty.
2186          */
2187         struct armv7a_common *armv7a = target_to_armv7a(target);
2188         struct adiv5_dap *swjdp = armv7a->arm.dap;
2189         int retval;
2190
2191         /* Switch to fast mode if not already in that mode. */
2192         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_FAST_MODE, dscr);
2193         if (retval != ERROR_OK)
2194                 return retval;
2195
2196         /* Latch STC instruction. */
2197         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2198                         armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2199         if (retval != ERROR_OK)
2200                 return retval;
2201
2202         /* Transfer all the data and issue all the instructions. */
2203         return mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap, buffer,
2204                         4, count, armv7a->debug_base + CPUDBG_DTRRX);
2205 }
2206
2207 static int cortex_a_write_apb_ab_memory(struct target *target,
2208         uint32_t address, uint32_t size,
2209         uint32_t count, const uint8_t *buffer)
2210 {
2211         /* Write memory through APB-AP. */
2212         int retval, final_retval;
2213         struct armv7a_common *armv7a = target_to_armv7a(target);
2214         struct adiv5_dap *swjdp = armv7a->arm.dap;
2215         struct arm *arm = &armv7a->arm;
2216         uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2217
2218         LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
2219                           address, size, count);
2220         if (target->state != TARGET_HALTED) {
2221                 LOG_WARNING("target not halted");
2222                 return ERROR_TARGET_NOT_HALTED;
2223         }
2224
2225         if (!count)
2226                 return ERROR_OK;
2227
2228         /* Clear any abort. */
2229         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2230                         armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2231         if (retval != ERROR_OK)
2232                 return retval;
2233
2234         /* Read DSCR. */
2235         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2236                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
2237         if (retval != ERROR_OK)
2238                 return retval;
2239
2240         /* Switch to non-blocking mode if not already in that mode. */
2241         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2242         if (retval != ERROR_OK)
2243                 goto out;
2244
2245         /* Mark R0 as dirty. */
2246         arm_reg_current(arm, 0)->dirty = true;
2247
2248         /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2249         retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2250         if (retval != ERROR_OK)
2251                 goto out;
2252
2253         /* Get the memory address into R0. */
2254         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2255                         armv7a->debug_base + CPUDBG_DTRRX, address);
2256         if (retval != ERROR_OK)
2257                 goto out;
2258         retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2259         if (retval != ERROR_OK)
2260                 goto out;
2261
2262         if (size == 4 && (address % 4) == 0) {
2263                 /* We are doing a word-aligned transfer, so use fast mode. */
2264                 retval = cortex_a_write_apb_ab_memory_fast(target, count, buffer, &dscr);
2265         } else {
2266                 /* Use slow path. */
2267                 retval = cortex_a_write_apb_ab_memory_slow(target, size, count, buffer, &dscr);
2268         }
2269
2270 out:
2271         final_retval = retval;
2272
2273         /* Switch to non-blocking mode if not already in that mode. */
2274         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2275         if (final_retval == ERROR_OK)
2276                 final_retval = retval;
2277
2278         /* Wait for last issued instruction to complete. */
2279         retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2280         if (final_retval == ERROR_OK)
2281                 final_retval = retval;
2282
2283         /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2284          * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2285          * check RXfull_l). Most of the time this will be free because RXfull_l
2286          * will be cleared immediately and cached in dscr. However, don’t do this
2287          * if there is fault, because then the instruction might not have completed
2288          * successfully. */
2289         if (!(dscr & DSCR_STICKY_ABORT_PRECISE)) {
2290                 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRRX_FULL_LATCHED, 0, &dscr);
2291                 if (retval != ERROR_OK)
2292                         return retval;
2293         }
2294
2295         /* If there were any sticky abort flags, clear them. */
2296         if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
2297                 fault_dscr = dscr;
2298                 mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2299                                 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2300                 dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
2301         } else {
2302                 fault_dscr = 0;
2303         }
2304
2305         /* Handle synchronous data faults. */
2306         if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2307                 if (final_retval == ERROR_OK) {
2308                         /* Final return value will reflect cause of fault. */
2309                         retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2310                         if (retval == ERROR_OK) {
2311                                 LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2312                                 final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2313                         } else
2314                                 final_retval = retval;
2315                 }
2316                 /* Fault destroyed DFAR/DFSR; restore them. */
2317                 retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2318                 if (retval != ERROR_OK)
2319                         LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2320         }
2321
2322         /* Handle asynchronous data faults. */
2323         if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2324                 if (final_retval == ERROR_OK)
2325                         /* No other error has been recorded so far, so keep this one. */
2326                         final_retval = ERROR_TARGET_DATA_ABORT;
2327         }
2328
2329         /* If the DCC is nonempty, clear it. */
2330         if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2331                 uint32_t dummy;
2332                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2333                                 armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2334                 if (final_retval == ERROR_OK)
2335                         final_retval = retval;
2336         }
2337         if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2338                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2339                 if (final_retval == ERROR_OK)
2340                         final_retval = retval;
2341         }
2342
2343         /* Done. */
2344         return final_retval;
2345 }
2346
2347 static int cortex_a_read_apb_ab_memory_slow(struct target *target,
2348         uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
2349 {
2350         /* Reads count objects of size size into *buffer. Old value of DSCR must be
2351          * in *dscr; updated to new value. This is slow because it works for
2352          * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2353          * the address is aligned, cortex_a_read_apb_ab_memory_fast should be
2354          * preferred.
2355          * Preconditions:
2356          * - Address is in R0.
2357          * - R0 is marked dirty.
2358          */
2359         struct armv7a_common *armv7a = target_to_armv7a(target);
2360         struct adiv5_dap *swjdp = armv7a->arm.dap;
2361         struct arm *arm = &armv7a->arm;
2362         int retval;
2363
2364         /* Mark register R1 as dirty, to use for transferring data. */
2365         arm_reg_current(arm, 1)->dirty = true;
2366
2367         /* Switch to non-blocking mode if not already in that mode. */
2368         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2369         if (retval != ERROR_OK)
2370                 return retval;
2371
2372         /* Go through the objects. */
2373         while (count) {
2374                 /* Issue a load of the appropriate size to R1. */
2375                 uint32_t opcode, data;
2376                 if (size == 1)
2377                         opcode = ARMV4_5_LDRB_IP(1, 0);
2378                 else if (size == 2)
2379                         opcode = ARMV4_5_LDRH_IP(1, 0);
2380                 else
2381                         opcode = ARMV4_5_LDRW_IP(1, 0);
2382                 retval = cortex_a_exec_opcode(target, opcode, dscr);
2383                 if (retval != ERROR_OK)
2384                         return retval;
2385
2386                 /* Issue a write of R1 to DTRTX. */
2387                 retval = cortex_a_exec_opcode(target, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr);
2388                 if (retval != ERROR_OK)
2389                         return retval;
2390
2391                 /* Check for faults and return early. */
2392                 if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2393                         return ERROR_OK; /* A data fault is not considered a system failure. */
2394
2395                 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2396                  * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2397                  * must also check TXfull_l). Most of the time this will be free
2398                  * because TXfull_l will be set immediately and cached in dscr. */
2399                 retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
2400                                 DSCR_DTRTX_FULL_LATCHED, dscr);
2401                 if (retval != ERROR_OK)
2402                         return retval;
2403
2404                 /* Read the value transferred to DTRTX into the buffer. */
2405                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2406                                 armv7a->debug_base + CPUDBG_DTRTX, &data);
2407                 if (retval != ERROR_OK)
2408                         return retval;
2409                 if (size == 1)
2410                         *buffer = (uint8_t) data;
2411                 else if (size == 2)
2412                         target_buffer_set_u16(target, buffer, (uint16_t) data);
2413                 else
2414                         target_buffer_set_u32(target, buffer, data);
2415
2416                 /* Advance. */
2417                 buffer += size;
2418                 --count;
2419         }
2420
2421         return ERROR_OK;
2422 }
2423
2424 static int cortex_a_read_apb_ab_memory_fast(struct target *target,
2425         uint32_t count, uint8_t *buffer, uint32_t *dscr)
2426 {
2427         /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2428          * *dscr; updated to new value. This is fast but only works for word-sized
2429          * objects at aligned addresses.
2430          * Preconditions:
2431          * - Address is in R0 and must be a multiple of 4.
2432          * - R0 is marked dirty.
2433          */
2434         struct armv7a_common *armv7a = target_to_armv7a(target);
2435         struct adiv5_dap *swjdp = armv7a->arm.dap;
2436         uint32_t new_dscr, u32;
2437         int retval;
2438
2439         /* Switch to non-blocking mode if not already in that mode. */
2440         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2441         if (retval != ERROR_OK)
2442                 return retval;
2443
2444         if (count > 1) {
2445                 /* Consecutively issue the LDC instruction via a write to ITR and
2446                  * change to fast mode, in a single bulk copy since DSCR == ITR + 4.
2447                  * The instruction is issued into the core before the mode switch. */
2448                 uint8_t command[8];
2449                 target_buffer_set_u32(target, command, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2450                 new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE;
2451                 target_buffer_set_u32(target, command + 4, new_dscr);
2452                 retval = mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, command, 4, 2,
2453                                 armv7a->debug_base + CPUDBG_ITR);
2454                 if (retval != ERROR_OK)
2455                         return retval;
2456                 *dscr = new_dscr;
2457
2458                 /* Read the value transferred to DTRTX into the buffer. Due to fast
2459                  * mode rules, this blocks until the instruction finishes executing and
2460                  * then reissues the read instruction to read the next word from
2461                  * memory. The last read of DTRTX in this call reads the second-to-last
2462                  * word from memory and issues the read instruction for the last word.
2463                  */
2464                 retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap, buffer,
2465                                 4, count - 1, armv7a->debug_base + CPUDBG_DTRTX);
2466                 if (retval != ERROR_OK)
2467                         return retval;
2468
2469                 /* Advance. */
2470                 buffer += (count - 1) * 4;
2471         } else {
2472                 /* Issue the LDC instruction via a write to ITR. */
2473                 retval = cortex_a_exec_opcode(target, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr);
2474                 if (retval != ERROR_OK)
2475                         return retval;
2476         }
2477
2478         /* Switch to non-blocking mode if not already in that mode. */
2479         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, dscr);
2480         if (retval != ERROR_OK)
2481                 return retval;
2482
2483         /* Wait for last issued instruction to complete. */
2484         retval = cortex_a_wait_instrcmpl(target, dscr, false);
2485         if (retval != ERROR_OK)
2486                 return retval;
2487
2488         /* Check for faults and return early. */
2489         if (*dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE))
2490                 return ERROR_OK; /* A data fault is not considered a system failure. */
2491
2492         /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2493          * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2494          * check TXfull_l). Most of the time this will be free because TXfull_l
2495          * will be set immediately and cached in dscr. */
2496         retval = cortex_a_wait_dscr_bits(target, DSCR_DTRTX_FULL_LATCHED,
2497                         DSCR_DTRTX_FULL_LATCHED, dscr);
2498         if (retval != ERROR_OK)
2499                 return retval;
2500
2501         /* Read the value transferred to DTRTX into the buffer. This is the last
2502          * word. */
2503         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2504                         armv7a->debug_base + CPUDBG_DTRTX, &u32);
2505         if (retval != ERROR_OK)
2506                 return retval;
2507         target_buffer_set_u32(target, buffer, u32);
2508
2509         return ERROR_OK;
2510 }
2511
2512 static int cortex_a_read_apb_ab_memory(struct target *target,
2513         uint32_t address, uint32_t size,
2514         uint32_t count, uint8_t *buffer)
2515 {
2516         /* Read memory through APB-AP. */
2517         int retval, final_retval;
2518         struct armv7a_common *armv7a = target_to_armv7a(target);
2519         struct adiv5_dap *swjdp = armv7a->arm.dap;
2520         struct arm *arm = &armv7a->arm;
2521         uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
2522
2523         LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
2524                           address, size, count);
2525         if (target->state != TARGET_HALTED) {
2526                 LOG_WARNING("target not halted");
2527                 return ERROR_TARGET_NOT_HALTED;
2528         }
2529
2530         if (!count)
2531                 return ERROR_OK;
2532
2533         /* Clear any abort. */
2534         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2535                         armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2536         if (retval != ERROR_OK)
2537                 return retval;
2538
2539         /* Read DSCR */
2540         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2541                         armv7a->debug_base + CPUDBG_DSCR, &dscr);
2542         if (retval != ERROR_OK)
2543                 return retval;
2544
2545         /* Switch to non-blocking mode if not already in that mode. */
2546         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2547         if (retval != ERROR_OK)
2548                 goto out;
2549
2550         /* Mark R0 as dirty. */
2551         arm_reg_current(arm, 0)->dirty = true;
2552
2553         /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2554         retval = cortex_a_read_dfar_dfsr(target, &orig_dfar, &orig_dfsr, &dscr);
2555         if (retval != ERROR_OK)
2556                 goto out;
2557
2558         /* Get the memory address into R0. */
2559         retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2560                         armv7a->debug_base + CPUDBG_DTRRX, address);
2561         if (retval != ERROR_OK)
2562                 goto out;
2563         retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
2564         if (retval != ERROR_OK)
2565                 goto out;
2566
2567         if (size == 4 && (address % 4) == 0) {
2568                 /* We are doing a word-aligned transfer, so use fast mode. */
2569                 retval = cortex_a_read_apb_ab_memory_fast(target, count, buffer, &dscr);
2570         } else {
2571                 /* Use slow path. */
2572                 retval = cortex_a_read_apb_ab_memory_slow(target, size, count, buffer, &dscr);
2573         }
2574
2575 out:
2576         final_retval = retval;
2577
2578         /* Switch to non-blocking mode if not already in that mode. */
2579         retval = cortex_a_set_dcc_mode(target, DSCR_EXT_DCC_NON_BLOCKING, &dscr);
2580         if (final_retval == ERROR_OK)
2581                 final_retval = retval;
2582
2583         /* Wait for last issued instruction to complete. */
2584         retval = cortex_a_wait_instrcmpl(target, &dscr, true);
2585         if (final_retval == ERROR_OK)
2586                 final_retval = retval;
2587
2588         /* If there were any sticky abort flags, clear them. */
2589         if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
2590                 fault_dscr = dscr;
2591                 mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
2592                                 armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
2593                 dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
2594         } else {
2595                 fault_dscr = 0;
2596         }
2597
2598         /* Handle synchronous data faults. */
2599         if (fault_dscr & DSCR_STICKY_ABORT_PRECISE) {
2600                 if (final_retval == ERROR_OK) {
2601                         /* Final return value will reflect cause of fault. */
2602                         retval = cortex_a_read_dfar_dfsr(target, &fault_dfar, &fault_dfsr, &dscr);
2603                         if (retval == ERROR_OK) {
2604                                 LOG_ERROR("data abort at 0x%08" PRIx32 ", dfsr = 0x%08" PRIx32, fault_dfar, fault_dfsr);
2605                                 final_retval = cortex_a_dfsr_to_error_code(fault_dfsr);
2606                         } else
2607                                 final_retval = retval;
2608                 }
2609                 /* Fault destroyed DFAR/DFSR; restore them. */
2610                 retval = cortex_a_write_dfar_dfsr(target, orig_dfar, orig_dfsr, &dscr);
2611                 if (retval != ERROR_OK)
2612                         LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32, dscr);
2613         }
2614
2615         /* Handle asynchronous data faults. */
2616         if (fault_dscr & DSCR_STICKY_ABORT_IMPRECISE) {
2617                 if (final_retval == ERROR_OK)
2618                         /* No other error has been recorded so far, so keep this one. */
2619                         final_retval = ERROR_TARGET_DATA_ABORT;
2620         }
2621
2622         /* If the DCC is nonempty, clear it. */
2623         if (dscr & DSCR_DTRTX_FULL_LATCHED) {
2624                 uint32_t dummy;
2625                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2626                                 armv7a->debug_base + CPUDBG_DTRTX, &dummy);
2627                 if (final_retval == ERROR_OK)
2628                         final_retval = retval;
2629         }
2630         if (dscr & DSCR_DTRRX_FULL_LATCHED) {
2631                 retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
2632                 if (final_retval == ERROR_OK)
2633                         final_retval = retval;
2634         }
2635
2636         /* Done. */
2637         return final_retval;
2638 }
2639
2640
2641 /*
2642  * Cortex-A Memory access
2643  *
2644  * This is same Cortex M3 but we must also use the correct
2645  * ap number for every access.
2646  */
2647
2648 static int cortex_a_read_phys_memory(struct target *target,
2649         uint32_t address, uint32_t size,
2650         uint32_t count, uint8_t *buffer)
2651 {
2652         struct armv7a_common *armv7a = target_to_armv7a(target);
2653         int retval = ERROR_COMMAND_SYNTAX_ERROR;
2654
2655         LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32,
2656                 address, size, count);
2657
2658         if (count && buffer) {
2659                 /* read memory through APB-AP */
2660                 if (!armv7a->is_armv7r) {
2661                         /*  disable mmu */
2662                         retval = cortex_a_mmu_modify(target, 0);
2663                         if (retval != ERROR_OK)
2664                                 return retval;
2665                 }
2666                 retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
2667         }
2668         return retval;
2669 }
2670
2671 static int cortex_a_read_memory(struct target *target, uint32_t address,
2672         uint32_t size, uint32_t count, uint8_t *buffer)
2673 {
2674         int mmu_enabled = 0;
2675         int retval;
2676         struct armv7a_common *armv7a = target_to_armv7a(target);
2677
2678         /* cortex_a handles unaligned memory access */
2679         LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
2680                 size, count);
2681
2682         /* determine if MMU was enabled on target stop */
2683         if (!armv7a->is_armv7r) {
2684                 retval = cortex_a_mmu(target, &mmu_enabled);
2685                 if (retval != ERROR_OK)
2686                         return retval;
2687         }
2688
2689         if (mmu_enabled) {
2690                 retval = cortex_a_check_address(target, address);
2691                 if (retval != ERROR_OK)
2692                         return retval;
2693                 /* enable MMU as we could have disabled it for phys access */
2694                 retval = cortex_a_mmu_modify(target, 1);
2695                 if (retval != ERROR_OK)
2696                         return retval;
2697         }
2698         retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
2699
2700         return retval;
2701 }
2702
2703 static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
2704         uint32_t size, uint32_t count, uint8_t *buffer)
2705 {
2706         int mmu_enabled = 0;
2707         uint32_t virt, phys;
2708         int retval;
2709         struct armv7a_common *armv7a = target_to_armv7a(target);
2710         struct adiv5_dap *swjdp = armv7a->arm.dap;
2711         uint8_t apsel = swjdp->apsel;
2712
2713         if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap))
2714                 return target_read_memory(target, address, size, count, buffer);
2715
2716         /* cortex_a handles unaligned memory access */
2717         LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
2718                 size, count);
2719
2720         /* determine if MMU was enabled on target stop */
2721         if (!armv7a->is_armv7r) {
2722                 retval = cortex_a_mmu(target, &mmu_enabled);
2723                 if (retval != ERROR_OK)
2724                         return retval;
2725         }
2726
2727         if (mmu_enabled) {
2728                 virt = address;
2729                 retval = cortex_a_virt2phys(target, virt, &phys);
2730                 if (retval != ERROR_OK)
2731                         return retval;
2732
2733                 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
2734                           virt, phys);
2735                 address = phys;
2736         }
2737
2738         if (!count || !buffer)
2739                 return ERROR_COMMAND_SYNTAX_ERROR;
2740
2741         retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
2742
2743         return retval;
2744 }
2745
2746 static int cortex_a_write_phys_memory(struct target *target,
2747         uint32_t address, uint32_t size,
2748         uint32_t count, const uint8_t *buffer)
2749 {
2750         struct armv7a_common *armv7a = target_to_armv7a(target);
2751         int retval = ERROR_COMMAND_SYNTAX_ERROR;
2752
2753         LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
2754                 size, count);
2755
2756         if (count && buffer) {
2757                 /* write memory through APB-AP */
2758                 if (!armv7a->is_armv7r) {
2759                         retval = cortex_a_mmu_modify(target, 0);
2760                         if (retval != ERROR_OK)
2761                                 return retval;
2762                 }
2763                 return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
2764         }
2765
2766         return retval;
2767 }
2768
2769 static int cortex_a_write_memory(struct target *target, uint32_t address,
2770         uint32_t size, uint32_t count, const uint8_t *buffer)
2771 {
2772         int mmu_enabled = 0;
2773         int retval;
2774         struct armv7a_common *armv7a = target_to_armv7a(target);
2775
2776         /* cortex_a handles unaligned memory access */
2777         LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
2778                 size, count);
2779
2780         /* determine if MMU was enabled on target stop */
2781         if (!armv7a->is_armv7r) {
2782                 retval = cortex_a_mmu(target, &mmu_enabled);
2783                 if (retval != ERROR_OK)
2784                         return retval;
2785         }
2786
2787         if (mmu_enabled) {
2788                 retval = cortex_a_check_address(target, address);
2789                 if (retval != ERROR_OK)
2790                         return retval;
2791                 /* enable MMU as we could have disabled it for phys access */
2792                 retval = cortex_a_mmu_modify(target, 1);
2793                 if (retval != ERROR_OK)
2794                         return retval;
2795         }
2796
2797         /* memory writes bypass the caches, must flush before writing */
2798         armv7a_cache_auto_flush_on_write(target, address, size * count);
2799
2800         retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
2801
2802         return retval;
2803 }
2804
2805 static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
2806         uint32_t size, uint32_t count, const uint8_t *buffer)
2807 {
2808         int mmu_enabled = 0;
2809         uint32_t virt, phys;
2810         int retval;
2811         struct armv7a_common *armv7a = target_to_armv7a(target);
2812         struct adiv5_dap *swjdp = armv7a->arm.dap;
2813         uint8_t apsel = swjdp->apsel;
2814
2815         if (!armv7a->memory_ap_available || (apsel != armv7a->memory_ap))
2816                 return target_write_memory(target, address, size, count, buffer);
2817
2818         /* cortex_a handles unaligned memory access */
2819         LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
2820                 size, count);
2821
2822         /* determine if MMU was enabled on target stop */
2823         if (!armv7a->is_armv7r) {
2824                 retval = cortex_a_mmu(target, &mmu_enabled);
2825                 if (retval != ERROR_OK)
2826                         return retval;
2827         }
2828
2829         if (mmu_enabled) {
2830                 virt = address;
2831                 retval = cortex_a_virt2phys(target, virt, &phys);
2832                 if (retval != ERROR_OK)
2833                         return retval;
2834
2835                 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
2836                           virt,
2837                           phys);
2838                 address = phys;
2839         }
2840
2841         if (!count || !buffer)
2842                 return ERROR_COMMAND_SYNTAX_ERROR;
2843
2844         retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
2845
2846         return retval;
2847 }
2848
2849 static int cortex_a_read_buffer(struct target *target, uint32_t address,
2850                                 uint32_t count, uint8_t *buffer)
2851 {
2852         uint32_t size;
2853
2854         /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2855          * will have something to do with the size we leave to it. */
2856         for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2857                 if (address & size) {
2858                         int retval = cortex_a_read_memory_ahb(target, address, size, 1, buffer);
2859                         if (retval != ERROR_OK)
2860                                 return retval;
2861                         address += size;
2862                         count -= size;
2863                         buffer += size;
2864                 }
2865         }
2866
2867         /* Read the data with as large access size as possible. */
2868         for (; size > 0; size /= 2) {
2869                 uint32_t aligned = count - count % size;
2870                 if (aligned > 0) {
2871                         int retval = cortex_a_read_memory_ahb(target, address, size, aligned / size, buffer);
2872                         if (retval != ERROR_OK)
2873                                 return retval;
2874                         address += aligned;
2875                         count -= aligned;
2876                         buffer += aligned;
2877                 }
2878         }
2879
2880         return ERROR_OK;
2881 }
2882
2883 static int cortex_a_write_buffer(struct target *target, uint32_t address,
2884                                  uint32_t count, const uint8_t *buffer)
2885 {
2886         uint32_t size;
2887
2888         /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2889          * will have something to do with the size we leave to it. */
2890         for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) {
2891                 if (address & size) {
2892                         int retval = cortex_a_write_memory_ahb(target, address, size, 1, buffer);
2893                         if (retval != ERROR_OK)
2894                                 return retval;
2895                         address += size;
2896                         count -= size;
2897                         buffer += size;
2898                 }
2899         }
2900
2901         /* Write the data with as large access size as possible. */
2902         for (; size > 0; size /= 2) {
2903                 uint32_t aligned = count - count % size;
2904                 if (aligned > 0) {
2905                         int retval = cortex_a_write_memory_ahb(target, address, size, aligned / size, buffer);
2906                         if (retval != ERROR_OK)
2907                                 return retval;
2908                         address += aligned;
2909                         count -= aligned;
2910                         buffer += aligned;
2911                 }
2912         }
2913
2914         return ERROR_OK;
2915 }
2916
2917 static int cortex_a_handle_target_request(void *priv)
2918 {
2919         struct target *target = priv;
2920         struct armv7a_common *armv7a = target_to_armv7a(target);
2921         struct adiv5_dap *swjdp = armv7a->arm.dap;
2922         int retval;
2923
2924         if (!target_was_examined(target))
2925                 return ERROR_OK;
2926         if (!target->dbg_msg_enabled)
2927                 return ERROR_OK;
2928
2929         if (target->state == TARGET_RUNNING) {
2930                 uint32_t request;
2931                 uint32_t dscr;
2932                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2933                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2934
2935                 /* check if we have data */
2936                 while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2937                         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2938                                         armv7a->debug_base + CPUDBG_DTRTX, &request);
2939                         if (retval == ERROR_OK) {
2940                                 target_request(target, request);
2941                                 retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
2942                                                 armv7a->debug_base + CPUDBG_DSCR, &dscr);
2943                         }
2944                 }
2945         }
2946
2947         return ERROR_OK;
2948 }
2949
2950 /*
2951  * Cortex-A target information and configuration
2952  */
2953
2954 static int cortex_a_examine_first(struct target *target)
2955 {
2956         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
2957         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
2958         struct adiv5_dap *swjdp = armv7a->arm.dap;
2959         int i;
2960         int retval = ERROR_OK;
2961         uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg;
2962
2963         /* We do one extra read to ensure DAP is configured,
2964          * we call ahbap_debugport_init(swjdp) instead
2965          */
2966         retval = ahbap_debugport_init(swjdp);
2967         if (retval != ERROR_OK)
2968                 return retval;
2969
2970         /* Search for the APB-AB - it is needed for access to debug registers */
2971         retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
2972         if (retval != ERROR_OK) {
2973                 LOG_ERROR("Could not find APB-AP for debug access");
2974                 return retval;
2975         }
2976         /* Search for the AHB-AB */
2977         retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7a->memory_ap);
2978         if (retval != ERROR_OK) {
2979                 /* AHB-AP not found - use APB-AP */
2980                 LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
2981                 armv7a->memory_ap_available = false;
2982         } else {
2983                 armv7a->memory_ap_available = true;
2984         }
2985
2986
2987         if (!target->dbgbase_set) {
2988                 uint32_t dbgbase;
2989                 /* Get ROM Table base */
2990                 uint32_t apid;
2991                 int32_t coreidx = target->coreid;
2992                 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2993                           target->cmd_name);
2994                 retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid);
2995                 if (retval != ERROR_OK)
2996                         return retval;
2997                 /* Lookup 0x15 -- Processor DAP */
2998                 retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15,
2999                                 &armv7a->debug_base, &coreidx);
3000                 if (retval != ERROR_OK) {
3001                         LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
3002                                   target->cmd_name);
3003                         return retval;
3004                 }
3005                 LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
3006                           coreidx, armv7a->debug_base);
3007         } else
3008                 armv7a->debug_base = target->dbgbase;
3009
3010         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3011                         armv7a->debug_base + CPUDBG_CPUID, &cpuid);
3012         if (retval != ERROR_OK)
3013                 return retval;
3014
3015         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3016                         armv7a->debug_base + CPUDBG_CPUID, &cpuid);
3017         if (retval != ERROR_OK) {
3018                 LOG_DEBUG("Examine %s failed", "CPUID");
3019                 return retval;
3020         }
3021
3022         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3023                         armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
3024         if (retval != ERROR_OK) {
3025                 LOG_DEBUG("Examine %s failed", "CTYPR");
3026                 return retval;
3027         }
3028
3029         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3030                         armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
3031         if (retval != ERROR_OK) {
3032                 LOG_DEBUG("Examine %s failed", "TTYPR");
3033                 return retval;
3034         }
3035
3036         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3037                         armv7a->debug_base + CPUDBG_DIDR, &didr);
3038         if (retval != ERROR_OK) {
3039                 LOG_DEBUG("Examine %s failed", "DIDR");
3040                 return retval;
3041         }
3042
3043         LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
3044         LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
3045         LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
3046         LOG_DEBUG("didr = 0x%08" PRIx32, didr);
3047
3048         cortex_a->cpuid = cpuid;
3049         cortex_a->ctypr = ctypr;
3050         cortex_a->ttypr = ttypr;
3051         cortex_a->didr = didr;
3052
3053         /* Unlocking the debug registers */
3054         if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
3055                 CORTEX_A15_PARTNUM) {
3056
3057                 retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
3058                                                      armv7a->debug_base + CPUDBG_OSLAR,
3059                                                      0);
3060
3061                 if (retval != ERROR_OK)
3062                         return retval;
3063
3064         }
3065         /* Unlocking the debug registers */
3066         if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
3067                 CORTEX_A7_PARTNUM) {
3068
3069                 retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
3070                                                      armv7a->debug_base + CPUDBG_OSLAR,
3071                                                      0);
3072
3073                 if (retval != ERROR_OK)
3074                         return retval;
3075
3076         }
3077         retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
3078                                             armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
3079
3080         if (retval != ERROR_OK)
3081                 return retval;
3082
3083         LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR  0x%" PRIx32, target->coreid, dbg_osreg);
3084
3085         armv7a->arm.core_type = ARM_MODE_MON;
3086
3087         /* Avoid recreating the registers cache */
3088         if (!target_was_examined(target)) {
3089                 retval = cortex_a_dpm_setup(cortex_a, didr);
3090                 if (retval != ERROR_OK)
3091                         return retval;
3092         }
3093
3094         /* Setup Breakpoint Register Pairs */
3095         cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;
3096         cortex_a->brp_num_context = ((didr >> 20) & 0x0F) + 1;
3097         cortex_a->brp_num_available = cortex_a->brp_num;
3098         free(cortex_a->brp_list);
3099         cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
3100 /*      cortex_a->brb_enabled = ????; */
3101         for (i = 0; i < cortex_a->brp_num; i++) {
3102                 cortex_a->brp_list[i].used = 0;
3103                 if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
3104                         cortex_a->brp_list[i].type = BRP_NORMAL;
3105                 else
3106                         cortex_a->brp_list[i].type = BRP_CONTEXT;
3107                 cortex_a->brp_list[i].value = 0;
3108                 cortex_a->brp_list[i].control = 0;
3109                 cortex_a->brp_list[i].BRPn = i;
3110         }
3111
3112         LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
3113
3114         target_set_examined(target);
3115         return ERROR_OK;
3116 }
3117
3118 static int cortex_a_examine(struct target *target)
3119 {
3120         int retval = ERROR_OK;
3121
3122         /* Reestablish communication after target reset */
3123         retval = cortex_a_examine_first(target);
3124
3125         /* Configure core debug access */
3126         if (retval == ERROR_OK)
3127                 retval = cortex_a_init_debug_access(target);
3128
3129         return retval;
3130 }
3131
3132 /*
3133  *      Cortex-A target creation and initialization
3134  */
3135
3136 static int cortex_a_init_target(struct command_context *cmd_ctx,
3137         struct target *target)
3138 {
3139         /* examine_first() does a bunch of this */
3140         return ERROR_OK;
3141 }
3142
3143 static int cortex_a_init_arch_info(struct target *target,
3144         struct cortex_a_common *cortex_a, struct jtag_tap *tap)
3145 {
3146         struct armv7a_common *armv7a = &cortex_a->armv7a_common;
3147         struct adiv5_dap *dap = &armv7a->dap;
3148
3149         armv7a->arm.dap = dap;
3150
3151         /* Setup struct cortex_a_common */
3152         cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
3153         /*  tap has no dap initialized */
3154         if (!tap->dap) {
3155                 armv7a->arm.dap = dap;
3156                 /* Setup struct cortex_a_common */
3157
3158                 /* prepare JTAG information for the new target */
3159                 cortex_a->jtag_info.tap = tap;
3160                 cortex_a->jtag_info.scann_size = 4;
3161
3162                 /* Leave (only) generic DAP stuff for debugport_init() */
3163                 dap->jtag_info = &cortex_a->jtag_info;
3164
3165                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
3166                 dap->tar_autoincr_block = (1 << 10);
3167                 dap->memaccess_tck = 80;
3168                 tap->dap = dap;
3169         } else
3170                 armv7a->arm.dap = tap->dap;
3171
3172         cortex_a->fast_reg_read = 0;
3173
3174         /* register arch-specific functions */
3175         armv7a->examine_debug_reason = NULL;
3176
3177         armv7a->post_debug_entry = cortex_a_post_debug_entry;
3178
3179         armv7a->pre_restore_context = NULL;
3180
3181         armv7a->armv7a_mmu.read_physical_memory = cortex_a_read_phys_memory;
3182
3183
3184 /*      arm7_9->handle_target_request = cortex_a_handle_target_request; */
3185
3186         /* REVISIT v7a setup should be in a v7a-specific routine */
3187         armv7a_init_arch_info(target, armv7a);
3188         target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target);
3189
3190         return ERROR_OK;
3191 }
3192
3193 static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
3194 {
3195         struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
3196
3197         cortex_a->armv7a_common.is_armv7r = false;
3198
3199         return cortex_a_init_arch_info(target, cortex_a, target->tap);
3200 }
3201
3202 static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
3203 {
3204         struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
3205
3206         cortex_a->armv7a_common.is_armv7r = true;
3207
3208         return cortex_a_init_arch_info(target, cortex_a, target->tap);
3209 }
3210
3211 static void cortex_a_deinit_target(struct target *target)
3212 {
3213         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3214         struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
3215
3216         free(cortex_a->brp_list);
3217         free(dpm->dbp);
3218         free(dpm->dwp);
3219         free(cortex_a);
3220 }
3221
3222 static int cortex_a_mmu(struct target *target, int *enabled)
3223 {
3224         if (target->state != TARGET_HALTED) {
3225                 LOG_ERROR("%s: target not halted", __func__);
3226                 return ERROR_TARGET_INVALID;
3227         }
3228
3229         *enabled = target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
3230         return ERROR_OK;
3231 }
3232
3233 static int cortex_a_virt2phys(struct target *target,
3234         uint32_t virt, uint32_t *phys)
3235 {
3236         int retval = ERROR_FAIL;
3237         struct armv7a_common *armv7a = target_to_armv7a(target);
3238         struct adiv5_dap *swjdp = armv7a->arm.dap;
3239         uint8_t apsel = swjdp->apsel;
3240         if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
3241                 uint32_t ret;
3242                 retval = armv7a_mmu_translate_va(target,
3243                                 virt, &ret);
3244                 if (retval != ERROR_OK)
3245                         goto done;
3246                 *phys = ret;
3247         } else {/*  use this method if armv7a->memory_ap not selected
3248                  *  mmu must be enable in order to get a correct translation */
3249                 retval = cortex_a_mmu_modify(target, 1);
3250                 if (retval != ERROR_OK)
3251                         goto done;
3252                 retval = armv7a_mmu_translate_va_pa(target, virt,  phys, 1);
3253         }
3254 done:
3255         return retval;
3256 }
3257
3258 COMMAND_HANDLER(cortex_a_handle_cache_info_command)
3259 {
3260         struct target *target = get_current_target(CMD_CTX);
3261         struct armv7a_common *armv7a = target_to_armv7a(target);
3262
3263         return armv7a_handle_cache_info_command(CMD_CTX,
3264                         &armv7a->armv7a_mmu.armv7a_cache);
3265 }
3266
3267
3268 COMMAND_HANDLER(cortex_a_handle_dbginit_command)
3269 {
3270         struct target *target = get_current_target(CMD_CTX);
3271         if (!target_was_examined(target)) {
3272                 LOG_ERROR("target not examined yet");
3273                 return ERROR_FAIL;
3274         }
3275
3276         return cortex_a_init_debug_access(target);
3277 }
3278 COMMAND_HANDLER(cortex_a_handle_smp_off_command)
3279 {
3280         struct target *target = get_current_target(CMD_CTX);
3281         /* check target is an smp target */
3282         struct target_list *head;
3283         struct target *curr;
3284         head = target->head;
3285         target->smp = 0;
3286         if (head != (struct target_list *)NULL) {
3287                 while (head != (struct target_list *)NULL) {
3288                         curr = head->target;
3289                         curr->smp = 0;
3290                         head = head->next;
3291                 }
3292                 /*  fixes the target display to the debugger */
3293                 target->gdb_service->target = target;
3294         }
3295         return ERROR_OK;
3296 }
3297
3298 COMMAND_HANDLER(cortex_a_handle_smp_on_command)
3299 {
3300         struct target *target = get_current_target(CMD_CTX);
3301         struct target_list *head;
3302         struct target *curr;
3303         head = target->head;
3304         if (head != (struct target_list *)NULL) {
3305                 target->smp = 1;
3306                 while (head != (struct target_list *)NULL) {
3307                         curr = head->target;
3308                         curr->smp = 1;
3309                         head = head->next;
3310                 }
3311         }
3312         return ERROR_OK;
3313 }
3314
3315 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command)
3316 {
3317         struct target *target = get_current_target(CMD_CTX);
3318         int retval = ERROR_OK;
3319         struct target_list *head;
3320         head = target->head;
3321         if (head != (struct target_list *)NULL) {
3322                 if (CMD_ARGC == 1) {
3323                         int coreid = 0;
3324                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
3325                         if (ERROR_OK != retval)
3326                                 return retval;
3327                         target->gdb_service->core[1] = coreid;
3328
3329                 }
3330                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
3331                         , target->gdb_service->core[1]);
3332         }
3333         return ERROR_OK;
3334 }
3335
3336 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
3337 {
3338         struct target *target = get_current_target(CMD_CTX);
3339         struct cortex_a_common *cortex_a = target_to_cortex_a(target);
3340
3341         static const Jim_Nvp nvp_maskisr_modes[] = {
3342                 { .name = "off", .value = CORTEX_A_ISRMASK_OFF },
3343                 { .name = "on", .value = CORTEX_A_ISRMASK_ON },
3344                 { .name = NULL, .value = -1 },
3345         };
3346         const Jim_Nvp *n;
3347
3348         if (target->state != TARGET_HALTED) {
3349                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3350                 return ERROR_OK;
3351         }
3352
3353         if (CMD_ARGC > 0) {
3354                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
3355                 if (n->name == NULL)
3356                         return ERROR_COMMAND_SYNTAX_ERROR;
3357                 cortex_a->isrmasking_mode = n->value;
3358
3359         }
3360
3361         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode);
3362         command_print(CMD_CTX, "cortex_a interrupt mask %s", n->name);
3363
3364         return ERROR_OK;
3365 }
3366
3367 static const struct command_registration cortex_a_exec_command_handlers[] = {
3368         {
3369                 .name = "cache_info",
3370                 .handler = cortex_a_handle_cache_info_command,
3371                 .mode = COMMAND_EXEC,
3372                 .help = "display information about target caches",
3373                 .usage = "",
3374         },
3375         {
3376                 .name = "dbginit",
3377                 .handler = cortex_a_handle_dbginit_command,
3378                 .mode = COMMAND_EXEC,
3379                 .help = "Initialize core debug",
3380                 .usage = "",
3381         },
3382         {   .name = "smp_off",
3383             .handler = cortex_a_handle_smp_off_command,
3384             .mode = COMMAND_EXEC,
3385             .help = "Stop smp handling",
3386             .usage = "",},
3387         {
3388                 .name = "smp_on",
3389                 .handler = cortex_a_handle_smp_on_command,
3390                 .mode = COMMAND_EXEC,
3391                 .help = "Restart smp handling",
3392                 .usage = "",
3393         },
3394         {
3395                 .name = "smp_gdb",
3396                 .handler = cortex_a_handle_smp_gdb_command,
3397                 .mode = COMMAND_EXEC,
3398                 .help = "display/fix current core played to gdb",
3399                 .usage = "",
3400         },
3401         {
3402                 .name = "maskisr",
3403                 .handler = handle_cortex_a_mask_interrupts_command,
3404                 .mode = COMMAND_EXEC,
3405                 .help = "mask cortex_a interrupts",
3406                 .usage = "['on'|'off']",
3407         },
3408
3409
3410         COMMAND_REGISTRATION_DONE
3411 };
3412 static const struct command_registration cortex_a_command_handlers[] = {
3413         {
3414                 .chain = arm_command_handlers,
3415         },
3416         {
3417                 .chain = armv7a_command_handlers,
3418         },
3419         {
3420                 .name = "cortex_a",
3421                 .mode = COMMAND_ANY,
3422                 .help = "Cortex-A command group",
3423                 .usage = "",
3424                 .chain = cortex_a_exec_command_handlers,
3425         },
3426         COMMAND_REGISTRATION_DONE
3427 };
3428
3429 struct target_type cortexa_target = {
3430         .name = "cortex_a",
3431         .deprecated_name = "cortex_a8",
3432
3433         .poll = cortex_a_poll,
3434         .arch_state = armv7a_arch_state,
3435
3436         .halt = cortex_a_halt,
3437         .resume = cortex_a_resume,
3438         .step = cortex_a_step,
3439
3440         .assert_reset = cortex_a_assert_reset,
3441         .deassert_reset = cortex_a_deassert_reset,
3442
3443         /* REVISIT allow exporting VFP3 registers ... */
3444         .get_gdb_reg_list = arm_get_gdb_reg_list,
3445
3446         .read_memory = cortex_a_read_memory,
3447         .write_memory = cortex_a_write_memory,
3448
3449         .read_buffer = cortex_a_read_buffer,
3450         .write_buffer = cortex_a_write_buffer,
3451
3452         .checksum_memory = arm_checksum_memory,
3453         .blank_check_memory = arm_blank_check_memory,
3454
3455         .run_algorithm = armv4_5_run_algorithm,
3456
3457         .add_breakpoint = cortex_a_add_breakpoint,
3458         .add_context_breakpoint = cortex_a_add_context_breakpoint,
3459         .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3460         .remove_breakpoint = cortex_a_remove_breakpoint,
3461         .add_watchpoint = NULL,
3462         .remove_watchpoint = NULL,
3463
3464         .commands = cortex_a_command_handlers,
3465         .target_create = cortex_a_target_create,
3466         .init_target = cortex_a_init_target,
3467         .examine = cortex_a_examine,
3468         .deinit_target = cortex_a_deinit_target,
3469
3470         .read_phys_memory = cortex_a_read_phys_memory,
3471         .write_phys_memory = cortex_a_write_phys_memory,
3472         .mmu = cortex_a_mmu,
3473         .virt2phys = cortex_a_virt2phys,
3474 };
3475
3476 static const struct command_registration cortex_r4_exec_command_handlers[] = {
3477         {
3478                 .name = "cache_info",
3479                 .handler = cortex_a_handle_cache_info_command,
3480                 .mode = COMMAND_EXEC,
3481                 .help = "display information about target caches",
3482                 .usage = "",
3483         },
3484         {
3485                 .name = "dbginit",
3486                 .handler = cortex_a_handle_dbginit_command,
3487                 .mode = COMMAND_EXEC,
3488                 .help = "Initialize core debug",
3489                 .usage = "",
3490         },
3491         {
3492                 .name = "maskisr",
3493                 .handler = handle_cortex_a_mask_interrupts_command,
3494                 .mode = COMMAND_EXEC,
3495                 .help = "mask cortex_r4 interrupts",
3496                 .usage = "['on'|'off']",
3497         },
3498
3499         COMMAND_REGISTRATION_DONE
3500 };
3501 static const struct command_registration cortex_r4_command_handlers[] = {
3502         {
3503                 .chain = arm_command_handlers,
3504         },
3505         {
3506                 .chain = armv7a_command_handlers,
3507         },
3508         {
3509                 .name = "cortex_r4",
3510                 .mode = COMMAND_ANY,
3511                 .help = "Cortex-R4 command group",
3512                 .usage = "",
3513                 .chain = cortex_r4_exec_command_handlers,
3514         },
3515         COMMAND_REGISTRATION_DONE
3516 };
3517
3518 struct target_type cortexr4_target = {
3519         .name = "cortex_r4",
3520
3521         .poll = cortex_a_poll,
3522         .arch_state = armv7a_arch_state,
3523
3524         .halt = cortex_a_halt,
3525         .resume = cortex_a_resume,
3526         .step = cortex_a_step,
3527
3528         .assert_reset = cortex_a_assert_reset,
3529         .deassert_reset = cortex_a_deassert_reset,
3530
3531         /* REVISIT allow exporting VFP3 registers ... */
3532         .get_gdb_reg_list = arm_get_gdb_reg_list,
3533
3534         .read_memory = cortex_a_read_memory,
3535         .write_memory = cortex_a_write_memory,
3536
3537         .checksum_memory = arm_checksum_memory,
3538         .blank_check_memory = arm_blank_check_memory,
3539
3540         .run_algorithm = armv4_5_run_algorithm,
3541
3542         .add_breakpoint = cortex_a_add_breakpoint,
3543         .add_context_breakpoint = cortex_a_add_context_breakpoint,
3544         .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
3545         .remove_breakpoint = cortex_a_remove_breakpoint,
3546         .add_watchpoint = NULL,
3547         .remove_watchpoint = NULL,
3548
3549         .commands = cortex_r4_command_handlers,
3550         .target_create = cortex_r4_target_create,
3551         .init_target = cortex_a_init_target,
3552         .examine = cortex_a_examine,
3553         .deinit_target = cortex_a_deinit_target,
3554 };