1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
32 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
34 #define SYSTEM_CONTROL_BASE 0x400FE000
36 #define ITM_TER0 0xE0000E00
37 #define ITM_TPR 0xE0000E40
38 #define ITM_TCR 0xE0000E80
39 #define ITM_LAR 0xE0000FB0
40 #define ITM_LAR_KEY 0xC5ACCE55
42 #define CPUID 0xE000ED00
43 /* Debug Control Block */
44 #define DCB_DHCSR 0xE000EDF0
45 #define DCB_DCRSR 0xE000EDF4
46 #define DCB_DCRDR 0xE000EDF8
47 #define DCB_DEMCR 0xE000EDFC
49 #define DCRSR_WnR (1 << 16)
51 #define DWT_CTRL 0xE0001000
52 #define DWT_CYCCNT 0xE0001004
53 #define DWT_COMP0 0xE0001020
54 #define DWT_MASK0 0xE0001024
55 #define DWT_FUNCTION0 0xE0001028
57 #define FP_CTRL 0xE0002000
58 #define FP_REMAP 0xE0002004
59 #define FP_COMP0 0xE0002008
60 #define FP_COMP1 0xE000200C
61 #define FP_COMP2 0xE0002010
62 #define FP_COMP3 0xE0002014
63 #define FP_COMP4 0xE0002018
64 #define FP_COMP5 0xE000201C
65 #define FP_COMP6 0xE0002020
66 #define FP_COMP7 0xE0002024
68 #define FPU_CPACR 0xE000ED88
69 #define FPU_FPCCR 0xE000EF34
70 #define FPU_FPCAR 0xE000EF38
71 #define FPU_FPDSCR 0xE000EF3C
73 #define TPIU_SSPSR 0xE0040000
74 #define TPIU_CSPSR 0xE0040004
75 #define TPIU_ACPR 0xE0040010
76 #define TPIU_SPPR 0xE00400F0
77 #define TPIU_FFSR 0xE0040300
78 #define TPIU_FFCR 0xE0040304
79 #define TPIU_FSCR 0xE0040308
81 /* DCB_DHCSR bit and field definitions */
82 #define DBGKEY (0xA05F << 16)
83 #define C_DEBUGEN (1 << 0)
84 #define C_HALT (1 << 1)
85 #define C_STEP (1 << 2)
86 #define C_MASKINTS (1 << 3)
87 #define S_REGRDY (1 << 16)
88 #define S_HALT (1 << 17)
89 #define S_SLEEP (1 << 18)
90 #define S_LOCKUP (1 << 19)
91 #define S_RETIRE_ST (1 << 24)
92 #define S_RESET_ST (1 << 25)
94 /* DCB_DEMCR bit and field definitions */
95 #define TRCENA (1 << 24)
96 #define VC_HARDERR (1 << 10)
97 #define VC_INTERR (1 << 9)
98 #define VC_BUSERR (1 << 8)
99 #define VC_STATERR (1 << 7)
100 #define VC_CHKERR (1 << 6)
101 #define VC_NOCPERR (1 << 5)
102 #define VC_MMERR (1 << 4)
103 #define VC_CORERESET (1 << 0)
105 #define NVIC_ICTR 0xE000E004
106 #define NVIC_ISE0 0xE000E100
107 #define NVIC_ICSR 0xE000ED04
108 #define NVIC_AIRCR 0xE000ED0C
109 #define NVIC_SHCSR 0xE000ED24
110 #define NVIC_CFSR 0xE000ED28
111 #define NVIC_MMFSRb 0xE000ED28
112 #define NVIC_BFSRb 0xE000ED29
113 #define NVIC_USFSRh 0xE000ED2A
114 #define NVIC_HFSR 0xE000ED2C
115 #define NVIC_DFSR 0xE000ED30
116 #define NVIC_MMFAR 0xE000ED34
117 #define NVIC_BFAR 0xE000ED38
119 /* NVIC_AIRCR bits */
120 #define AIRCR_VECTKEY (0x5FA << 16)
121 #define AIRCR_SYSRESETREQ (1 << 2)
122 #define AIRCR_VECTCLRACTIVE (1 << 1)
123 #define AIRCR_VECTRESET (1 << 0)
124 /* NVIC_SHCSR bits */
125 #define SHCSR_BUSFAULTENA (1 << 17)
127 #define DFSR_HALTED 1
129 #define DFSR_DWTTRAP 4
130 #define DFSR_VCATCH 8
133 #define FPCR_LITERAL 1
134 #define FPCR_REPLACE_REMAP (0 << 30)
135 #define FPCR_REPLACE_BKPT_LOW (1 << 30)
136 #define FPCR_REPLACE_BKPT_HIGH (2 << 30)
137 #define FPCR_REPLACE_BKPT_BOTH (3 << 30)
139 struct cortex_m_fp_comparator {
143 uint32_t fpcr_address;
146 struct cortex_m_dwt_comparator {
151 uint32_t dwt_comparator_address;
154 enum cortex_m_soft_reset_config {
155 CORTEX_M_RESET_SYSRESETREQ,
156 CORTEX_M_RESET_VECTRESET,
159 enum cortex_m_isrmasking_mode {
160 CORTEX_M_ISRMASK_AUTO,
161 CORTEX_M_ISRMASK_OFF,
165 struct cortex_m_common {
168 /* Context information */
170 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
171 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
173 /* Flash Patch and Breakpoint (FPB) */
176 int fp_code_available;
180 struct cortex_m_fp_comparator *fp_comparator_list;
182 /* Data Watchpoint and Trace (DWT) */
184 int dwt_comp_available;
185 struct cortex_m_dwt_comparator *dwt_comparator_list;
186 struct reg_cache *dwt_cache;
188 enum cortex_m_soft_reset_config soft_reset_config;
190 enum cortex_m_isrmasking_mode isrmasking_mode;
192 struct armv7m_common armv7m;
195 static inline struct cortex_m_common *
196 target_to_cm(struct target *target)
198 return container_of(target->arch_info,
199 struct cortex_m_common, armv7m);
202 int cortex_m_examine(struct target *target);
203 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
204 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
205 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
206 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
207 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
208 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
209 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
210 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
211 void cortex_m_enable_breakpoints(struct target *target);
212 void cortex_m_enable_watchpoints(struct target *target);
213 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
214 void cortex_m_deinit_target(struct target *target);
216 #endif /* CORTEX_M_H */