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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FBP remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54
  55 /* forward declarations */
  56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58 static void cortex_m3_enable_watchpoints(struct target *target);
  59 static int cortex_m3_store_core_reg_u32(struct target *target,
  60                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  61
  62 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
  63                 uint32_t *value, int regnum)
  64 {
  65         int retval;
  66         uint32_t dcrdr;
  67
  68         /* because the DCB_DCRDR is used for the emulated dcc channel
  69          * we have to save/restore the DCB_DCRDR when used */
  70
  71         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  72
  73         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  74         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  75         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  76
  77         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  78         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  79         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  80
  81         retval = jtagdp_transaction_endcheck(swjdp);
  82
  83         /* restore DCB_DCRDR - this needs to be in a seperate
  84          * transaction otherwise the emulated DCC channel breaks */
  85         if (retval == ERROR_OK)
  86                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  87
  88         return retval;
  89 }
  90
  91 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
  92                 uint32_t value, int regnum)
  93 {
  94         int retval;
  95         uint32_t dcrdr;
  96
  97         /* because the DCB_DCRDR is used for the emulated dcc channel
  98          * we have to save/restore the DCB_DCRDR when used */
  99
 100         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 101
 102         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 103         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 104         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 105
 106         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 107         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 108         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 109
 110         retval = jtagdp_transaction_endcheck(swjdp);
 111
 112         /* restore DCB_DCRDR - this needs to be in a seperate
 113          * transaction otherwise the emulated DCC channel breaks */
 114         if (retval == ERROR_OK)
 115                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 116
 117         return retval;
 118 }
 119
 120 static int cortex_m3_write_debug_halt_mask(struct target *target,
 121                 uint32_t mask_on, uint32_t mask_off)
 122 {
 123         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 124         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 125
 126         /* mask off status bits */
 127         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 128         /* create new register mask */
 129         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 130
 131         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 132 }
 133
 134 static int cortex_m3_clear_halt(struct target *target)
 135 {
 136         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 137         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 138
 139         /* clear step if any */
 140         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 141
 142         /* Read Debug Fault Status Register */
 143         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 144
 145         /* Clear Debug Fault Status */
 146         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 147         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 148
 149         return ERROR_OK;
 150 }
 151
 152 static int cortex_m3_single_step_core(struct target *target)
 153 {
 154         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 155         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 156         uint32_t dhcsr_save;
 157
 158         /* backup dhcsr reg */
 159         dhcsr_save = cortex_m3->dcb_dhcsr;
 160
 161         /* Mask interrupts before clearing halt, if done already.  This avoids
 162          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 163          * HALT can put the core into an unknown state.
 164          */
 165         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 166                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 167                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 168         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 169                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 170         LOG_DEBUG(" ");
 171
 172         /* restore dhcsr reg */
 173         cortex_m3->dcb_dhcsr = dhcsr_save;
 174         cortex_m3_clear_halt(target);
 175
 176         return ERROR_OK;
 177 }
 178
 179 static int cortex_m3_endreset_event(struct target *target)
 180 {
 181         int i;
 182         uint32_t dcb_demcr;
 183         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 184         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 185         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 186         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 187         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 188
 189         /* REVISIT The four debug monitor bits are currently ignored... */
 190         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 191         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 192
 193         /* this register is used for emulated dcc channel */
 194         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 195
 196         /* Enable debug requests */
 197         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 198         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 199                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 200
 201         /* clear any interrupt masking */
 202         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 203
 204         /* Enable features controlled by ITM and DWT blocks, and catch only
 205          * the vectors we were told to pay attention to.
 206          *
 207          * Target firmware is responsible for all fault handling policy
 208          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 209          * or manual updates to the NVIC SHCSR and CCR registers.
 210          */
 211         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 212
 213         /* Paranoia: evidently some (early?) chips don't preserve all the
 214          * debug state (including FBP, DWT, etc) across reset...
 215          */
 216
 217         /* Enable FPB */
 218         target_write_u32(target, FP_CTRL, 3);
 219         cortex_m3->fpb_enabled = 1;
 220
 221         /* Restore FPB registers */
 222         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 223         {
 224                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 225         }
 226
 227         /* Restore DWT registers */
 228         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 229         {
 230                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 231                                 dwt_list[i].comp);
 232                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 233                                 dwt_list[i].mask);
 234                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 235                                 dwt_list[i].function);
 236         }
 237         jtagdp_transaction_endcheck(swjdp);
 238
 239         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 240
 241         /* make sure we have latest dhcsr flags */
 242         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 243
 244         return ERROR_OK;
 245 }
 246
 247 static int cortex_m3_examine_debug_reason(struct target *target)
 248 {
 249         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 250
 251         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 252         /* only check the debug reason if we don't know it already */
 253
 254         if ((target->debug_reason != DBG_REASON_DBGRQ)
 255                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 256         {
 257                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 258                 {
 259                         target->debug_reason = DBG_REASON_BREAKPOINT;
 260                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 261                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 262                 }
 263                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 264                         target->debug_reason = DBG_REASON_WATCHPOINT;
 265                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 266                         target->debug_reason = DBG_REASON_BREAKPOINT;
 267                 else /* EXTERNAL, HALTED */
 268                         target->debug_reason = DBG_REASON_UNDEFINED;
 269         }
 270
 271         return ERROR_OK;
 272 }
 273
 274 static int cortex_m3_examine_exception_reason(struct target *target)
 275 {
 276         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 277         struct armv7m_common *armv7m = target_to_armv7m(target);
 278         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 279
 280         mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 281         switch (armv7m->exception_number)
 282         {
 283                 case 2: /* NMI */
 284                         break;
 285                 case 3: /* Hard Fault */
 286                         mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 287                         if (except_sr & 0x40000000)
 288                         {
 289                                 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 290                         }
 291                         break;
 292                 case 4: /* Memory Management */
 293                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 294                         mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 295                         break;
 296                 case 5: /* Bus Fault */
 297                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 298                         mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 299                         break;
 300                 case 6: /* Usage Fault */
 301                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 302                         break;
 303                 case 11:        /* SVCall */
 304                         break;
 305                 case 12:        /* Debug Monitor */
 306                         mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 307                         break;
 308                 case 14:        /* PendSV */
 309                         break;
 310                 case 15:        /* SysTick */
 311                         break;
 312                 default:
 313                         except_sr = 0;
 314                         break;
 315         }
 316         jtagdp_transaction_endcheck(swjdp);
 317         LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 318                 shcsr, except_sr, cfsr, except_ar);
 319         return ERROR_OK;
 320 }
 321
 322 /* PSP is used in some thread modes */
 323 static const int armv7m_psp_reg_map[17] = {
 324         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 325         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 326         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 327         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 328         ARMV7M_xPSR,
 329 };
 330
 331 /* MSP is used in handler and some thread modes */
 332 static const int armv7m_msp_reg_map[17] = {
 333         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 334         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 335         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 336         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 337         ARMV7M_xPSR,
 338 };
 339
 340 static int cortex_m3_debug_entry(struct target *target)
 341 {
 342         int i;
 343         uint32_t xPSR;
 344         int retval;
 345         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 346         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 347         struct arm *arm = &armv7m->arm;
 348         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 349         struct reg *r;
 350
 351         LOG_DEBUG(" ");
 352
 353         cortex_m3_clear_halt(target);
 354         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 355
 356         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 357                 return retval;
 358
 359         /* Examine target state and mode */
 360         /* First load register acessible through core debug port*/
 361         int num_regs = armv7m->core_cache->num_regs;
 362
 363         for (i = 0; i < num_regs; i++)
 364         {
 365                 if (!armv7m->core_cache->reg_list[i].valid)
 366                         armv7m->read_core_reg(target, i);
 367         }
 368
 369         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 370         xPSR = buf_get_u32(r->value, 0, 32);
 371
 372 #ifdef ARMV7_GDB_HACKS
 373         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 374          * Instead, each CM3 should have its own dummy value...
 375          */
 376         /* copy real xpsr reg for gdb, setting thumb bit */
 377         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 378         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 379         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 380         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 381 #endif
 382
 383         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 384         if (xPSR & 0xf00)
 385         {
 386                 r->dirty = r->valid;
 387                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 388         }
 389
 390         /* Are we in an exception handler */
 391         if (xPSR & 0x1FF)
 392         {
 393                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 394                 armv7m->exception_number = (xPSR & 0x1FF);
 395
 396                 arm->core_mode = ARM_MODE_HANDLER;
 397                 arm->map = armv7m_msp_reg_map;
 398         }
 399         else
 400         {
 401                 unsigned control = buf_get_u32(armv7m->core_cache
 402                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 403
 404                 /* is this thread privileged? */
 405                 armv7m->core_mode = control & 1;
 406                 arm->core_mode = armv7m->core_mode
 407                                 ? ARM_MODE_USER_THREAD
 408                                 : ARM_MODE_THREAD;
 409
 410                 /* which stack is it using? */
 411                 if (control & 2)
 412                         arm->map = armv7m_psp_reg_map;
 413                 else
 414                         arm->map = armv7m_msp_reg_map;
 415
 416                 armv7m->exception_number = 0;
 417         }
 418
 419         if (armv7m->exception_number)
 420         {
 421                 cortex_m3_examine_exception_reason(target);
 422         }
 423
 424         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 425                 armv7m_mode_strings[armv7m->core_mode],
 426                 *(uint32_t*)(arm->pc->value),
 427                 target_state_name(target));
 428
 429         if (armv7m->post_debug_entry)
 430                 armv7m->post_debug_entry(target);
 431
 432         return ERROR_OK;
 433 }
 434
 435 static int cortex_m3_poll(struct target *target)
 436 {
 437         int retval;
 438         enum target_state prev_target_state = target->state;
 439         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 440         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 441
 442         /* Read from Debug Halting Control and Status Register */
 443         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 444         if (retval != ERROR_OK)
 445         {
 446                 target->state = TARGET_UNKNOWN;
 447                 return retval;
 448         }
 449
 450         /* Recover from lockup.  See ARMv7-M architecture spec,
 451          * section B1.5.15 "Unrecoverable exception cases".
 452          *
 453          * REVISIT Is there a better way to report and handle this?
 454          */
 455         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 456                 LOG_WARNING("%s -- clearing lockup after double fault",
 457                                 target_name(target));
 458                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 459                 target->debug_reason = DBG_REASON_DBGRQ;
 460
 461                 /* refresh status bits */
 462                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 463         }
 464
 465         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 466         {
 467                 /* check if still in reset */
 468                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 469
 470                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 471                 {
 472                         target->state = TARGET_RESET;
 473                         return ERROR_OK;
 474                 }
 475         }
 476
 477         if (target->state == TARGET_RESET)
 478         {
 479                 /* Cannot switch context while running so endreset is
 480                  * called with target->state == TARGET_RESET
 481                  */
 482                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 483                                 cortex_m3->dcb_dhcsr);
 484                 cortex_m3_endreset_event(target);
 485                 target->state = TARGET_RUNNING;
 486                 prev_target_state = TARGET_RUNNING;
 487         }
 488
 489         if (cortex_m3->dcb_dhcsr & S_HALT)
 490         {
 491                 target->state = TARGET_HALTED;
 492
 493                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 494                 {
 495                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 496                                 return retval;
 497
 498                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 499                 }
 500                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 501                 {
 502                         LOG_DEBUG(" ");
 503                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 504                                 return retval;
 505
 506                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 507                 }
 508         }
 509
 510         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 511          * How best to model low power modes?
 512          */
 513
 514         if (target->state == TARGET_UNKNOWN)
 515         {
 516                 /* check if processor is retiring instructions */
 517                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 518                 {
 519                         target->state = TARGET_RUNNING;
 520                         return ERROR_OK;
 521                 }
 522         }
 523
 524         return ERROR_OK;
 525 }
 526
 527 static int cortex_m3_halt(struct target *target)
 528 {
 529         LOG_DEBUG("target->state: %s",
 530                 target_state_name(target));
 531
 532         if (target->state == TARGET_HALTED)
 533         {
 534                 LOG_DEBUG("target was already halted");
 535                 return ERROR_OK;
 536         }
 537
 538         if (target->state == TARGET_UNKNOWN)
 539         {
 540                 LOG_WARNING("target was in unknown state when halt was requested");
 541         }
 542
 543         if (target->state == TARGET_RESET)
 544         {
 545                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 546                 {
 547                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 548                         return ERROR_TARGET_FAILURE;
 549                 }
 550                 else
 551                 {
 552                         /* we came here in a reset_halt or reset_init sequence
 553                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 554                          */
 555                         target->debug_reason = DBG_REASON_DBGRQ;
 556
 557                         return ERROR_OK;
 558                 }
 559         }
 560
 561         /* Write to Debug Halting Control and Status Register */
 562         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 563
 564         target->debug_reason = DBG_REASON_DBGRQ;
 565
 566         return ERROR_OK;
 567 }
 568
 569 static int cortex_m3_soft_reset_halt(struct target *target)
 570 {
 571         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 572         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 573         uint32_t dcb_dhcsr = 0;
 574         int retval, timeout = 0;
 575
 576         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 577         mem_ap_write_u32(swjdp, DCB_DEMCR,
 578                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 579
 580         /* Request a core-only reset */
 581         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 582                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 583         target->state = TARGET_RESET;
 584
 585         /* registers are now invalid */
 586         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 587
 588         while (timeout < 100)
 589         {
 590                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 591                 if (retval == ERROR_OK)
 592                 {
 593                         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 594                                         &cortex_m3->nvic_dfsr);
 595                         if ((dcb_dhcsr & S_HALT)
 596                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 597                         {
 598                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 599                                         "DFSR 0x%08x",
 600                                         (unsigned) dcb_dhcsr,
 601                                         (unsigned) cortex_m3->nvic_dfsr);
 602                                 cortex_m3_poll(target);
 603                                 /* FIXME restore user's vector catch config */
 604                                 return ERROR_OK;
 605                         }
 606                         else
 607                                 LOG_DEBUG("waiting for system reset-halt, "
 608                                         "DHCSR 0x%08x, %d ms",
 609                                         (unsigned) dcb_dhcsr, timeout);
 610                 }
 611                 timeout++;
 612                 alive_sleep(1);
 613         }
 614
 615         return ERROR_OK;
 616 }
 617
 618 static void cortex_m3_enable_breakpoints(struct target *target)
 619 {
 620         struct breakpoint *breakpoint = target->breakpoints;
 621
 622         /* set any pending breakpoints */
 623         while (breakpoint)
 624         {
 625                 if (!breakpoint->set)
 626                         cortex_m3_set_breakpoint(target, breakpoint);
 627                 breakpoint = breakpoint->next;
 628         }
 629 }
 630
 631 static int cortex_m3_resume(struct target *target, int current,
 632                 uint32_t address, int handle_breakpoints, int debug_execution)
 633 {
 634         struct armv7m_common *armv7m = target_to_armv7m(target);
 635         struct breakpoint *breakpoint = NULL;
 636         uint32_t resume_pc;
 637         struct reg *r;
 638
 639         if (target->state != TARGET_HALTED)
 640         {
 641                 LOG_WARNING("target not halted");
 642                 return ERROR_TARGET_NOT_HALTED;
 643         }
 644
 645         if (!debug_execution)
 646         {
 647                 target_free_all_working_areas(target);
 648                 cortex_m3_enable_breakpoints(target);
 649                 cortex_m3_enable_watchpoints(target);
 650         }
 651
 652         if (debug_execution)
 653         {
 654                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 655
 656                 /* Disable interrupts */
 657                 /* We disable interrupts in the PRIMASK register instead of
 658                  * masking with C_MASKINTS.  This is probably the same issue
 659                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 660                  * in parallel with disabled interrupts can cause local faults
 661                  * to not be taken.
 662                  *
 663                  * REVISIT this clearly breaks non-debug execution, since the
 664                  * PRIMASK register state isn't saved/restored...  workaround
 665                  * by never resuming app code after debug execution.
 666                  */
 667                 buf_set_u32(r->value, 0, 1, 1);
 668                 r->dirty = true;
 669                 r->valid = true;
 670
 671                 /* Make sure we are in Thumb mode */
 672                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 673                 buf_set_u32(r->value, 24, 1, 1);
 674                 r->dirty = true;
 675                 r->valid = true;
 676         }
 677
 678         /* current = 1: continue on current pc, otherwise continue at <address> */
 679         r = armv7m->arm.pc;
 680         if (!current)
 681         {
 682                 buf_set_u32(r->value, 0, 32, address);
 683                 r->dirty = true;
 684                 r->valid = true;
 685         }
 686
 687         /* if we halted last time due to a bkpt instruction
 688          * then we have to manually step over it, otherwise
 689          * the core will break again */
 690
 691         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 692                         && !debug_execution)
 693         {
 694                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 695         }
 696
 697         resume_pc = buf_get_u32(r->value, 0, 32);
 698
 699         armv7m_restore_context(target);
 700
 701         /* the front-end may request us not to handle breakpoints */
 702         if (handle_breakpoints)
 703         {
 704                 /* Single step past breakpoint at current address */
 705                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 706                 {
 707                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 708                                           breakpoint->address,
 709                                           breakpoint->unique_id);
 710                         cortex_m3_unset_breakpoint(target, breakpoint);
 711                         cortex_m3_single_step_core(target);
 712                         cortex_m3_set_breakpoint(target, breakpoint);
 713                 }
 714         }
 715
 716         /* Restart core */
 717         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 718
 719         target->debug_reason = DBG_REASON_NOTHALTED;
 720
 721         /* registers are now invalid */
 722         register_cache_invalidate(armv7m->core_cache);
 723
 724         if (!debug_execution)
 725         {
 726                 target->state = TARGET_RUNNING;
 727                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 728                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 729         }
 730         else
 731         {
 732                 target->state = TARGET_DEBUG_RUNNING;
 733                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 734                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 735         }
 736
 737         return ERROR_OK;
 738 }
 739
 740 /* int irqstepcount = 0; */
 741 static int cortex_m3_step(struct target *target, int current,
 742                 uint32_t address, int handle_breakpoints)
 743 {
 744         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 745         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 746         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 747         struct breakpoint *breakpoint = NULL;
 748         struct reg *pc = armv7m->arm.pc;
 749         bool bkpt_inst_found = false;
 750
 751         if (target->state != TARGET_HALTED)
 752         {
 753                 LOG_WARNING("target not halted");
 754                 return ERROR_TARGET_NOT_HALTED;
 755         }
 756
 757         /* current = 1: continue on current pc, otherwise continue at <address> */
 758         if (!current)
 759                 buf_set_u32(pc->value, 0, 32, address);
 760
 761         /* the front-end may request us not to handle breakpoints */
 762         if (handle_breakpoints) {
 763                 breakpoint = breakpoint_find(target,
 764                                 buf_get_u32(pc->value, 0, 32));
 765                 if (breakpoint)
 766                         cortex_m3_unset_breakpoint(target, breakpoint);
 767         }
 768
 769         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 770
 771         target->debug_reason = DBG_REASON_SINGLESTEP;
 772
 773         armv7m_restore_context(target);
 774
 775         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 776
 777         /* if no bkpt instruction is found at pc then we can perform
 778          * a normal step, otherwise we have to manually step over the bkpt
 779          * instruction - as such simulate a step */
 780         if (bkpt_inst_found == false)
 781         {
 782                 /* set step and clear halt */
 783                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 784         }
 785
 786         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 787
 788         /* registers are now invalid */
 789         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 790
 791         if (breakpoint)
 792                 cortex_m3_set_breakpoint(target, breakpoint);
 793
 794         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 795                         " nvic_icsr = 0x%" PRIx32,
 796                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 797
 798         cortex_m3_debug_entry(target);
 799         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 800
 801         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 802                         " nvic_icsr = 0x%" PRIx32,
 803                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 804
 805         return ERROR_OK;
 806 }
 807
 808 static int cortex_m3_assert_reset(struct target *target)
 809 {
 810         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 811         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 812         int assert_srst = 1;
 813
 814         LOG_DEBUG("target->state: %s",
 815                 target_state_name(target));
 816
 817         enum reset_types jtag_reset_config = jtag_get_reset_config();
 818
 819         /*
 820          * We can reset Cortex-M3 targets using just the NVIC without
 821          * requiring SRST, getting a SoC reset (or a core-only reset)
 822          * instead of a system reset.
 823          */
 824         if (!(jtag_reset_config & RESET_HAS_SRST))
 825                 assert_srst = 0;
 826
 827         /* Enable debug requests */
 828         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 829         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 830                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 831
 832         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 833
 834         if (!target->reset_halt)
 835         {
 836                 /* Set/Clear C_MASKINTS in a separate operation */
 837                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 838                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 839                                         DBGKEY | C_DEBUGEN | C_HALT);
 840
 841                 /* clear any debug flags before resuming */
 842                 cortex_m3_clear_halt(target);
 843
 844                 /* clear C_HALT in dhcsr reg */
 845                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 846         }
 847         else
 848         {
 849                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 850                  *
 851                  * REVISIT catching BUSERR presumably helps to defend against
 852                  * bad vector table entries.  Should this include MMERR or
 853                  * other flags too?
 854                  */
 855                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 856                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 857         }
 858
 859         /*
 860          * When nRST is asserted on most Stellaris devices, it clears some of
 861          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 862          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 863          * chips.  (Only power-on reset should affect debug state, beyond a
 864          * few specified bits; not the chip's nRST input, wired to SRST.)
 865          *
 866          * REVISIT current errata specs don't seem to cover this issue.
 867          * Do we have more details than this email?
 868          *   https://lists.berlios.de/pipermail
 869          *      /openocd-development/2008-August/003065.html
 870          */
 871         if (strcmp(target->variant, "lm3s") == 0)
 872         {
 873                 /* Check for silicon revisions with the issue. */
 874                 uint32_t did0;
 875
 876                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 877                 {
 878                         switch ((did0 >> 16) & 0xff)
 879                         {
 880                                 case 0:
 881                                         /* all Sandstorm suffer issue */
 882                                         assert_srst = 0;
 883                                         break;
 884
 885                                 case 1:
 886                                 case 3:
 887                                         /* Fury and DustDevil rev A have
 888                                          * this nRST problem.  It should
 889                                          * be fixed in rev B silicon.
 890                                          */
 891                                         if (((did0 >> 8) & 0xff) == 0)
 892                                                 assert_srst = 0;
 893                                         break;
 894                                 case 4:
 895                                         /* Tempest should be fine. */
 896                                         break;
 897                         }
 898                 }
 899         }
 900
 901         if (assert_srst)
 902         {
 903                 /* default to asserting srst */
 904                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 905                 {
 906                         jtag_add_reset(1, 1);
 907                 }
 908                 else
 909                 {
 910                         jtag_add_reset(0, 1);
 911                 }
 912         }
 913         else
 914         {
 915                 /* Use a standard Cortex-M3 software reset mechanism.
 916                  * SYSRESETREQ will reset SoC peripherals outside the
 917                  * core, like watchdog timers, if the SoC wires it up
 918                  * correctly.  Else VECRESET can reset just the core.
 919                  */
 920                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 921                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 922                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 923
 924                 {
 925                         /* I do not know why this is necessary, but it
 926                          * fixes strange effects (step/resume cause NMI
 927                          * after reset) on LM3S6918 -- Michael Schwingen
 928                          */
 929                         uint32_t tmp;
 930                         mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 931                 }
 932         }
 933
 934         target->state = TARGET_RESET;
 935         jtag_add_sleep(50000);
 936
 937         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 938
 939         if (target->reset_halt)
 940         {
 941                 int retval;
 942                 if ((retval = target_halt(target)) != ERROR_OK)
 943                         return retval;
 944         }
 945
 946         return ERROR_OK;
 947 }
 948
 949 static int cortex_m3_deassert_reset(struct target *target)
 950 {
 951         LOG_DEBUG("target->state: %s",
 952                 target_state_name(target));
 953
 954         /* deassert reset lines */
 955         jtag_add_reset(0, 0);
 956
 957         return ERROR_OK;
 958 }
 959
 960 static int
 961 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 962 {
 963         int retval;
 964         int fp_num = 0;
 965         uint32_t hilo;
 966         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 967         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
 968
 969         if (breakpoint->set)
 970         {
 971                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
 972                 return ERROR_OK;
 973         }
 974
 975         if (cortex_m3->auto_bp_type)
 976         {
 977                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 978         }
 979
 980         if (breakpoint->type == BKPT_HARD)
 981         {
 982                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
 983                         fp_num++;
 984                 if (fp_num >= cortex_m3->fp_num_code)
 985                 {
 986                         LOG_ERROR("Can not find free FPB Comparator!");
 987                         return ERROR_FAIL;
 988                 }
 989                 breakpoint->set = fp_num + 1;
 990                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
 991                 comparator_list[fp_num].used = 1;
 992                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 993                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 994                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
 995                 if (!cortex_m3->fpb_enabled)
 996                 {
 997                         LOG_DEBUG("FPB wasn't enabled, do it now");
 998                         target_write_u32(target, FP_CTRL, 3);
 999                 }
1000         }
1001         else if (breakpoint->type == BKPT_SOFT)
1002         {
1003                 uint8_t code[4];
1004
1005                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1006                  * semihosting; don't use that.  Otherwise the BKPT
1007                  * parameter is arbitrary.
1008                  */
1009                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1010                 retval = target_read_memory(target,
1011                                 breakpoint->address & 0xFFFFFFFE,
1012                                 breakpoint->length, 1,
1013                                 breakpoint->orig_instr);
1014                 if (retval != ERROR_OK)
1015                         return retval;
1016                 retval = target_write_memory(target,
1017                                 breakpoint->address & 0xFFFFFFFE,
1018                                 breakpoint->length, 1,
1019                                 code);
1020                 if (retval != ERROR_OK)
1021                         return retval;
1022                 breakpoint->set = true;
1023         }
1024
1025         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1026                           breakpoint->unique_id,
1027                           (int)(breakpoint->type),
1028                           breakpoint->address,
1029                           breakpoint->length,
1030                           breakpoint->set);
1031
1032         return ERROR_OK;
1033 }
1034
1035 static int
1036 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1037 {
1038         int retval;
1039         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1040         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1041
1042         if (!breakpoint->set)
1043         {
1044                 LOG_WARNING("breakpoint not set");
1045                 return ERROR_OK;
1046         }
1047
1048         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1049                           breakpoint->unique_id,
1050                           (int)(breakpoint->type),
1051                           breakpoint->address,
1052                           breakpoint->length,
1053                           breakpoint->set);
1054
1055         if (breakpoint->type == BKPT_HARD)
1056         {
1057                 int fp_num = breakpoint->set - 1;
1058                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1059                 {
1060                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1061                         return ERROR_OK;
1062                 }
1063                 comparator_list[fp_num].used = 0;
1064                 comparator_list[fp_num].fpcr_value = 0;
1065                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1066         }
1067         else
1068         {
1069                 /* restore original instruction (kept in target endianness) */
1070                 if (breakpoint->length == 4)
1071                 {
1072                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1073                         {
1074                                 return retval;
1075                         }
1076                 }
1077                 else
1078                 {
1079                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1080                         {
1081                                 return retval;
1082                         }
1083                 }
1084         }
1085         breakpoint->set = false;
1086
1087         return ERROR_OK;
1088 }
1089
1090 static int
1091 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1092 {
1093         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1094
1095         if (cortex_m3->auto_bp_type)
1096         {
1097                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1098 #ifdef ARMV7_GDB_HACKS
1099                 if (breakpoint->length != 2) {
1100                         /* XXX Hack: Replace all breakpoints with length != 2 with
1101                          * a hardware breakpoint. */
1102                         breakpoint->type = BKPT_HARD;
1103                         breakpoint->length = 2;
1104                 }
1105 #endif
1106         }
1107
1108         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1109         {
1110                 LOG_INFO("flash patch comparator requested outside code memory region");
1111                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1112         }
1113
1114         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1115         {
1116                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1117                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1118         }
1119
1120         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1121         {
1122                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1123                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1124         }
1125
1126         if ((breakpoint->length != 2))
1127         {
1128                 LOG_INFO("only breakpoints of two bytes length supported");
1129                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1130         }
1131
1132         if (breakpoint->type == BKPT_HARD)
1133                 cortex_m3->fp_code_available--;
1134         cortex_m3_set_breakpoint(target, breakpoint);
1135
1136         return ERROR_OK;
1137 }
1138
1139 static int
1140 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1141 {
1142         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1143
1144         /* REVISIT why check? FBP can be updated with core running ... */
1145         if (target->state != TARGET_HALTED)
1146         {
1147                 LOG_WARNING("target not halted");
1148                 return ERROR_TARGET_NOT_HALTED;
1149         }
1150
1151         if (cortex_m3->auto_bp_type)
1152         {
1153                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1154         }
1155
1156         if (breakpoint->set)
1157         {
1158                 cortex_m3_unset_breakpoint(target, breakpoint);
1159         }
1160
1161         if (breakpoint->type == BKPT_HARD)
1162                 cortex_m3->fp_code_available++;
1163
1164         return ERROR_OK;
1165 }
1166
1167 static int
1168 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1169 {
1170         int dwt_num = 0;
1171         uint32_t mask, temp;
1172         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1173
1174         /* watchpoint params were validated earlier */
1175         mask = 0;
1176         temp = watchpoint->length;
1177         while (temp) {
1178                 temp >>= 1;
1179                 mask++;
1180         }
1181         mask--;
1182
1183         /* REVISIT Don't fully trust these "not used" records ... users
1184          * may set up breakpoints by hand, e.g. dual-address data value
1185          * watchpoint using comparator #1; comparator #0 matching cycle
1186          * count; send data trace info through ITM and TPIU; etc
1187          */
1188         struct cortex_m3_dwt_comparator *comparator;
1189
1190         for (comparator = cortex_m3->dwt_comparator_list;
1191                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1192                         comparator++, dwt_num++)
1193                 continue;
1194         if (dwt_num >= cortex_m3->dwt_num_comp)
1195         {
1196                 LOG_ERROR("Can not find free DWT Comparator");
1197                 return ERROR_FAIL;
1198         }
1199         comparator->used = 1;
1200         watchpoint->set = dwt_num + 1;
1201
1202         comparator->comp = watchpoint->address;
1203         target_write_u32(target, comparator->dwt_comparator_address + 0,
1204                         comparator->comp);
1205
1206         comparator->mask = mask;
1207         target_write_u32(target, comparator->dwt_comparator_address + 4,
1208                         comparator->mask);
1209
1210         switch (watchpoint->rw) {
1211         case WPT_READ:
1212                 comparator->function = 5;
1213                 break;
1214         case WPT_WRITE:
1215                 comparator->function = 6;
1216                 break;
1217         case WPT_ACCESS:
1218                 comparator->function = 7;
1219                 break;
1220         }
1221         target_write_u32(target, comparator->dwt_comparator_address + 8,
1222                         comparator->function);
1223
1224         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1225                         watchpoint->unique_id, dwt_num,
1226                         (unsigned) comparator->comp,
1227                         (unsigned) comparator->mask,
1228                         (unsigned) comparator->function);
1229         return ERROR_OK;
1230 }
1231
1232 static int
1233 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1234 {
1235         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1236         struct cortex_m3_dwt_comparator *comparator;
1237         int dwt_num;
1238
1239         if (!watchpoint->set)
1240         {
1241                 LOG_WARNING("watchpoint (wpid: %d) not set",
1242                                 watchpoint->unique_id);
1243                 return ERROR_OK;
1244         }
1245
1246         dwt_num = watchpoint->set - 1;
1247
1248         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1249                         watchpoint->unique_id, dwt_num,
1250                         (unsigned) watchpoint->address);
1251
1252         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1253         {
1254                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1255                 return ERROR_OK;
1256         }
1257
1258         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1259         comparator->used = 0;
1260         comparator->function = 0;
1261         target_write_u32(target, comparator->dwt_comparator_address + 8,
1262                         comparator->function);
1263
1264         watchpoint->set = false;
1265
1266         return ERROR_OK;
1267 }
1268
1269 static int
1270 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1271 {
1272         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1273
1274         if (cortex_m3->dwt_comp_available < 1)
1275         {
1276                 LOG_DEBUG("no comparators?");
1277                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1278         }
1279
1280         /* hardware doesn't support data value masking */
1281         if (watchpoint->mask != ~(uint32_t)0) {
1282                 LOG_DEBUG("watchpoint value masks not supported");
1283                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284         }
1285
1286         /* hardware allows address masks of up to 32K */
1287         unsigned mask;
1288
1289         for (mask = 0; mask < 16; mask++) {
1290                 if ((1u << mask) == watchpoint->length)
1291                         break;
1292         }
1293         if (mask == 16) {
1294                 LOG_DEBUG("unsupported watchpoint length");
1295                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1296         }
1297         if (watchpoint->address & ((1 << mask) - 1)) {
1298                 LOG_DEBUG("watchpoint address is unaligned");
1299                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1300         }
1301
1302         /* Caller doesn't seem to be able to describe watching for data
1303          * values of zero; that flags "no value".
1304          *
1305          * REVISIT This DWT may well be able to watch for specific data
1306          * values.  Requires comparator #1 to set DATAVMATCH and match
1307          * the data, and another comparator (DATAVADDR0) matching addr.
1308          */
1309         if (watchpoint->value) {
1310                 LOG_DEBUG("data value watchpoint not YET supported");
1311                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1312         }
1313
1314         cortex_m3->dwt_comp_available--;
1315         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1316
1317         return ERROR_OK;
1318 }
1319
1320 static int
1321 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1322 {
1323         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1324
1325         /* REVISIT why check? DWT can be updated with core running ... */
1326         if (target->state != TARGET_HALTED)
1327         {
1328                 LOG_WARNING("target not halted");
1329                 return ERROR_TARGET_NOT_HALTED;
1330         }
1331
1332         if (watchpoint->set)
1333         {
1334                 cortex_m3_unset_watchpoint(target, watchpoint);
1335         }
1336
1337         cortex_m3->dwt_comp_available++;
1338         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1339
1340         return ERROR_OK;
1341 }
1342
1343 static void cortex_m3_enable_watchpoints(struct target *target)
1344 {
1345         struct watchpoint *watchpoint = target->watchpoints;
1346
1347         /* set any pending watchpoints */
1348         while (watchpoint)
1349         {
1350                 if (!watchpoint->set)
1351                         cortex_m3_set_watchpoint(target, watchpoint);
1352                 watchpoint = watchpoint->next;
1353         }
1354 }
1355
1356 static int cortex_m3_load_core_reg_u32(struct target *target,
1357                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1358 {
1359         int retval;
1360         struct armv7m_common *armv7m = target_to_armv7m(target);
1361         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1362
1363         /* NOTE:  we "know" here that the register identifiers used
1364          * in the v7m header match the Cortex-M3 Debug Core Register
1365          * Selector values for R0..R15, xPSR, MSP, and PSP.
1366          */
1367         switch (num) {
1368         case 0 ... 18:
1369                 /* read a normal core register */
1370                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1371
1372                 if (retval != ERROR_OK)
1373                 {
1374                         LOG_ERROR("JTAG failure %i",retval);
1375                         return ERROR_JTAG_DEVICE_ERROR;
1376                 }
1377                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1378                 break;
1379
1380         case ARMV7M_PRIMASK:
1381         case ARMV7M_BASEPRI:
1382         case ARMV7M_FAULTMASK:
1383         case ARMV7M_CONTROL:
1384                 /* Cortex-M3 packages these four registers as bitfields
1385                  * in one Debug Core register.  So say r0 and r2 docs;
1386                  * it was removed from r1 docs, but still works.
1387                  */
1388                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1389
1390                 switch (num)
1391                 {
1392                         case ARMV7M_PRIMASK:
1393                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1394                                 break;
1395
1396                         case ARMV7M_BASEPRI:
1397                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1398                                 break;
1399
1400                         case ARMV7M_FAULTMASK:
1401                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1402                                 break;
1403
1404                         case ARMV7M_CONTROL:
1405                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1406                                 break;
1407                 }
1408
1409                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1410                 break;
1411
1412         default:
1413                 return ERROR_INVALID_ARGUMENTS;
1414         }
1415
1416         return ERROR_OK;
1417 }
1418
1419 static int cortex_m3_store_core_reg_u32(struct target *target,
1420                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1421 {
1422         int retval;
1423         uint32_t reg;
1424         struct armv7m_common *armv7m = target_to_armv7m(target);
1425         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1426
1427 #ifdef ARMV7_GDB_HACKS
1428         /* If the LR register is being modified, make sure it will put us
1429          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1430          * hack to deal with the fact that gdb will sometimes "forge"
1431          * return addresses, and doesn't set the LSB correctly (i.e., when
1432          * printing expressions containing function calls, it sets LR = 0.)
1433          * Valid exception return codes have bit 0 set too.
1434          */
1435         if (num == ARMV7M_R14)
1436                 value |= 0x01;
1437 #endif
1438
1439         /* NOTE:  we "know" here that the register identifiers used
1440          * in the v7m header match the Cortex-M3 Debug Core Register
1441          * Selector values for R0..R15, xPSR, MSP, and PSP.
1442          */
1443         switch (num) {
1444         case 0 ... 18:
1445                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1446                 if (retval != ERROR_OK)
1447                 {
1448                         struct reg *r;
1449
1450                         LOG_ERROR("JTAG failure %i", retval);
1451                         r = armv7m->core_cache->reg_list + num;
1452                         r->dirty = r->valid;
1453                         return ERROR_JTAG_DEVICE_ERROR;
1454                 }
1455                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1456                 break;
1457
1458         case ARMV7M_PRIMASK:
1459         case ARMV7M_BASEPRI:
1460         case ARMV7M_FAULTMASK:
1461         case ARMV7M_CONTROL:
1462                 /* Cortex-M3 packages these four registers as bitfields
1463                  * in one Debug Core register.  So say r0 and r2 docs;
1464                  * it was removed from r1 docs, but still works.
1465                  */
1466                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1467
1468                 switch (num)
1469                 {
1470                         case ARMV7M_PRIMASK:
1471                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1472                                 break;
1473
1474                         case ARMV7M_BASEPRI:
1475                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1476                                 break;
1477
1478                         case ARMV7M_FAULTMASK:
1479                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1480                                 break;
1481
1482                         case ARMV7M_CONTROL:
1483                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1484                                 break;
1485                 }
1486
1487                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1488
1489                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1490                 break;
1491
1492         default:
1493                 return ERROR_INVALID_ARGUMENTS;
1494         }
1495
1496         return ERROR_OK;
1497 }
1498
1499 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1500                 uint32_t size, uint32_t count, uint8_t *buffer)
1501 {
1502         struct armv7m_common *armv7m = target_to_armv7m(target);
1503         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1504         int retval = ERROR_INVALID_ARGUMENTS;
1505
1506         /* cortex_m3 handles unaligned memory access */
1507         if (count && buffer) {
1508                 switch (size) {
1509                 case 4:
1510                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1511                         break;
1512                 case 2:
1513                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1514                         break;
1515                 case 1:
1516                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1517                         break;
1518                 }
1519         }
1520
1521         return retval;
1522 }
1523
1524 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1525                 uint32_t size, uint32_t count, uint8_t *buffer)
1526 {
1527         struct armv7m_common *armv7m = target_to_armv7m(target);
1528         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1529         int retval = ERROR_INVALID_ARGUMENTS;
1530
1531         if (count && buffer) {
1532                 switch (size) {
1533                 case 4:
1534                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1535                         break;
1536                 case 2:
1537                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1538                         break;
1539                 case 1:
1540                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1541                         break;
1542                 }
1543         }
1544
1545         return retval;
1546 }
1547
1548 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1549                 uint32_t count, uint8_t *buffer)
1550 {
1551         return cortex_m3_write_memory(target, address, 4, count, buffer);
1552 }
1553
1554 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1555                 struct target *target)
1556 {
1557         armv7m_build_reg_cache(target);
1558         return ERROR_OK;
1559 }
1560
1561 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1562  * on r/w if the core is not running, and clear on resume or reset ... or
1563  * at least, in a post_restore_context() method.
1564  */
1565
1566 struct dwt_reg_state {
1567         struct target   *target;
1568         uint32_t        addr;
1569         uint32_t        value;  /* scratch/cache */
1570 };
1571
1572 static int cortex_m3_dwt_get_reg(struct reg *reg)
1573 {
1574         struct dwt_reg_state *state = reg->arch_info;
1575
1576         return target_read_u32(state->target, state->addr, &state->value);
1577 }
1578
1579 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1580 {
1581         struct dwt_reg_state *state = reg->arch_info;
1582
1583         return target_write_u32(state->target, state->addr,
1584                         buf_get_u32(buf, 0, reg->size));
1585 }
1586
1587 struct dwt_reg {
1588         uint32_t        addr;
1589         char            *name;
1590         unsigned        size;
1591 };
1592
1593 static struct dwt_reg dwt_base_regs[] = {
1594         { DWT_CTRL, "dwt_ctrl", 32, },
1595         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1596          * increments while the core is asleep.
1597          */
1598         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1599         /* plus some 8 bit counters, useful for profiling with TPIU */
1600 };
1601
1602 static struct dwt_reg dwt_comp[] = {
1603 #define DWT_COMPARATOR(i) \
1604                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1605                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1606                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1607         DWT_COMPARATOR(0),
1608         DWT_COMPARATOR(1),
1609         DWT_COMPARATOR(2),
1610         DWT_COMPARATOR(3),
1611 #undef DWT_COMPARATOR
1612 };
1613
1614 static const struct reg_arch_type dwt_reg_type = {
1615         .get = cortex_m3_dwt_get_reg,
1616         .set = cortex_m3_dwt_set_reg,
1617 };
1618
1619 static void
1620 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1621 {
1622         struct dwt_reg_state *state;
1623
1624         state = calloc(1, sizeof *state);
1625         if (!state)
1626                 return;
1627         state->addr = d->addr;
1628         state->target = t;
1629
1630         r->name = d->name;
1631         r->size = d->size;
1632         r->value = &state->value;
1633         r->arch_info = state;
1634         r->type = &dwt_reg_type;
1635 }
1636
1637 static void
1638 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1639 {
1640         uint32_t dwtcr;
1641         struct reg_cache *cache;
1642         struct cortex_m3_dwt_comparator *comparator;
1643         int reg, i;
1644
1645         target_read_u32(target, DWT_CTRL, &dwtcr);
1646         if (!dwtcr) {
1647                 LOG_DEBUG("no DWT");
1648                 return;
1649         }
1650
1651         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1652         cm3->dwt_comp_available = cm3->dwt_num_comp;
1653         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1654                         sizeof(struct cortex_m3_dwt_comparator));
1655         if (!cm3->dwt_comparator_list) {
1656 fail0:
1657                 cm3->dwt_num_comp = 0;
1658                 LOG_ERROR("out of mem");
1659                 return;
1660         }
1661
1662         cache = calloc(1, sizeof *cache);
1663         if (!cache) {
1664 fail1:
1665                 free(cm3->dwt_comparator_list);
1666                 goto fail0;
1667         }
1668         cache->name = "cortex-m3 dwt registers";
1669         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1670         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1671         if (!cache->reg_list) {
1672                 free(cache);
1673                 goto fail1;
1674         }
1675
1676         for (reg = 0; reg < 2; reg++)
1677                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1678                                 dwt_base_regs + reg);
1679
1680         comparator = cm3->dwt_comparator_list;
1681         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1682                 int j;
1683
1684                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1685                 for (j = 0; j < 3; j++, reg++)
1686                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1687                                         dwt_comp + 3 * i + j);
1688         }
1689
1690         *register_get_last_cache_p(&target->reg_cache) = cache;
1691         cm3->dwt_cache = cache;
1692
1693         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1694                         dwtcr, cm3->dwt_num_comp,
1695                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1696
1697         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1698          * implement single-address data value watchpoints ... so we
1699          * won't need to check it later, when asked to set one up.
1700          */
1701 }
1702
1703 static int cortex_m3_examine(struct target *target)
1704 {
1705         int retval;
1706         uint32_t cpuid, fpcr;
1707         int i;
1708         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1709         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1710
1711         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1712                 return retval;
1713
1714         if (!target_was_examined(target))
1715         {
1716                 target_set_examined(target);
1717
1718                 /* Read from Device Identification Registers */
1719                 retval = target_read_u32(target, CPUID, &cpuid);
1720                 if (retval != ERROR_OK)
1721                         return retval;
1722
1723                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1724                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1725                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1726                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1727
1728                 /* NOTE: FPB and DWT are both optional. */
1729
1730                 /* Setup FPB */
1731                 target_read_u32(target, FP_CTRL, &fpcr);
1732                 cortex_m3->auto_bp_type = 1;
1733                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1734                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1735                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1736                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1737                 cortex_m3->fpb_enabled = fpcr & 1;
1738                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1739                 {
1740                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1741                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1742                 }
1743                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1744
1745                 /* Setup DWT */
1746                 cortex_m3_dwt_setup(cortex_m3, target);
1747
1748                 /* These hardware breakpoints only work for code in flash! */
1749                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1750                                 target_name(target),
1751                                 cortex_m3->fp_num_code,
1752                                 cortex_m3->dwt_num_comp);
1753         }
1754
1755         return ERROR_OK;
1756 }
1757
1758 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1759 {
1760         uint16_t dcrdr;
1761
1762         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1763         *ctrl = (uint8_t)dcrdr;
1764         *value = (uint8_t)(dcrdr >> 8);
1765
1766         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1767
1768         /* write ack back to software dcc register
1769          * signify we have read data */
1770         if (dcrdr & (1 << 0))
1771         {
1772                 dcrdr = 0;
1773                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1774         }
1775
1776         return ERROR_OK;
1777 }
1778
1779 static int cortex_m3_target_request_data(struct target *target,
1780                 uint32_t size, uint8_t *buffer)
1781 {
1782         struct armv7m_common *armv7m = target_to_armv7m(target);
1783         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1784         uint8_t data;
1785         uint8_t ctrl;
1786         uint32_t i;
1787
1788         for (i = 0; i < (size * 4); i++)
1789         {
1790                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1791                 buffer[i] = data;
1792         }
1793
1794         return ERROR_OK;
1795 }
1796
1797 static int cortex_m3_handle_target_request(void *priv)
1798 {
1799         struct target *target = priv;
1800         if (!target_was_examined(target))
1801                 return ERROR_OK;
1802         struct armv7m_common *armv7m = target_to_armv7m(target);
1803         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1804
1805         if (!target->dbg_msg_enabled)
1806                 return ERROR_OK;
1807
1808         if (target->state == TARGET_RUNNING)
1809         {
1810                 uint8_t data;
1811                 uint8_t ctrl;
1812
1813                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1814
1815                 /* check if we have data */
1816                 if (ctrl & (1 << 0))
1817                 {
1818                         uint32_t request;
1819
1820                         /* we assume target is quick enough */
1821                         request = data;
1822                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1823                         request |= (data << 8);
1824                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1825                         request |= (data << 16);
1826                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1827                         request |= (data << 24);
1828                         target_request(target, request);
1829                 }
1830         }
1831
1832         return ERROR_OK;
1833 }
1834
1835 static int cortex_m3_init_arch_info(struct target *target,
1836                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1837 {
1838         int retval;
1839         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1840
1841         armv7m_init_arch_info(target, armv7m);
1842
1843         /* prepare JTAG information for the new target */
1844         cortex_m3->jtag_info.tap = tap;
1845         cortex_m3->jtag_info.scann_size = 4;
1846
1847         /* Leave (only) generic DAP stuff for debugport_init(); */
1848         armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1849         armv7m->swjdp_info.memaccess_tck = 8;
1850         /* Cortex-M3 has 4096 bytes autoincrement range */
1851         armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
1852
1853         /* register arch-specific functions */
1854         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1855
1856         armv7m->post_debug_entry = NULL;
1857
1858         armv7m->pre_restore_context = NULL;
1859         armv7m->post_restore_context = NULL;
1860
1861         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1862         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1863
1864         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1865
1866         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1867         {
1868                 return retval;
1869         }
1870
1871         return ERROR_OK;
1872 }
1873
1874 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1875 {
1876         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1877
1878         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1879         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1880
1881         return ERROR_OK;
1882 }
1883
1884 /*--------------------------------------------------------------------------*/
1885
1886 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1887                 struct cortex_m3_common *cm3)
1888 {
1889         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1890                 command_print(cmd_ctx, "target is not a Cortex-M3");
1891                 return ERROR_TARGET_INVALID;
1892         }
1893         return ERROR_OK;
1894 }
1895
1896 /*
1897  * Only stuff below this line should need to verify that its target
1898  * is a Cortex-M3.  Everything else should have indirected through the
1899  * cortexm3_target structure, which is only used with CM3 targets.
1900  */
1901
1902 /*
1903  * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1904  * as at least ARM-1156T2.  The interesting thing about Cortex-M is
1905  * that *only* Thumb2 disassembly matters.  There are also some small
1906  * additions to Thumb2 that are specific to ARMv7-M.
1907  */
1908 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1909 {
1910         int retval;
1911         struct target *target = get_current_target(CMD_CTX);
1912         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1913         uint32_t address;
1914         unsigned long count = 1;
1915         struct arm_instruction cur_instruction;
1916
1917         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1918         if (retval != ERROR_OK)
1919                 return retval;
1920
1921         errno = 0;
1922         switch (CMD_ARGC) {
1923         case 2:
1924                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1925                 /* FALL THROUGH */
1926         case 1:
1927                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1928                 break;
1929         default:
1930                 command_print(CMD_CTX,
1931                         "usage: cortex_m3 disassemble <address> [<count>]");
1932                 return ERROR_OK;
1933         }
1934
1935         while (count--) {
1936                 retval = thumb2_opcode(target, address, &cur_instruction);
1937                 if (retval != ERROR_OK)
1938                         return retval;
1939                 command_print(CMD_CTX, "%s", cur_instruction.text);
1940                 address += cur_instruction.instruction_size;
1941         }
1942
1943         return ERROR_OK;
1944 }
1945
1946 static const struct {
1947         char name[10];
1948         unsigned mask;
1949 } vec_ids[] = {
1950         { "hard_err",   VC_HARDERR, },
1951         { "int_err",    VC_INTERR, },
1952         { "bus_err",    VC_BUSERR, },
1953         { "state_err",  VC_STATERR, },
1954         { "chk_err",    VC_CHKERR, },
1955         { "nocp_err",   VC_NOCPERR, },
1956         { "mm_err",     VC_MMERR, },
1957         { "reset",      VC_CORERESET, },
1958 };
1959
1960 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1961 {
1962         struct target *target = get_current_target(CMD_CTX);
1963         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1964         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1965         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1966         uint32_t demcr = 0;
1967         int retval;
1968
1969         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1970         if (retval != ERROR_OK)
1971                 return retval;
1972
1973         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1974
1975         if (CMD_ARGC > 0) {
1976                 unsigned catch = 0;
1977
1978                 if (CMD_ARGC == 1) {
1979                         if (strcmp(CMD_ARGV[0], "all") == 0) {
1980                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1981                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
1982                                         | VC_MMERR | VC_CORERESET;
1983                                 goto write;
1984                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1985                                 goto write;
1986                         }
1987                 }
1988                 while (CMD_ARGC-- > 0) {
1989                         unsigned i;
1990                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1991                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1992                                         continue;
1993                                 catch |= vec_ids[i].mask;
1994                                 break;
1995                         }
1996                         if (i == ARRAY_SIZE(vec_ids)) {
1997                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1998                                 return ERROR_INVALID_ARGUMENTS;
1999                         }
2000                 }
2001 write:
2002                 /* For now, armv7m->demcr only stores vector catch flags. */
2003                 armv7m->demcr = catch;
2004
2005                 demcr &= ~0xffff;
2006                 demcr |= catch;
2007
2008                 /* write, but don't assume it stuck (why not??) */
2009                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2010                 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2011
2012                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2013                  * Otherwise the vector catch hardware could fire when there's
2014                  * no debugger hooked up, causing much confusion...
2015                  */
2016         }
2017
2018         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2019         {
2020                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2021                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2022         }
2023
2024         return ERROR_OK;
2025 }
2026
2027 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2028 {
2029         struct target *target = get_current_target(CMD_CTX);
2030         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2031         int retval;
2032
2033         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2034         if (retval != ERROR_OK)
2035                 return retval;
2036
2037         if (target->state != TARGET_HALTED)
2038         {
2039                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2040                 return ERROR_OK;
2041         }
2042
2043         if (CMD_ARGC > 0)
2044         {
2045                 bool enable;
2046                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2047                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2048                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2049                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2050         }
2051
2052         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2053                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2054
2055         return ERROR_OK;
2056 }
2057
2058 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2059         {
2060                 .name = "disassemble",
2061                 .handler = handle_cortex_m3_disassemble_command,
2062                 .mode = COMMAND_EXEC,
2063                 .help = "disassemble Thumb2 instructions",
2064                 .usage = "address [count]",
2065         },
2066         {
2067                 .name = "maskisr",
2068                 .handler = handle_cortex_m3_mask_interrupts_command,
2069                 .mode = COMMAND_EXEC,
2070                 .help = "mask cortex_m3 interrupts",
2071                 .usage = "['on'|'off']",
2072         },
2073         {
2074                 .name = "vector_catch",
2075                 .handler = handle_cortex_m3_vector_catch_command,
2076                 .mode = COMMAND_EXEC,
2077                 .help = "configure hardware vectors to trigger debug entry",
2078                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2079         },
2080         COMMAND_REGISTRATION_DONE
2081 };
2082 static const struct command_registration cortex_m3_command_handlers[] = {
2083         {
2084                 .chain = armv7m_command_handlers,
2085         },
2086         {
2087                 .name = "cortex_m3",
2088                 .mode = COMMAND_EXEC,
2089                 .help = "Cortex-M3 command group",
2090                 .chain = cortex_m3_exec_command_handlers,
2091         },
2092         COMMAND_REGISTRATION_DONE
2093 };
2094
2095 struct target_type cortexm3_target =
2096 {
2097         .name = "cortex_m3",
2098
2099         .poll = cortex_m3_poll,
2100         .arch_state = armv7m_arch_state,
2101
2102         .target_request_data = cortex_m3_target_request_data,
2103
2104         .halt = cortex_m3_halt,
2105         .resume = cortex_m3_resume,
2106         .step = cortex_m3_step,
2107
2108         .assert_reset = cortex_m3_assert_reset,
2109         .deassert_reset = cortex_m3_deassert_reset,
2110         .soft_reset_halt = cortex_m3_soft_reset_halt,
2111
2112         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2113
2114         .read_memory = cortex_m3_read_memory,
2115         .write_memory = cortex_m3_write_memory,
2116         .bulk_write_memory = cortex_m3_bulk_write_memory,
2117         .checksum_memory = armv7m_checksum_memory,
2118         .blank_check_memory = armv7m_blank_check_memory,
2119
2120         .run_algorithm = armv7m_run_algorithm,
2121
2122         .add_breakpoint = cortex_m3_add_breakpoint,
2123         .remove_breakpoint = cortex_m3_remove_breakpoint,
2124         .add_watchpoint = cortex_m3_add_watchpoint,
2125         .remove_watchpoint = cortex_m3_remove_watchpoint,
2126
2127         .commands = cortex_m3_command_handlers,
2128         .target_create = cortex_m3_target_create,
2129         .init_target = cortex_m3_init_target,
2130         .examine = cortex_m3_examine,
2131 };