git.sur5r.net Git - openocd/blob - src/target/cortex_m3.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FBP remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54
  55 /* forward declarations */
  56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58 static void cortex_m3_enable_watchpoints(struct target *target);
  59 static int cortex_m3_store_core_reg_u32(struct target *target,
  60                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  61
  62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  63                 uint32_t *value, int regnum)
  64 {
  65         int retval;
  66         uint32_t dcrdr;
  67
  68         /* because the DCB_DCRDR is used for the emulated dcc channel
  69          * we have to save/restore the DCB_DCRDR when used */
  70
  71         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  72
  73         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  74         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  75         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  76         if (retval != ERROR_OK)
  77                 return retval;
  78
  79         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  80         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  81         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  82         if (retval != ERROR_OK)
  83                 return retval;
  84
  85         retval = dap_run(swjdp);
  86         if (retval != ERROR_OK)
  87                 return retval;
  88
  89         /* restore DCB_DCRDR - this needs to be in a seperate
  90          * transaction otherwise the emulated DCC channel breaks */
  91         if (retval == ERROR_OK)
  92                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  93
  94         return retval;
  95 }
  96
  97 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
  98                 uint32_t value, int regnum)
  99 {
 100         int retval;
 101         uint32_t dcrdr;
 102
 103         /* because the DCB_DCRDR is used for the emulated dcc channel
 104          * we have to save/restore the DCB_DCRDR when used */
 105
 106         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 107
 108         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 109         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 110         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 111         // XXX check retval
 112
 113         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 114         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 115         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 116         // XXX check retval
 117
 118         retval = dap_run(swjdp);
 119
 120         /* restore DCB_DCRDR - this needs to be in a seperate
 121          * transaction otherwise the emulated DCC channel breaks */
 122         if (retval == ERROR_OK)
 123                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 124
 125         return retval;
 126 }
 127
 128 static int cortex_m3_write_debug_halt_mask(struct target *target,
 129                 uint32_t mask_on, uint32_t mask_off)
 130 {
 131         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 132         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 133
 134         /* mask off status bits */
 135         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 136         /* create new register mask */
 137         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 138
 139         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 140 }
 141
 142 static int cortex_m3_clear_halt(struct target *target)
 143 {
 144         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 145         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 146
 147         /* clear step if any */
 148         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 149
 150         /* Read Debug Fault Status Register */
 151         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 152
 153         /* Clear Debug Fault Status */
 154         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 155         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 156
 157         return ERROR_OK;
 158 }
 159
 160 static int cortex_m3_single_step_core(struct target *target)
 161 {
 162         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 163         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 164         uint32_t dhcsr_save;
 165
 166         /* backup dhcsr reg */
 167         dhcsr_save = cortex_m3->dcb_dhcsr;
 168
 169         /* Mask interrupts before clearing halt, if done already.  This avoids
 170          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 171          * HALT can put the core into an unknown state.
 172          */
 173         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 174                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 175                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 176         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 177                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 178         LOG_DEBUG(" ");
 179
 180         /* restore dhcsr reg */
 181         cortex_m3->dcb_dhcsr = dhcsr_save;
 182         cortex_m3_clear_halt(target);
 183
 184         return ERROR_OK;
 185 }
 186
 187 static int cortex_m3_endreset_event(struct target *target)
 188 {
 189         int i;
 190         int retval;
 191         uint32_t dcb_demcr;
 192         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 193         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 194         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 195         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 196         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 197
 198         /* REVISIT The four debug monitor bits are currently ignored... */
 199         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 200         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 201
 202         /* this register is used for emulated dcc channel */
 203         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 204
 205         /* Enable debug requests */
 206         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 207         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 208                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 209
 210         /* clear any interrupt masking */
 211         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 212
 213         /* Enable features controlled by ITM and DWT blocks, and catch only
 214          * the vectors we were told to pay attention to.
 215          *
 216          * Target firmware is responsible for all fault handling policy
 217          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 218          * or manual updates to the NVIC SHCSR and CCR registers.
 219          */
 220         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 221
 222         /* Paranoia: evidently some (early?) chips don't preserve all the
 223          * debug state (including FBP, DWT, etc) across reset...
 224          */
 225
 226         /* Enable FPB */
 227         target_write_u32(target, FP_CTRL, 3);
 228         cortex_m3->fpb_enabled = 1;
 229
 230         /* Restore FPB registers */
 231         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 232         {
 233                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 234         }
 235
 236         /* Restore DWT registers */
 237         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 238         {
 239                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 240                                 dwt_list[i].comp);
 241                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 242                                 dwt_list[i].mask);
 243                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 244                                 dwt_list[i].function);
 245         }
 246         retval = dap_run(swjdp);
 247         if (retval != ERROR_OK)
 248                 return retval;
 249
 250         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 251
 252         /* make sure we have latest dhcsr flags */
 253         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 254
 255         return retval;
 256 }
 257
 258 static int cortex_m3_examine_debug_reason(struct target *target)
 259 {
 260         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 261
 262         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 263         /* only check the debug reason if we don't know it already */
 264
 265         if ((target->debug_reason != DBG_REASON_DBGRQ)
 266                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 267         {
 268                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 269                 {
 270                         target->debug_reason = DBG_REASON_BREAKPOINT;
 271                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 272                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 273                 }
 274                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 275                         target->debug_reason = DBG_REASON_WATCHPOINT;
 276                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 277                         target->debug_reason = DBG_REASON_BREAKPOINT;
 278                 else /* EXTERNAL, HALTED */
 279                         target->debug_reason = DBG_REASON_UNDEFINED;
 280         }
 281
 282         return ERROR_OK;
 283 }
 284
 285 static int cortex_m3_examine_exception_reason(struct target *target)
 286 {
 287         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 288         struct armv7m_common *armv7m = target_to_armv7m(target);
 289         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
 290         int retval;
 291
 292         mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 293         switch (armv7m->exception_number)
 294         {
 295                 case 2: /* NMI */
 296                         break;
 297                 case 3: /* Hard Fault */
 298                         mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 299                         if (except_sr & 0x40000000)
 300                         {
 301                                 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 302                         }
 303                         break;
 304                 case 4: /* Memory Management */
 305                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 306                         mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 307                         break;
 308                 case 5: /* Bus Fault */
 309                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 310                         mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 311                         break;
 312                 case 6: /* Usage Fault */
 313                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 314                         break;
 315                 case 11:        /* SVCall */
 316                         break;
 317                 case 12:        /* Debug Monitor */
 318                         mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 319                         break;
 320                 case 14:        /* PendSV */
 321                         break;
 322                 case 15:        /* SysTick */
 323                         break;
 324                 default:
 325                         except_sr = 0;
 326                         break;
 327         }
 328         retval = dap_run(swjdp);
 329         if (retval == ERROR_OK)
 330                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 331                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 332                         armv7m_exception_string(armv7m->exception_number),
 333                         shcsr, except_sr, cfsr, except_ar);
 334         return retval;
 335 }
 336
 337 /* PSP is used in some thread modes */
 338 static const int armv7m_psp_reg_map[17] = {
 339         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 340         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 341         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 342         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 343         ARMV7M_xPSR,
 344 };
 345
 346 /* MSP is used in handler and some thread modes */
 347 static const int armv7m_msp_reg_map[17] = {
 348         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 349         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 350         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 351         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 352         ARMV7M_xPSR,
 353 };
 354
 355 static int cortex_m3_debug_entry(struct target *target)
 356 {
 357         int i;
 358         uint32_t xPSR;
 359         int retval;
 360         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 361         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 362         struct arm *arm = &armv7m->arm;
 363         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
 364         struct reg *r;
 365
 366         LOG_DEBUG(" ");
 367
 368         cortex_m3_clear_halt(target);
 369         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 370
 371         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 372                 return retval;
 373
 374         /* Examine target state and mode */
 375         /* First load register acessible through core debug port*/
 376         int num_regs = armv7m->core_cache->num_regs;
 377
 378         for (i = 0; i < num_regs; i++)
 379         {
 380                 if (!armv7m->core_cache->reg_list[i].valid)
 381                         armv7m->read_core_reg(target, i);
 382         }
 383
 384         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 385         xPSR = buf_get_u32(r->value, 0, 32);
 386
 387 #ifdef ARMV7_GDB_HACKS
 388         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 389          * Instead, each CM3 should have its own dummy value...
 390          */
 391         /* copy real xpsr reg for gdb, setting thumb bit */
 392         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 393         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 394         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 395         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 396 #endif
 397
 398         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 399         if (xPSR & 0xf00)
 400         {
 401                 r->dirty = r->valid;
 402                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 403         }
 404
 405         /* Are we in an exception handler */
 406         if (xPSR & 0x1FF)
 407         {
 408                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 409                 armv7m->exception_number = (xPSR & 0x1FF);
 410
 411                 arm->core_mode = ARM_MODE_HANDLER;
 412                 arm->map = armv7m_msp_reg_map;
 413         }
 414         else
 415         {
 416                 unsigned control = buf_get_u32(armv7m->core_cache
 417                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 418
 419                 /* is this thread privileged? */
 420                 armv7m->core_mode = control & 1;
 421                 arm->core_mode = armv7m->core_mode
 422                                 ? ARM_MODE_USER_THREAD
 423                                 : ARM_MODE_THREAD;
 424
 425                 /* which stack is it using? */
 426                 if (control & 2)
 427                         arm->map = armv7m_psp_reg_map;
 428                 else
 429                         arm->map = armv7m_msp_reg_map;
 430
 431                 armv7m->exception_number = 0;
 432         }
 433
 434         if (armv7m->exception_number)
 435         {
 436                 cortex_m3_examine_exception_reason(target);
 437         }
 438
 439         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 440                 armv7m_mode_strings[armv7m->core_mode],
 441                 *(uint32_t*)(arm->pc->value),
 442                 target_state_name(target));
 443
 444         if (armv7m->post_debug_entry)
 445                 armv7m->post_debug_entry(target);
 446
 447         return ERROR_OK;
 448 }
 449
 450 static int cortex_m3_poll(struct target *target)
 451 {
 452         int retval;
 453         enum target_state prev_target_state = target->state;
 454         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 455         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 456
 457         /* Read from Debug Halting Control and Status Register */
 458         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 459         if (retval != ERROR_OK)
 460         {
 461                 target->state = TARGET_UNKNOWN;
 462                 return retval;
 463         }
 464
 465         /* Recover from lockup.  See ARMv7-M architecture spec,
 466          * section B1.5.15 "Unrecoverable exception cases".
 467          *
 468          * REVISIT Is there a better way to report and handle this?
 469          */
 470         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 471                 LOG_WARNING("%s -- clearing lockup after double fault",
 472                                 target_name(target));
 473                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 474                 target->debug_reason = DBG_REASON_DBGRQ;
 475
 476                 /* refresh status bits */
 477                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 478         }
 479
 480         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 481         {
 482                 /* check if still in reset */
 483                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 484
 485                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 486                 {
 487                         target->state = TARGET_RESET;
 488                         return ERROR_OK;
 489                 }
 490         }
 491
 492         if (target->state == TARGET_RESET)
 493         {
 494                 /* Cannot switch context while running so endreset is
 495                  * called with target->state == TARGET_RESET
 496                  */
 497                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 498                                 cortex_m3->dcb_dhcsr);
 499                 cortex_m3_endreset_event(target);
 500                 target->state = TARGET_RUNNING;
 501                 prev_target_state = TARGET_RUNNING;
 502         }
 503
 504         if (cortex_m3->dcb_dhcsr & S_HALT)
 505         {
 506                 target->state = TARGET_HALTED;
 507
 508                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 509                 {
 510                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 511                                 return retval;
 512
 513                         if (arm_semihosting(target, &retval) != 0)
 514                                 return retval;
 515
 516                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 517                 }
 518                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 519                 {
 520                         LOG_DEBUG(" ");
 521                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 522                                 return retval;
 523
 524                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 525                 }
 526         }
 527
 528         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 529          * How best to model low power modes?
 530          */
 531
 532         if (target->state == TARGET_UNKNOWN)
 533         {
 534                 /* check if processor is retiring instructions */
 535                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 536                 {
 537                         target->state = TARGET_RUNNING;
 538                         return ERROR_OK;
 539                 }
 540         }
 541
 542         return ERROR_OK;
 543 }
 544
 545 static int cortex_m3_halt(struct target *target)
 546 {
 547         LOG_DEBUG("target->state: %s",
 548                 target_state_name(target));
 549
 550         if (target->state == TARGET_HALTED)
 551         {
 552                 LOG_DEBUG("target was already halted");
 553                 return ERROR_OK;
 554         }
 555
 556         if (target->state == TARGET_UNKNOWN)
 557         {
 558                 LOG_WARNING("target was in unknown state when halt was requested");
 559         }
 560
 561         if (target->state == TARGET_RESET)
 562         {
 563                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 564                 {
 565                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 566                         return ERROR_TARGET_FAILURE;
 567                 }
 568                 else
 569                 {
 570                         /* we came here in a reset_halt or reset_init sequence
 571                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 572                          */
 573                         target->debug_reason = DBG_REASON_DBGRQ;
 574
 575                         return ERROR_OK;
 576                 }
 577         }
 578
 579         /* Write to Debug Halting Control and Status Register */
 580         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 581
 582         target->debug_reason = DBG_REASON_DBGRQ;
 583
 584         return ERROR_OK;
 585 }
 586
 587 static int cortex_m3_soft_reset_halt(struct target *target)
 588 {
 589         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 590         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 591         uint32_t dcb_dhcsr = 0;
 592         int retval, timeout = 0;
 593
 594         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 595         mem_ap_write_u32(swjdp, DCB_DEMCR,
 596                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 597
 598         /* Request a core-only reset */
 599         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 600                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 601         target->state = TARGET_RESET;
 602
 603         /* registers are now invalid */
 604         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 605
 606         while (timeout < 100)
 607         {
 608                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 609                 if (retval == ERROR_OK)
 610                 {
 611                         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 612                                         &cortex_m3->nvic_dfsr);
 613                         if ((dcb_dhcsr & S_HALT)
 614                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 615                         {
 616                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 617                                         "DFSR 0x%08x",
 618                                         (unsigned) dcb_dhcsr,
 619                                         (unsigned) cortex_m3->nvic_dfsr);
 620                                 cortex_m3_poll(target);
 621                                 /* FIXME restore user's vector catch config */
 622                                 return ERROR_OK;
 623                         }
 624                         else
 625                                 LOG_DEBUG("waiting for system reset-halt, "
 626                                         "DHCSR 0x%08x, %d ms",
 627                                         (unsigned) dcb_dhcsr, timeout);
 628                 }
 629                 timeout++;
 630                 alive_sleep(1);
 631         }
 632
 633         return ERROR_OK;
 634 }
 635
 636 static void cortex_m3_enable_breakpoints(struct target *target)
 637 {
 638         struct breakpoint *breakpoint = target->breakpoints;
 639
 640         /* set any pending breakpoints */
 641         while (breakpoint)
 642         {
 643                 if (!breakpoint->set)
 644                         cortex_m3_set_breakpoint(target, breakpoint);
 645                 breakpoint = breakpoint->next;
 646         }
 647 }
 648
 649 static int cortex_m3_resume(struct target *target, int current,
 650                 uint32_t address, int handle_breakpoints, int debug_execution)
 651 {
 652         struct armv7m_common *armv7m = target_to_armv7m(target);
 653         struct breakpoint *breakpoint = NULL;
 654         uint32_t resume_pc;
 655         struct reg *r;
 656
 657         if (target->state != TARGET_HALTED)
 658         {
 659                 LOG_WARNING("target not halted");
 660                 return ERROR_TARGET_NOT_HALTED;
 661         }
 662
 663         if (!debug_execution)
 664         {
 665                 target_free_all_working_areas(target);
 666                 cortex_m3_enable_breakpoints(target);
 667                 cortex_m3_enable_watchpoints(target);
 668         }
 669
 670         if (debug_execution)
 671         {
 672                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 673
 674                 /* Disable interrupts */
 675                 /* We disable interrupts in the PRIMASK register instead of
 676                  * masking with C_MASKINTS.  This is probably the same issue
 677                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 678                  * in parallel with disabled interrupts can cause local faults
 679                  * to not be taken.
 680                  *
 681                  * REVISIT this clearly breaks non-debug execution, since the
 682                  * PRIMASK register state isn't saved/restored...  workaround
 683                  * by never resuming app code after debug execution.
 684                  */
 685                 buf_set_u32(r->value, 0, 1, 1);
 686                 r->dirty = true;
 687                 r->valid = true;
 688
 689                 /* Make sure we are in Thumb mode */
 690                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 691                 buf_set_u32(r->value, 24, 1, 1);
 692                 r->dirty = true;
 693                 r->valid = true;
 694         }
 695
 696         /* current = 1: continue on current pc, otherwise continue at <address> */
 697         r = armv7m->arm.pc;
 698         if (!current)
 699         {
 700                 buf_set_u32(r->value, 0, 32, address);
 701                 r->dirty = true;
 702                 r->valid = true;
 703         }
 704
 705         /* if we halted last time due to a bkpt instruction
 706          * then we have to manually step over it, otherwise
 707          * the core will break again */
 708
 709         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 710                         && !debug_execution)
 711         {
 712                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 713         }
 714
 715         resume_pc = buf_get_u32(r->value, 0, 32);
 716
 717         armv7m_restore_context(target);
 718
 719         /* the front-end may request us not to handle breakpoints */
 720         if (handle_breakpoints)
 721         {
 722                 /* Single step past breakpoint at current address */
 723                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 724                 {
 725                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 726                                           breakpoint->address,
 727                                           breakpoint->unique_id);
 728                         cortex_m3_unset_breakpoint(target, breakpoint);
 729                         cortex_m3_single_step_core(target);
 730                         cortex_m3_set_breakpoint(target, breakpoint);
 731                 }
 732         }
 733
 734         /* Restart core */
 735         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 736
 737         target->debug_reason = DBG_REASON_NOTHALTED;
 738
 739         /* registers are now invalid */
 740         register_cache_invalidate(armv7m->core_cache);
 741
 742         if (!debug_execution)
 743         {
 744                 target->state = TARGET_RUNNING;
 745                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 746                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 747         }
 748         else
 749         {
 750                 target->state = TARGET_DEBUG_RUNNING;
 751                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 752                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 753         }
 754
 755         return ERROR_OK;
 756 }
 757
 758 /* int irqstepcount = 0; */
 759 static int cortex_m3_step(struct target *target, int current,
 760                 uint32_t address, int handle_breakpoints)
 761 {
 762         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 763         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 764         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
 765         struct breakpoint *breakpoint = NULL;
 766         struct reg *pc = armv7m->arm.pc;
 767         bool bkpt_inst_found = false;
 768
 769         if (target->state != TARGET_HALTED)
 770         {
 771                 LOG_WARNING("target not halted");
 772                 return ERROR_TARGET_NOT_HALTED;
 773         }
 774
 775         /* current = 1: continue on current pc, otherwise continue at <address> */
 776         if (!current)
 777                 buf_set_u32(pc->value, 0, 32, address);
 778
 779         /* the front-end may request us not to handle breakpoints */
 780         if (handle_breakpoints) {
 781                 breakpoint = breakpoint_find(target,
 782                                 buf_get_u32(pc->value, 0, 32));
 783                 if (breakpoint)
 784                         cortex_m3_unset_breakpoint(target, breakpoint);
 785         }
 786
 787         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 788
 789         target->debug_reason = DBG_REASON_SINGLESTEP;
 790
 791         armv7m_restore_context(target);
 792
 793         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 794
 795         /* if no bkpt instruction is found at pc then we can perform
 796          * a normal step, otherwise we have to manually step over the bkpt
 797          * instruction - as such simulate a step */
 798         if (bkpt_inst_found == false)
 799         {
 800                 /* set step and clear halt */
 801                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 802         }
 803
 804         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 805
 806         /* registers are now invalid */
 807         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 808
 809         if (breakpoint)
 810                 cortex_m3_set_breakpoint(target, breakpoint);
 811
 812         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 813                         " nvic_icsr = 0x%" PRIx32,
 814                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 815
 816         cortex_m3_debug_entry(target);
 817         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 818
 819         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 820                         " nvic_icsr = 0x%" PRIx32,
 821                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 822
 823         return ERROR_OK;
 824 }
 825
 826 static int cortex_m3_assert_reset(struct target *target)
 827 {
 828         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 829         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
 830         int assert_srst = 1;
 831
 832         LOG_DEBUG("target->state: %s",
 833                 target_state_name(target));
 834
 835         enum reset_types jtag_reset_config = jtag_get_reset_config();
 836
 837         /*
 838          * We can reset Cortex-M3 targets using just the NVIC without
 839          * requiring SRST, getting a SoC reset (or a core-only reset)
 840          * instead of a system reset.
 841          */
 842         if (!(jtag_reset_config & RESET_HAS_SRST))
 843                 assert_srst = 0;
 844
 845         /* Enable debug requests */
 846         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 847         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 848                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 849
 850         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 851
 852         if (!target->reset_halt)
 853         {
 854                 /* Set/Clear C_MASKINTS in a separate operation */
 855                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 856                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 857                                         DBGKEY | C_DEBUGEN | C_HALT);
 858
 859                 /* clear any debug flags before resuming */
 860                 cortex_m3_clear_halt(target);
 861
 862                 /* clear C_HALT in dhcsr reg */
 863                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 864         }
 865         else
 866         {
 867                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 868                  *
 869                  * REVISIT catching BUSERR presumably helps to defend against
 870                  * bad vector table entries.  Should this include MMERR or
 871                  * other flags too?
 872                  */
 873                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 874                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 875         }
 876
 877         /*
 878          * When nRST is asserted on most Stellaris devices, it clears some of
 879          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 880          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 881          * chips.  (Only power-on reset should affect debug state, beyond a
 882          * few specified bits; not the chip's nRST input, wired to SRST.)
 883          *
 884          * REVISIT current errata specs don't seem to cover this issue.
 885          * Do we have more details than this email?
 886          *   https://lists.berlios.de/pipermail
 887          *      /openocd-development/2008-August/003065.html
 888          */
 889         if (strcmp(target->variant, "lm3s") == 0)
 890         {
 891                 /* Check for silicon revisions with the issue. */
 892                 uint32_t did0;
 893
 894                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 895                 {
 896                         switch ((did0 >> 16) & 0xff)
 897                         {
 898                                 case 0:
 899                                         /* all Sandstorm suffer issue */
 900                                         assert_srst = 0;
 901                                         break;
 902
 903                                 case 1:
 904                                 case 3:
 905                                         /* Fury and DustDevil rev A have
 906                                          * this nRST problem.  It should
 907                                          * be fixed in rev B silicon.
 908                                          */
 909                                         if (((did0 >> 8) & 0xff) == 0)
 910                                                 assert_srst = 0;
 911                                         break;
 912                                 case 4:
 913                                         /* Tempest should be fine. */
 914                                         break;
 915                         }
 916                 }
 917         }
 918
 919         if (assert_srst)
 920         {
 921                 /* default to asserting srst */
 922                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 923                 {
 924                         jtag_add_reset(1, 1);
 925                 }
 926                 else
 927                 {
 928                         jtag_add_reset(0, 1);
 929                 }
 930         }
 931         else
 932         {
 933                 /* Use a standard Cortex-M3 software reset mechanism.
 934                  * SYSRESETREQ will reset SoC peripherals outside the
 935                  * core, like watchdog timers, if the SoC wires it up
 936                  * correctly.  Else VECRESET can reset just the core.
 937                  */
 938                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 939                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 940                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 941
 942                 {
 943                         /* I do not know why this is necessary, but it
 944                          * fixes strange effects (step/resume cause NMI
 945                          * after reset) on LM3S6918 -- Michael Schwingen
 946                          */
 947                         uint32_t tmp;
 948                         mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 949                 }
 950         }
 951
 952         target->state = TARGET_RESET;
 953         jtag_add_sleep(50000);
 954
 955         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 956
 957         if (target->reset_halt)
 958         {
 959                 int retval;
 960                 if ((retval = target_halt(target)) != ERROR_OK)
 961                         return retval;
 962         }
 963
 964         return ERROR_OK;
 965 }
 966
 967 static int cortex_m3_deassert_reset(struct target *target)
 968 {
 969         LOG_DEBUG("target->state: %s",
 970                 target_state_name(target));
 971
 972         /* deassert reset lines */
 973         jtag_add_reset(0, 0);
 974
 975         return ERROR_OK;
 976 }
 977
 978 static int
 979 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 980 {
 981         int retval;
 982         int fp_num = 0;
 983         uint32_t hilo;
 984         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 985         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
 986
 987         if (breakpoint->set)
 988         {
 989                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
 990                 return ERROR_OK;
 991         }
 992
 993         if (cortex_m3->auto_bp_type)
 994         {
 995                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 996         }
 997
 998         if (breakpoint->type == BKPT_HARD)
 999         {
1000                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1001                         fp_num++;
1002                 if (fp_num >= cortex_m3->fp_num_code)
1003                 {
1004                         LOG_ERROR("Can not find free FPB Comparator!");
1005                         return ERROR_FAIL;
1006                 }
1007                 breakpoint->set = fp_num + 1;
1008                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1009                 comparator_list[fp_num].used = 1;
1010                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1011                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1012                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1013                 if (!cortex_m3->fpb_enabled)
1014                 {
1015                         LOG_DEBUG("FPB wasn't enabled, do it now");
1016                         target_write_u32(target, FP_CTRL, 3);
1017                 }
1018         }
1019         else if (breakpoint->type == BKPT_SOFT)
1020         {
1021                 uint8_t code[4];
1022
1023                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1024                  * semihosting; don't use that.  Otherwise the BKPT
1025                  * parameter is arbitrary.
1026                  */
1027                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1028                 retval = target_read_memory(target,
1029                                 breakpoint->address & 0xFFFFFFFE,
1030                                 breakpoint->length, 1,
1031                                 breakpoint->orig_instr);
1032                 if (retval != ERROR_OK)
1033                         return retval;
1034                 retval = target_write_memory(target,
1035                                 breakpoint->address & 0xFFFFFFFE,
1036                                 breakpoint->length, 1,
1037                                 code);
1038                 if (retval != ERROR_OK)
1039                         return retval;
1040                 breakpoint->set = true;
1041         }
1042
1043         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1044                           breakpoint->unique_id,
1045                           (int)(breakpoint->type),
1046                           breakpoint->address,
1047                           breakpoint->length,
1048                           breakpoint->set);
1049
1050         return ERROR_OK;
1051 }
1052
1053 static int
1054 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1055 {
1056         int retval;
1057         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1058         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1059
1060         if (!breakpoint->set)
1061         {
1062                 LOG_WARNING("breakpoint not set");
1063                 return ERROR_OK;
1064         }
1065
1066         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1067                           breakpoint->unique_id,
1068                           (int)(breakpoint->type),
1069                           breakpoint->address,
1070                           breakpoint->length,
1071                           breakpoint->set);
1072
1073         if (breakpoint->type == BKPT_HARD)
1074         {
1075                 int fp_num = breakpoint->set - 1;
1076                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1077                 {
1078                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1079                         return ERROR_OK;
1080                 }
1081                 comparator_list[fp_num].used = 0;
1082                 comparator_list[fp_num].fpcr_value = 0;
1083                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1084         }
1085         else
1086         {
1087                 /* restore original instruction (kept in target endianness) */
1088                 if (breakpoint->length == 4)
1089                 {
1090                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1091                         {
1092                                 return retval;
1093                         }
1094                 }
1095                 else
1096                 {
1097                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1098                         {
1099                                 return retval;
1100                         }
1101                 }
1102         }
1103         breakpoint->set = false;
1104
1105         return ERROR_OK;
1106 }
1107
1108 static int
1109 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1110 {
1111         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1112
1113         if (cortex_m3->auto_bp_type)
1114         {
1115                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1116 #ifdef ARMV7_GDB_HACKS
1117                 if (breakpoint->length != 2) {
1118                         /* XXX Hack: Replace all breakpoints with length != 2 with
1119                          * a hardware breakpoint. */
1120                         breakpoint->type = BKPT_HARD;
1121                         breakpoint->length = 2;
1122                 }
1123 #endif
1124         }
1125
1126         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1127         {
1128                 LOG_INFO("flash patch comparator requested outside code memory region");
1129                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1130         }
1131
1132         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1133         {
1134                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1135                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1136         }
1137
1138         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1139         {
1140                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1141                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1142         }
1143
1144         if ((breakpoint->length != 2))
1145         {
1146                 LOG_INFO("only breakpoints of two bytes length supported");
1147                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1148         }
1149
1150         if (breakpoint->type == BKPT_HARD)
1151                 cortex_m3->fp_code_available--;
1152         cortex_m3_set_breakpoint(target, breakpoint);
1153
1154         return ERROR_OK;
1155 }
1156
1157 static int
1158 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1159 {
1160         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1161
1162         /* REVISIT why check? FBP can be updated with core running ... */
1163         if (target->state != TARGET_HALTED)
1164         {
1165                 LOG_WARNING("target not halted");
1166                 return ERROR_TARGET_NOT_HALTED;
1167         }
1168
1169         if (cortex_m3->auto_bp_type)
1170         {
1171                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1172         }
1173
1174         if (breakpoint->set)
1175         {
1176                 cortex_m3_unset_breakpoint(target, breakpoint);
1177         }
1178
1179         if (breakpoint->type == BKPT_HARD)
1180                 cortex_m3->fp_code_available++;
1181
1182         return ERROR_OK;
1183 }
1184
1185 static int
1186 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1187 {
1188         int dwt_num = 0;
1189         uint32_t mask, temp;
1190         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1191
1192         /* watchpoint params were validated earlier */
1193         mask = 0;
1194         temp = watchpoint->length;
1195         while (temp) {
1196                 temp >>= 1;
1197                 mask++;
1198         }
1199         mask--;
1200
1201         /* REVISIT Don't fully trust these "not used" records ... users
1202          * may set up breakpoints by hand, e.g. dual-address data value
1203          * watchpoint using comparator #1; comparator #0 matching cycle
1204          * count; send data trace info through ITM and TPIU; etc
1205          */
1206         struct cortex_m3_dwt_comparator *comparator;
1207
1208         for (comparator = cortex_m3->dwt_comparator_list;
1209                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1210                         comparator++, dwt_num++)
1211                 continue;
1212         if (dwt_num >= cortex_m3->dwt_num_comp)
1213         {
1214                 LOG_ERROR("Can not find free DWT Comparator");
1215                 return ERROR_FAIL;
1216         }
1217         comparator->used = 1;
1218         watchpoint->set = dwt_num + 1;
1219
1220         comparator->comp = watchpoint->address;
1221         target_write_u32(target, comparator->dwt_comparator_address + 0,
1222                         comparator->comp);
1223
1224         comparator->mask = mask;
1225         target_write_u32(target, comparator->dwt_comparator_address + 4,
1226                         comparator->mask);
1227
1228         switch (watchpoint->rw) {
1229         case WPT_READ:
1230                 comparator->function = 5;
1231                 break;
1232         case WPT_WRITE:
1233                 comparator->function = 6;
1234                 break;
1235         case WPT_ACCESS:
1236                 comparator->function = 7;
1237                 break;
1238         }
1239         target_write_u32(target, comparator->dwt_comparator_address + 8,
1240                         comparator->function);
1241
1242         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1243                         watchpoint->unique_id, dwt_num,
1244                         (unsigned) comparator->comp,
1245                         (unsigned) comparator->mask,
1246                         (unsigned) comparator->function);
1247         return ERROR_OK;
1248 }
1249
1250 static int
1251 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1252 {
1253         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1254         struct cortex_m3_dwt_comparator *comparator;
1255         int dwt_num;
1256
1257         if (!watchpoint->set)
1258         {
1259                 LOG_WARNING("watchpoint (wpid: %d) not set",
1260                                 watchpoint->unique_id);
1261                 return ERROR_OK;
1262         }
1263
1264         dwt_num = watchpoint->set - 1;
1265
1266         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1267                         watchpoint->unique_id, dwt_num,
1268                         (unsigned) watchpoint->address);
1269
1270         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1271         {
1272                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1273                 return ERROR_OK;
1274         }
1275
1276         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1277         comparator->used = 0;
1278         comparator->function = 0;
1279         target_write_u32(target, comparator->dwt_comparator_address + 8,
1280                         comparator->function);
1281
1282         watchpoint->set = false;
1283
1284         return ERROR_OK;
1285 }
1286
1287 static int
1288 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1289 {
1290         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1291
1292         if (cortex_m3->dwt_comp_available < 1)
1293         {
1294                 LOG_DEBUG("no comparators?");
1295                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1296         }
1297
1298         /* hardware doesn't support data value masking */
1299         if (watchpoint->mask != ~(uint32_t)0) {
1300                 LOG_DEBUG("watchpoint value masks not supported");
1301                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1302         }
1303
1304         /* hardware allows address masks of up to 32K */
1305         unsigned mask;
1306
1307         for (mask = 0; mask < 16; mask++) {
1308                 if ((1u << mask) == watchpoint->length)
1309                         break;
1310         }
1311         if (mask == 16) {
1312                 LOG_DEBUG("unsupported watchpoint length");
1313                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1314         }
1315         if (watchpoint->address & ((1 << mask) - 1)) {
1316                 LOG_DEBUG("watchpoint address is unaligned");
1317                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1318         }
1319
1320         /* Caller doesn't seem to be able to describe watching for data
1321          * values of zero; that flags "no value".
1322          *
1323          * REVISIT This DWT may well be able to watch for specific data
1324          * values.  Requires comparator #1 to set DATAVMATCH and match
1325          * the data, and another comparator (DATAVADDR0) matching addr.
1326          */
1327         if (watchpoint->value) {
1328                 LOG_DEBUG("data value watchpoint not YET supported");
1329                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1330         }
1331
1332         cortex_m3->dwt_comp_available--;
1333         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1334
1335         return ERROR_OK;
1336 }
1337
1338 static int
1339 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1340 {
1341         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1342
1343         /* REVISIT why check? DWT can be updated with core running ... */
1344         if (target->state != TARGET_HALTED)
1345         {
1346                 LOG_WARNING("target not halted");
1347                 return ERROR_TARGET_NOT_HALTED;
1348         }
1349
1350         if (watchpoint->set)
1351         {
1352                 cortex_m3_unset_watchpoint(target, watchpoint);
1353         }
1354
1355         cortex_m3->dwt_comp_available++;
1356         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1357
1358         return ERROR_OK;
1359 }
1360
1361 static void cortex_m3_enable_watchpoints(struct target *target)
1362 {
1363         struct watchpoint *watchpoint = target->watchpoints;
1364
1365         /* set any pending watchpoints */
1366         while (watchpoint)
1367         {
1368                 if (!watchpoint->set)
1369                         cortex_m3_set_watchpoint(target, watchpoint);
1370                 watchpoint = watchpoint->next;
1371         }
1372 }
1373
1374 static int cortex_m3_load_core_reg_u32(struct target *target,
1375                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1376 {
1377         int retval;
1378         struct armv7m_common *armv7m = target_to_armv7m(target);
1379         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1380
1381         /* NOTE:  we "know" here that the register identifiers used
1382          * in the v7m header match the Cortex-M3 Debug Core Register
1383          * Selector values for R0..R15, xPSR, MSP, and PSP.
1384          */
1385         switch (num) {
1386         case 0 ... 18:
1387                 /* read a normal core register */
1388                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1389
1390                 if (retval != ERROR_OK)
1391                 {
1392                         LOG_ERROR("JTAG failure %i",retval);
1393                         return ERROR_JTAG_DEVICE_ERROR;
1394                 }
1395                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1396                 break;
1397
1398         case ARMV7M_PRIMASK:
1399         case ARMV7M_BASEPRI:
1400         case ARMV7M_FAULTMASK:
1401         case ARMV7M_CONTROL:
1402                 /* Cortex-M3 packages these four registers as bitfields
1403                  * in one Debug Core register.  So say r0 and r2 docs;
1404                  * it was removed from r1 docs, but still works.
1405                  */
1406                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1407
1408                 switch (num)
1409                 {
1410                         case ARMV7M_PRIMASK:
1411                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1412                                 break;
1413
1414                         case ARMV7M_BASEPRI:
1415                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1416                                 break;
1417
1418                         case ARMV7M_FAULTMASK:
1419                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1420                                 break;
1421
1422                         case ARMV7M_CONTROL:
1423                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1424                                 break;
1425                 }
1426
1427                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1428                 break;
1429
1430         default:
1431                 return ERROR_INVALID_ARGUMENTS;
1432         }
1433
1434         return ERROR_OK;
1435 }
1436
1437 static int cortex_m3_store_core_reg_u32(struct target *target,
1438                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1439 {
1440         int retval;
1441         uint32_t reg;
1442         struct armv7m_common *armv7m = target_to_armv7m(target);
1443         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1444
1445 #ifdef ARMV7_GDB_HACKS
1446         /* If the LR register is being modified, make sure it will put us
1447          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1448          * hack to deal with the fact that gdb will sometimes "forge"
1449          * return addresses, and doesn't set the LSB correctly (i.e., when
1450          * printing expressions containing function calls, it sets LR = 0.)
1451          * Valid exception return codes have bit 0 set too.
1452          */
1453         if (num == ARMV7M_R14)
1454                 value |= 0x01;
1455 #endif
1456
1457         /* NOTE:  we "know" here that the register identifiers used
1458          * in the v7m header match the Cortex-M3 Debug Core Register
1459          * Selector values for R0..R15, xPSR, MSP, and PSP.
1460          */
1461         switch (num) {
1462         case 0 ... 18:
1463                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1464                 if (retval != ERROR_OK)
1465                 {
1466                         struct reg *r;
1467
1468                         LOG_ERROR("JTAG failure %i", retval);
1469                         r = armv7m->core_cache->reg_list + num;
1470                         r->dirty = r->valid;
1471                         return ERROR_JTAG_DEVICE_ERROR;
1472                 }
1473                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1474                 break;
1475
1476         case ARMV7M_PRIMASK:
1477         case ARMV7M_BASEPRI:
1478         case ARMV7M_FAULTMASK:
1479         case ARMV7M_CONTROL:
1480                 /* Cortex-M3 packages these four registers as bitfields
1481                  * in one Debug Core register.  So say r0 and r2 docs;
1482                  * it was removed from r1 docs, but still works.
1483                  */
1484                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1485
1486                 switch (num)
1487                 {
1488                         case ARMV7M_PRIMASK:
1489                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1490                                 break;
1491
1492                         case ARMV7M_BASEPRI:
1493                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1494                                 break;
1495
1496                         case ARMV7M_FAULTMASK:
1497                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1498                                 break;
1499
1500                         case ARMV7M_CONTROL:
1501                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1502                                 break;
1503                 }
1504
1505                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1506
1507                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1508                 break;
1509
1510         default:
1511                 return ERROR_INVALID_ARGUMENTS;
1512         }
1513
1514         return ERROR_OK;
1515 }
1516
1517 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1518                 uint32_t size, uint32_t count, uint8_t *buffer)
1519 {
1520         struct armv7m_common *armv7m = target_to_armv7m(target);
1521         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1522         int retval = ERROR_INVALID_ARGUMENTS;
1523
1524         /* cortex_m3 handles unaligned memory access */
1525         if (count && buffer) {
1526                 switch (size) {
1527                 case 4:
1528                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1529                         break;
1530                 case 2:
1531                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1532                         break;
1533                 case 1:
1534                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1535                         break;
1536                 }
1537         }
1538
1539         return retval;
1540 }
1541
1542 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1543                 uint32_t size, uint32_t count, uint8_t *buffer)
1544 {
1545         struct armv7m_common *armv7m = target_to_armv7m(target);
1546         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1547         int retval = ERROR_INVALID_ARGUMENTS;
1548
1549         if (count && buffer) {
1550                 switch (size) {
1551                 case 4:
1552                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1553                         break;
1554                 case 2:
1555                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1556                         break;
1557                 case 1:
1558                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1559                         break;
1560                 }
1561         }
1562
1563         return retval;
1564 }
1565
1566 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1567                 uint32_t count, uint8_t *buffer)
1568 {
1569         return cortex_m3_write_memory(target, address, 4, count, buffer);
1570 }
1571
1572 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1573                 struct target *target)
1574 {
1575         armv7m_build_reg_cache(target);
1576         return ERROR_OK;
1577 }
1578
1579 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1580  * on r/w if the core is not running, and clear on resume or reset ... or
1581  * at least, in a post_restore_context() method.
1582  */
1583
1584 struct dwt_reg_state {
1585         struct target   *target;
1586         uint32_t        addr;
1587         uint32_t        value;  /* scratch/cache */
1588 };
1589
1590 static int cortex_m3_dwt_get_reg(struct reg *reg)
1591 {
1592         struct dwt_reg_state *state = reg->arch_info;
1593
1594         return target_read_u32(state->target, state->addr, &state->value);
1595 }
1596
1597 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1598 {
1599         struct dwt_reg_state *state = reg->arch_info;
1600
1601         return target_write_u32(state->target, state->addr,
1602                         buf_get_u32(buf, 0, reg->size));
1603 }
1604
1605 struct dwt_reg {
1606         uint32_t        addr;
1607         char            *name;
1608         unsigned        size;
1609 };
1610
1611 static struct dwt_reg dwt_base_regs[] = {
1612         { DWT_CTRL, "dwt_ctrl", 32, },
1613         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1614          * increments while the core is asleep.
1615          */
1616         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1617         /* plus some 8 bit counters, useful for profiling with TPIU */
1618 };
1619
1620 static struct dwt_reg dwt_comp[] = {
1621 #define DWT_COMPARATOR(i) \
1622                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1623                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1624                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1625         DWT_COMPARATOR(0),
1626         DWT_COMPARATOR(1),
1627         DWT_COMPARATOR(2),
1628         DWT_COMPARATOR(3),
1629 #undef DWT_COMPARATOR
1630 };
1631
1632 static const struct reg_arch_type dwt_reg_type = {
1633         .get = cortex_m3_dwt_get_reg,
1634         .set = cortex_m3_dwt_set_reg,
1635 };
1636
1637 static void
1638 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1639 {
1640         struct dwt_reg_state *state;
1641
1642         state = calloc(1, sizeof *state);
1643         if (!state)
1644                 return;
1645         state->addr = d->addr;
1646         state->target = t;
1647
1648         r->name = d->name;
1649         r->size = d->size;
1650         r->value = &state->value;
1651         r->arch_info = state;
1652         r->type = &dwt_reg_type;
1653 }
1654
1655 static void
1656 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1657 {
1658         uint32_t dwtcr;
1659         struct reg_cache *cache;
1660         struct cortex_m3_dwt_comparator *comparator;
1661         int reg, i;
1662
1663         target_read_u32(target, DWT_CTRL, &dwtcr);
1664         if (!dwtcr) {
1665                 LOG_DEBUG("no DWT");
1666                 return;
1667         }
1668
1669         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1670         cm3->dwt_comp_available = cm3->dwt_num_comp;
1671         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1672                         sizeof(struct cortex_m3_dwt_comparator));
1673         if (!cm3->dwt_comparator_list) {
1674 fail0:
1675                 cm3->dwt_num_comp = 0;
1676                 LOG_ERROR("out of mem");
1677                 return;
1678         }
1679
1680         cache = calloc(1, sizeof *cache);
1681         if (!cache) {
1682 fail1:
1683                 free(cm3->dwt_comparator_list);
1684                 goto fail0;
1685         }
1686         cache->name = "cortex-m3 dwt registers";
1687         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1688         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1689         if (!cache->reg_list) {
1690                 free(cache);
1691                 goto fail1;
1692         }
1693
1694         for (reg = 0; reg < 2; reg++)
1695                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1696                                 dwt_base_regs + reg);
1697
1698         comparator = cm3->dwt_comparator_list;
1699         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1700                 int j;
1701
1702                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1703                 for (j = 0; j < 3; j++, reg++)
1704                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1705                                         dwt_comp + 3 * i + j);
1706         }
1707
1708         *register_get_last_cache_p(&target->reg_cache) = cache;
1709         cm3->dwt_cache = cache;
1710
1711         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1712                         dwtcr, cm3->dwt_num_comp,
1713                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1714
1715         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1716          * implement single-address data value watchpoints ... so we
1717          * won't need to check it later, when asked to set one up.
1718          */
1719 }
1720
1721 static int cortex_m3_examine(struct target *target)
1722 {
1723         int retval;
1724         uint32_t cpuid, fpcr;
1725         int i;
1726         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1727         struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
1728
1729         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1730                 return retval;
1731
1732         if (!target_was_examined(target))
1733         {
1734                 target_set_examined(target);
1735
1736                 /* Read from Device Identification Registers */
1737                 retval = target_read_u32(target, CPUID, &cpuid);
1738                 if (retval != ERROR_OK)
1739                         return retval;
1740
1741                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1742                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1743                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1744                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1745
1746                 /* NOTE: FPB and DWT are both optional. */
1747
1748                 /* Setup FPB */
1749                 target_read_u32(target, FP_CTRL, &fpcr);
1750                 cortex_m3->auto_bp_type = 1;
1751                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1752                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1753                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1754                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1755                 cortex_m3->fpb_enabled = fpcr & 1;
1756                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1757                 {
1758                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1759                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1760                 }
1761                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1762
1763                 /* Setup DWT */
1764                 cortex_m3_dwt_setup(cortex_m3, target);
1765
1766                 /* These hardware breakpoints only work for code in flash! */
1767                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1768                                 target_name(target),
1769                                 cortex_m3->fp_num_code,
1770                                 cortex_m3->dwt_num_comp);
1771         }
1772
1773         return ERROR_OK;
1774 }
1775
1776 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1777 {
1778         uint16_t dcrdr;
1779
1780         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1781         *ctrl = (uint8_t)dcrdr;
1782         *value = (uint8_t)(dcrdr >> 8);
1783
1784         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1785
1786         /* write ack back to software dcc register
1787          * signify we have read data */
1788         if (dcrdr & (1 << 0))
1789         {
1790                 dcrdr = 0;
1791                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1792         }
1793
1794         return ERROR_OK;
1795 }
1796
1797 static int cortex_m3_target_request_data(struct target *target,
1798                 uint32_t size, uint8_t *buffer)
1799 {
1800         struct armv7m_common *armv7m = target_to_armv7m(target);
1801         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1802         uint8_t data;
1803         uint8_t ctrl;
1804         uint32_t i;
1805
1806         for (i = 0; i < (size * 4); i++)
1807         {
1808                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1809                 buffer[i] = data;
1810         }
1811
1812         return ERROR_OK;
1813 }
1814
1815 static int cortex_m3_handle_target_request(void *priv)
1816 {
1817         struct target *target = priv;
1818         if (!target_was_examined(target))
1819                 return ERROR_OK;
1820         struct armv7m_common *armv7m = target_to_armv7m(target);
1821         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1822
1823         if (!target->dbg_msg_enabled)
1824                 return ERROR_OK;
1825
1826         if (target->state == TARGET_RUNNING)
1827         {
1828                 uint8_t data;
1829                 uint8_t ctrl;
1830
1831                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1832
1833                 /* check if we have data */
1834                 if (ctrl & (1 << 0))
1835                 {
1836                         uint32_t request;
1837
1838                         /* we assume target is quick enough */
1839                         request = data;
1840                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1841                         request |= (data << 8);
1842                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1843                         request |= (data << 16);
1844                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1845                         request |= (data << 24);
1846                         target_request(target, request);
1847                 }
1848         }
1849
1850         return ERROR_OK;
1851 }
1852
1853 static int cortex_m3_init_arch_info(struct target *target,
1854                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1855 {
1856         int retval;
1857         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1858
1859         armv7m_init_arch_info(target, armv7m);
1860
1861         /* prepare JTAG information for the new target */
1862         cortex_m3->jtag_info.tap = tap;
1863         cortex_m3->jtag_info.scann_size = 4;
1864
1865         /* Leave (only) generic DAP stuff for debugport_init(); */
1866         armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1867         armv7m->swjdp_info.memaccess_tck = 8;
1868         /* Cortex-M3 has 4096 bytes autoincrement range */
1869         armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
1870
1871         /* register arch-specific functions */
1872         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1873
1874         armv7m->post_debug_entry = NULL;
1875
1876         armv7m->pre_restore_context = NULL;
1877         armv7m->post_restore_context = NULL;
1878
1879         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1880         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1881
1882         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1883
1884         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1885         {
1886                 return retval;
1887         }
1888
1889         return ERROR_OK;
1890 }
1891
1892 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1893 {
1894         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1895
1896         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1897         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1898
1899         return ERROR_OK;
1900 }
1901
1902 /*--------------------------------------------------------------------------*/
1903
1904 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1905                 struct cortex_m3_common *cm3)
1906 {
1907         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1908                 command_print(cmd_ctx, "target is not a Cortex-M3");
1909                 return ERROR_TARGET_INVALID;
1910         }
1911         return ERROR_OK;
1912 }
1913
1914 /*
1915  * Only stuff below this line should need to verify that its target
1916  * is a Cortex-M3.  Everything else should have indirected through the
1917  * cortexm3_target structure, which is only used with CM3 targets.
1918  */
1919
1920 static const struct {
1921         char name[10];
1922         unsigned mask;
1923 } vec_ids[] = {
1924         { "hard_err",   VC_HARDERR, },
1925         { "int_err",    VC_INTERR, },
1926         { "bus_err",    VC_BUSERR, },
1927         { "state_err",  VC_STATERR, },
1928         { "chk_err",    VC_CHKERR, },
1929         { "nocp_err",   VC_NOCPERR, },
1930         { "mm_err",     VC_MMERR, },
1931         { "reset",      VC_CORERESET, },
1932 };
1933
1934 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1935 {
1936         struct target *target = get_current_target(CMD_CTX);
1937         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1938         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1939         struct adiv5_dap *swjdp = &armv7m->swjdp_info;
1940         uint32_t demcr = 0;
1941         int retval;
1942
1943         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1944         if (retval != ERROR_OK)
1945                 return retval;
1946
1947         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1948
1949         if (CMD_ARGC > 0) {
1950                 unsigned catch = 0;
1951
1952                 if (CMD_ARGC == 1) {
1953                         if (strcmp(CMD_ARGV[0], "all") == 0) {
1954                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1955                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
1956                                         | VC_MMERR | VC_CORERESET;
1957                                 goto write;
1958                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1959                                 goto write;
1960                         }
1961                 }
1962                 while (CMD_ARGC-- > 0) {
1963                         unsigned i;
1964                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1965                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1966                                         continue;
1967                                 catch |= vec_ids[i].mask;
1968                                 break;
1969                         }
1970                         if (i == ARRAY_SIZE(vec_ids)) {
1971                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1972                                 return ERROR_INVALID_ARGUMENTS;
1973                         }
1974                 }
1975 write:
1976                 /* For now, armv7m->demcr only stores vector catch flags. */
1977                 armv7m->demcr = catch;
1978
1979                 demcr &= ~0xffff;
1980                 demcr |= catch;
1981
1982                 /* write, but don't assume it stuck (why not??) */
1983                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1984                 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1985
1986                 /* FIXME be sure to clear DEMCR on clean server shutdown.
1987                  * Otherwise the vector catch hardware could fire when there's
1988                  * no debugger hooked up, causing much confusion...
1989                  */
1990         }
1991
1992         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1993         {
1994                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1995                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1996         }
1997
1998         return ERROR_OK;
1999 }
2000
2001 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2002 {
2003         struct target *target = get_current_target(CMD_CTX);
2004         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2005         int retval;
2006
2007         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2008         if (retval != ERROR_OK)
2009                 return retval;
2010
2011         if (target->state != TARGET_HALTED)
2012         {
2013                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2014                 return ERROR_OK;
2015         }
2016
2017         if (CMD_ARGC > 0)
2018         {
2019                 bool enable;
2020                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2021                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2022                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2023                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2024         }
2025
2026         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2027                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2028
2029         return ERROR_OK;
2030 }
2031
2032 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2033         {
2034                 .name = "maskisr",
2035                 .handler = handle_cortex_m3_mask_interrupts_command,
2036                 .mode = COMMAND_EXEC,
2037                 .help = "mask cortex_m3 interrupts",
2038                 .usage = "['on'|'off']",
2039         },
2040         {
2041                 .name = "vector_catch",
2042                 .handler = handle_cortex_m3_vector_catch_command,
2043                 .mode = COMMAND_EXEC,
2044                 .help = "configure hardware vectors to trigger debug entry",
2045                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2046         },
2047         COMMAND_REGISTRATION_DONE
2048 };
2049 static const struct command_registration cortex_m3_command_handlers[] = {
2050         {
2051                 .chain = armv7m_command_handlers,
2052         },
2053         {
2054                 .name = "cortex_m3",
2055                 .mode = COMMAND_EXEC,
2056                 .help = "Cortex-M3 command group",
2057                 .chain = cortex_m3_exec_command_handlers,
2058         },
2059         COMMAND_REGISTRATION_DONE
2060 };
2061
2062 struct target_type cortexm3_target =
2063 {
2064         .name = "cortex_m3",
2065
2066         .poll = cortex_m3_poll,
2067         .arch_state = armv7m_arch_state,
2068
2069         .target_request_data = cortex_m3_target_request_data,
2070
2071         .halt = cortex_m3_halt,
2072         .resume = cortex_m3_resume,
2073         .step = cortex_m3_step,
2074
2075         .assert_reset = cortex_m3_assert_reset,
2076         .deassert_reset = cortex_m3_deassert_reset,
2077         .soft_reset_halt = cortex_m3_soft_reset_halt,
2078
2079         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2080
2081         .read_memory = cortex_m3_read_memory,
2082         .write_memory = cortex_m3_write_memory,
2083         .bulk_write_memory = cortex_m3_bulk_write_memory,
2084         .checksum_memory = armv7m_checksum_memory,
2085         .blank_check_memory = armv7m_blank_check_memory,
2086
2087         .run_algorithm = armv7m_run_algorithm,
2088
2089         .add_breakpoint = cortex_m3_add_breakpoint,
2090         .remove_breakpoint = cortex_m3_remove_breakpoint,
2091         .add_watchpoint = cortex_m3_add_watchpoint,
2092         .remove_watchpoint = cortex_m3_remove_watchpoint,
2093
2094         .commands = cortex_m3_command_handlers,
2095         .target_create = cortex_m3_target_create,
2096         .init_target = cortex_m3_init_target,
2097         .examine = cortex_m3_examine,
2098 };