git.sur5r.net Git - openocd/blob - src/target/cortex_m3.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FBP remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54
  55 /* forward declarations */
  56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58 static void cortex_m3_enable_watchpoints(struct target *target);
  59 static int cortex_m3_store_core_reg_u32(struct target *target,
  60                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  61
  62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  63                 uint32_t *value, int regnum)
  64 {
  65         int retval;
  66         uint32_t dcrdr;
  67
  68         /* because the DCB_DCRDR is used for the emulated dcc channel
  69          * we have to save/restore the DCB_DCRDR when used */
  70
  71         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  72         if (retval != ERROR_OK)
  73                 return retval;
  74
  75         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  76         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  77         if (retval != ERROR_OK)
  78                 return retval;
  79         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  80         if (retval != ERROR_OK)
  81                 return retval;
  82
  83         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  84         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  85         if (retval != ERROR_OK)
  86                 return retval;
  87         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  88         if (retval != ERROR_OK)
  89                 return retval;
  90
  91         retval = dap_run(swjdp);
  92         if (retval != ERROR_OK)
  93                 return retval;
  94
  95         /* restore DCB_DCRDR - this needs to be in a seperate
  96          * transaction otherwise the emulated DCC channel breaks */
  97         if (retval == ERROR_OK)
  98                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  99
 100         return retval;
 101 }
 102
 103 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 104                 uint32_t value, int regnum)
 105 {
 106         int retval;
 107         uint32_t dcrdr;
 108
 109         /* because the DCB_DCRDR is used for the emulated dcc channel
 110          * we have to save/restore the DCB_DCRDR when used */
 111
 112         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 113         if (retval != ERROR_OK)
 114                 return retval;
 115
 116         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 117         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 118         if (retval != ERROR_OK)
 119                 return retval;
 120         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 121         // XXX check retval
 122
 123         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 124         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 125         if (retval != ERROR_OK)
 126                 return retval;
 127         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 128         // XXX check retval
 129
 130         retval = dap_run(swjdp);
 131
 132         /* restore DCB_DCRDR - this needs to be in a seperate
 133          * transaction otherwise the emulated DCC channel breaks */
 134         if (retval == ERROR_OK)
 135                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 136
 137         return retval;
 138 }
 139
 140 static int cortex_m3_write_debug_halt_mask(struct target *target,
 141                 uint32_t mask_on, uint32_t mask_off)
 142 {
 143         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 144         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 145
 146         /* mask off status bits */
 147         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 148         /* create new register mask */
 149         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 150
 151         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 152 }
 153
 154 static int cortex_m3_clear_halt(struct target *target)
 155 {
 156         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 157         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 158         int retval;
 159
 160         /* clear step if any */
 161         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 162
 163         /* Read Debug Fault Status Register */
 164         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 165         if (retval != ERROR_OK)
 166                 return retval;
 167
 168         /* Clear Debug Fault Status */
 169         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 170         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 171
 172         return ERROR_OK;
 173 }
 174
 175 static int cortex_m3_single_step_core(struct target *target)
 176 {
 177         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 178         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 179         uint32_t dhcsr_save;
 180
 181         /* backup dhcsr reg */
 182         dhcsr_save = cortex_m3->dcb_dhcsr;
 183
 184         /* Mask interrupts before clearing halt, if done already.  This avoids
 185          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 186          * HALT can put the core into an unknown state.
 187          */
 188         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 189                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 190                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 191         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 192                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 193         LOG_DEBUG(" ");
 194
 195         /* restore dhcsr reg */
 196         cortex_m3->dcb_dhcsr = dhcsr_save;
 197         cortex_m3_clear_halt(target);
 198
 199         return ERROR_OK;
 200 }
 201
 202 static int cortex_m3_endreset_event(struct target *target)
 203 {
 204         int i;
 205         int retval;
 206         uint32_t dcb_demcr;
 207         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 208         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 209         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 210         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 211         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 212
 213         /* REVISIT The four debug monitor bits are currently ignored... */
 214         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 215         if (retval != ERROR_OK)
 216                 return retval;
 217         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 218
 219         /* this register is used for emulated dcc channel */
 220         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 221
 222         /* Enable debug requests */
 223         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 227                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 228
 229         /* clear any interrupt masking */
 230         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 231
 232         /* Enable features controlled by ITM and DWT blocks, and catch only
 233          * the vectors we were told to pay attention to.
 234          *
 235          * Target firmware is responsible for all fault handling policy
 236          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 237          * or manual updates to the NVIC SHCSR and CCR registers.
 238          */
 239         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 240
 241         /* Paranoia: evidently some (early?) chips don't preserve all the
 242          * debug state (including FBP, DWT, etc) across reset...
 243          */
 244
 245         /* Enable FPB */
 246         target_write_u32(target, FP_CTRL, 3);
 247         cortex_m3->fpb_enabled = 1;
 248
 249         /* Restore FPB registers */
 250         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 251         {
 252                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 253         }
 254
 255         /* Restore DWT registers */
 256         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 257         {
 258                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 259                                 dwt_list[i].comp);
 260                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 261                                 dwt_list[i].mask);
 262                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 263                                 dwt_list[i].function);
 264         }
 265         retval = dap_run(swjdp);
 266         if (retval != ERROR_OK)
 267                 return retval;
 268
 269         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 270
 271         /* make sure we have latest dhcsr flags */
 272         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 273
 274         return retval;
 275 }
 276
 277 static int cortex_m3_examine_debug_reason(struct target *target)
 278 {
 279         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 280
 281         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 282         /* only check the debug reason if we don't know it already */
 283
 284         if ((target->debug_reason != DBG_REASON_DBGRQ)
 285                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 286         {
 287                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 288                 {
 289                         target->debug_reason = DBG_REASON_BREAKPOINT;
 290                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 291                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 292                 }
 293                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 294                         target->debug_reason = DBG_REASON_WATCHPOINT;
 295                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 296                         target->debug_reason = DBG_REASON_BREAKPOINT;
 297                 else /* EXTERNAL, HALTED */
 298                         target->debug_reason = DBG_REASON_UNDEFINED;
 299         }
 300
 301         return ERROR_OK;
 302 }
 303
 304 static int cortex_m3_examine_exception_reason(struct target *target)
 305 {
 306         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 307         struct armv7m_common *armv7m = target_to_armv7m(target);
 308         struct adiv5_dap *swjdp = &armv7m->dap;
 309         int retval;
 310
 311         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 312         if (retval != ERROR_OK)
 313                 return retval;
 314         switch (armv7m->exception_number)
 315         {
 316                 case 2: /* NMI */
 317                         break;
 318                 case 3: /* Hard Fault */
 319                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 320                         if (retval != ERROR_OK)
 321                                 return retval;
 322                         if (except_sr & 0x40000000)
 323                         {
 324                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 325                                 if (retval != ERROR_OK)
 326                                         return retval;
 327                         }
 328                         break;
 329                 case 4: /* Memory Management */
 330                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 331                         if (retval != ERROR_OK)
 332                                 return retval;
 333                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 334                         if (retval != ERROR_OK)
 335                                 return retval;
 336                         break;
 337                 case 5: /* Bus Fault */
 338                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 339                         if (retval != ERROR_OK)
 340                                 return retval;
 341                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 342                         if (retval != ERROR_OK)
 343                                 return retval;
 344                         break;
 345                 case 6: /* Usage Fault */
 346                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 347                         if (retval != ERROR_OK)
 348                                 return retval;
 349                         break;
 350                 case 11:        /* SVCall */
 351                         break;
 352                 case 12:        /* Debug Monitor */
 353                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 354                         if (retval != ERROR_OK)
 355                                 return retval;
 356                         break;
 357                 case 14:        /* PendSV */
 358                         break;
 359                 case 15:        /* SysTick */
 360                         break;
 361                 default:
 362                         except_sr = 0;
 363                         break;
 364         }
 365         retval = dap_run(swjdp);
 366         if (retval == ERROR_OK)
 367                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 368                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 369                         armv7m_exception_string(armv7m->exception_number),
 370                         shcsr, except_sr, cfsr, except_ar);
 371         return retval;
 372 }
 373
 374 /* PSP is used in some thread modes */
 375 static const int armv7m_psp_reg_map[17] = {
 376         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 377         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 378         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 379         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 380         ARMV7M_xPSR,
 381 };
 382
 383 /* MSP is used in handler and some thread modes */
 384 static const int armv7m_msp_reg_map[17] = {
 385         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 386         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 387         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 388         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 389         ARMV7M_xPSR,
 390 };
 391
 392 static int cortex_m3_debug_entry(struct target *target)
 393 {
 394         int i;
 395         uint32_t xPSR;
 396         int retval;
 397         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 398         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 399         struct arm *arm = &armv7m->arm;
 400         struct adiv5_dap *swjdp = &armv7m->dap;
 401         struct reg *r;
 402
 403         LOG_DEBUG(" ");
 404
 405         cortex_m3_clear_halt(target);
 406         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 407         if (retval != ERROR_OK)
 408                 return retval;
 409
 410         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 411                 return retval;
 412
 413         /* Examine target state and mode */
 414         /* First load register acessible through core debug port*/
 415         int num_regs = armv7m->core_cache->num_regs;
 416
 417         for (i = 0; i < num_regs; i++)
 418         {
 419                 if (!armv7m->core_cache->reg_list[i].valid)
 420                         armv7m->read_core_reg(target, i);
 421         }
 422
 423         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 424         xPSR = buf_get_u32(r->value, 0, 32);
 425
 426 #ifdef ARMV7_GDB_HACKS
 427         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 428          * Instead, each CM3 should have its own dummy value...
 429          */
 430         /* copy real xpsr reg for gdb, setting thumb bit */
 431         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 432         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 433         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 434         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 435 #endif
 436
 437         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 438         if (xPSR & 0xf00)
 439         {
 440                 r->dirty = r->valid;
 441                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 442         }
 443
 444         /* Are we in an exception handler */
 445         if (xPSR & 0x1FF)
 446         {
 447                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 448                 armv7m->exception_number = (xPSR & 0x1FF);
 449
 450                 arm->core_mode = ARM_MODE_HANDLER;
 451                 arm->map = armv7m_msp_reg_map;
 452         }
 453         else
 454         {
 455                 unsigned control = buf_get_u32(armv7m->core_cache
 456                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 457
 458                 /* is this thread privileged? */
 459                 armv7m->core_mode = control & 1;
 460                 arm->core_mode = armv7m->core_mode
 461                                 ? ARM_MODE_USER_THREAD
 462                                 : ARM_MODE_THREAD;
 463
 464                 /* which stack is it using? */
 465                 if (control & 2)
 466                         arm->map = armv7m_psp_reg_map;
 467                 else
 468                         arm->map = armv7m_msp_reg_map;
 469
 470                 armv7m->exception_number = 0;
 471         }
 472
 473         if (armv7m->exception_number)
 474         {
 475                 cortex_m3_examine_exception_reason(target);
 476         }
 477
 478         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 479                 armv7m_mode_strings[armv7m->core_mode],
 480                 *(uint32_t*)(arm->pc->value),
 481                 target_state_name(target));
 482
 483         if (armv7m->post_debug_entry)
 484         {
 485                 retval = armv7m->post_debug_entry(target);
 486                 if (retval != ERROR_OK)
 487                         return retval;
 488         }
 489
 490         return ERROR_OK;
 491 }
 492
 493 static int cortex_m3_poll(struct target *target)
 494 {
 495         int retval;
 496         enum target_state prev_target_state = target->state;
 497         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 498         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 499
 500         /* Read from Debug Halting Control and Status Register */
 501         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 502         if (retval != ERROR_OK)
 503         {
 504                 target->state = TARGET_UNKNOWN;
 505                 return retval;
 506         }
 507
 508         /* Recover from lockup.  See ARMv7-M architecture spec,
 509          * section B1.5.15 "Unrecoverable exception cases".
 510          *
 511          * REVISIT Is there a better way to report and handle this?
 512          */
 513         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 514                 LOG_WARNING("%s -- clearing lockup after double fault",
 515                                 target_name(target));
 516                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 517                 target->debug_reason = DBG_REASON_DBGRQ;
 518
 519                 /* refresh status bits */
 520                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 521                 if (retval != ERROR_OK)
 522                         return retval;
 523         }
 524
 525         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 526         {
 527                 /* check if still in reset */
 528                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 529                 if (retval != ERROR_OK)
 530                         return retval;
 531
 532                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 533                 {
 534                         target->state = TARGET_RESET;
 535                         return ERROR_OK;
 536                 }
 537         }
 538
 539         if (target->state == TARGET_RESET)
 540         {
 541                 /* Cannot switch context while running so endreset is
 542                  * called with target->state == TARGET_RESET
 543                  */
 544                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 545                                 cortex_m3->dcb_dhcsr);
 546                 cortex_m3_endreset_event(target);
 547                 target->state = TARGET_RUNNING;
 548                 prev_target_state = TARGET_RUNNING;
 549         }
 550
 551         if (cortex_m3->dcb_dhcsr & S_HALT)
 552         {
 553                 target->state = TARGET_HALTED;
 554
 555                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 556                 {
 557                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 558                                 return retval;
 559
 560                         if (arm_semihosting(target, &retval) != 0)
 561                                 return retval;
 562
 563                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 564                 }
 565                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 566                 {
 567                         LOG_DEBUG(" ");
 568                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 569                                 return retval;
 570
 571                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 572                 }
 573         }
 574
 575         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 576          * How best to model low power modes?
 577          */
 578
 579         if (target->state == TARGET_UNKNOWN)
 580         {
 581                 /* check if processor is retiring instructions */
 582                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 583                 {
 584                         target->state = TARGET_RUNNING;
 585                         return ERROR_OK;
 586                 }
 587         }
 588
 589         return ERROR_OK;
 590 }
 591
 592 static int cortex_m3_halt(struct target *target)
 593 {
 594         LOG_DEBUG("target->state: %s",
 595                 target_state_name(target));
 596
 597         if (target->state == TARGET_HALTED)
 598         {
 599                 LOG_DEBUG("target was already halted");
 600                 return ERROR_OK;
 601         }
 602
 603         if (target->state == TARGET_UNKNOWN)
 604         {
 605                 LOG_WARNING("target was in unknown state when halt was requested");
 606         }
 607
 608         if (target->state == TARGET_RESET)
 609         {
 610                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 611                 {
 612                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 613                         return ERROR_TARGET_FAILURE;
 614                 }
 615                 else
 616                 {
 617                         /* we came here in a reset_halt or reset_init sequence
 618                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 619                          */
 620                         target->debug_reason = DBG_REASON_DBGRQ;
 621
 622                         return ERROR_OK;
 623                 }
 624         }
 625
 626         /* Write to Debug Halting Control and Status Register */
 627         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 628
 629         target->debug_reason = DBG_REASON_DBGRQ;
 630
 631         return ERROR_OK;
 632 }
 633
 634 static int cortex_m3_soft_reset_halt(struct target *target)
 635 {
 636         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 637         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 638         uint32_t dcb_dhcsr = 0;
 639         int retval, timeout = 0;
 640
 641         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 642         mem_ap_write_u32(swjdp, DCB_DEMCR,
 643                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 644
 645         /* Request a core-only reset */
 646         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 647                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 648         target->state = TARGET_RESET;
 649
 650         /* registers are now invalid */
 651         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 652
 653         while (timeout < 100)
 654         {
 655                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 656                 if (retval == ERROR_OK)
 657                 {
 658                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 659                                         &cortex_m3->nvic_dfsr);
 660                         if (retval != ERROR_OK)
 661                                 return retval;
 662                         if ((dcb_dhcsr & S_HALT)
 663                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 664                         {
 665                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 666                                         "DFSR 0x%08x",
 667                                         (unsigned) dcb_dhcsr,
 668                                         (unsigned) cortex_m3->nvic_dfsr);
 669                                 cortex_m3_poll(target);
 670                                 /* FIXME restore user's vector catch config */
 671                                 return ERROR_OK;
 672                         }
 673                         else
 674                                 LOG_DEBUG("waiting for system reset-halt, "
 675                                         "DHCSR 0x%08x, %d ms",
 676                                         (unsigned) dcb_dhcsr, timeout);
 677                 }
 678                 timeout++;
 679                 alive_sleep(1);
 680         }
 681
 682         return ERROR_OK;
 683 }
 684
 685 static void cortex_m3_enable_breakpoints(struct target *target)
 686 {
 687         struct breakpoint *breakpoint = target->breakpoints;
 688
 689         /* set any pending breakpoints */
 690         while (breakpoint)
 691         {
 692                 if (!breakpoint->set)
 693                         cortex_m3_set_breakpoint(target, breakpoint);
 694                 breakpoint = breakpoint->next;
 695         }
 696 }
 697
 698 static int cortex_m3_resume(struct target *target, int current,
 699                 uint32_t address, int handle_breakpoints, int debug_execution)
 700 {
 701         struct armv7m_common *armv7m = target_to_armv7m(target);
 702         struct breakpoint *breakpoint = NULL;
 703         uint32_t resume_pc;
 704         struct reg *r;
 705
 706         if (target->state != TARGET_HALTED)
 707         {
 708                 LOG_WARNING("target not halted");
 709                 return ERROR_TARGET_NOT_HALTED;
 710         }
 711
 712         if (!debug_execution)
 713         {
 714                 target_free_all_working_areas(target);
 715                 cortex_m3_enable_breakpoints(target);
 716                 cortex_m3_enable_watchpoints(target);
 717         }
 718
 719         if (debug_execution)
 720         {
 721                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 722
 723                 /* Disable interrupts */
 724                 /* We disable interrupts in the PRIMASK register instead of
 725                  * masking with C_MASKINTS.  This is probably the same issue
 726                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 727                  * in parallel with disabled interrupts can cause local faults
 728                  * to not be taken.
 729                  *
 730                  * REVISIT this clearly breaks non-debug execution, since the
 731                  * PRIMASK register state isn't saved/restored...  workaround
 732                  * by never resuming app code after debug execution.
 733                  */
 734                 buf_set_u32(r->value, 0, 1, 1);
 735                 r->dirty = true;
 736                 r->valid = true;
 737
 738                 /* Make sure we are in Thumb mode */
 739                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 740                 buf_set_u32(r->value, 24, 1, 1);
 741                 r->dirty = true;
 742                 r->valid = true;
 743         }
 744
 745         /* current = 1: continue on current pc, otherwise continue at <address> */
 746         r = armv7m->arm.pc;
 747         if (!current)
 748         {
 749                 buf_set_u32(r->value, 0, 32, address);
 750                 r->dirty = true;
 751                 r->valid = true;
 752         }
 753
 754         /* if we halted last time due to a bkpt instruction
 755          * then we have to manually step over it, otherwise
 756          * the core will break again */
 757
 758         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 759                         && !debug_execution)
 760         {
 761                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 762         }
 763
 764         resume_pc = buf_get_u32(r->value, 0, 32);
 765
 766         armv7m_restore_context(target);
 767
 768         /* the front-end may request us not to handle breakpoints */
 769         if (handle_breakpoints)
 770         {
 771                 /* Single step past breakpoint at current address */
 772                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 773                 {
 774                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 775                                           breakpoint->address,
 776                                           breakpoint->unique_id);
 777                         cortex_m3_unset_breakpoint(target, breakpoint);
 778                         cortex_m3_single_step_core(target);
 779                         cortex_m3_set_breakpoint(target, breakpoint);
 780                 }
 781         }
 782
 783         /* Restart core */
 784         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 785
 786         target->debug_reason = DBG_REASON_NOTHALTED;
 787
 788         /* registers are now invalid */
 789         register_cache_invalidate(armv7m->core_cache);
 790
 791         if (!debug_execution)
 792         {
 793                 target->state = TARGET_RUNNING;
 794                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 795                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 796         }
 797         else
 798         {
 799                 target->state = TARGET_DEBUG_RUNNING;
 800                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 801                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 802         }
 803
 804         return ERROR_OK;
 805 }
 806
 807 /* int irqstepcount = 0; */
 808 static int cortex_m3_step(struct target *target, int current,
 809                 uint32_t address, int handle_breakpoints)
 810 {
 811         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 812         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 813         struct adiv5_dap *swjdp = &armv7m->dap;
 814         struct breakpoint *breakpoint = NULL;
 815         struct reg *pc = armv7m->arm.pc;
 816         bool bkpt_inst_found = false;
 817
 818         if (target->state != TARGET_HALTED)
 819         {
 820                 LOG_WARNING("target not halted");
 821                 return ERROR_TARGET_NOT_HALTED;
 822         }
 823
 824         /* current = 1: continue on current pc, otherwise continue at <address> */
 825         if (!current)
 826                 buf_set_u32(pc->value, 0, 32, address);
 827
 828         /* the front-end may request us not to handle breakpoints */
 829         if (handle_breakpoints) {
 830                 breakpoint = breakpoint_find(target,
 831                                 buf_get_u32(pc->value, 0, 32));
 832                 if (breakpoint)
 833                         cortex_m3_unset_breakpoint(target, breakpoint);
 834         }
 835
 836         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 837
 838         target->debug_reason = DBG_REASON_SINGLESTEP;
 839
 840         armv7m_restore_context(target);
 841
 842         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 843
 844         /* if no bkpt instruction is found at pc then we can perform
 845          * a normal step, otherwise we have to manually step over the bkpt
 846          * instruction - as such simulate a step */
 847         if (bkpt_inst_found == false)
 848         {
 849                 /* set step and clear halt */
 850                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 851         }
 852
 853         int retval;
 854         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 855         if (retval != ERROR_OK)
 856                 return retval;
 857
 858         /* registers are now invalid */
 859         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 860
 861         if (breakpoint)
 862                 cortex_m3_set_breakpoint(target, breakpoint);
 863
 864         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 865                         " nvic_icsr = 0x%" PRIx32,
 866                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 867
 868         retval = cortex_m3_debug_entry(target);
 869         if (retval != ERROR_OK)
 870                 return retval;
 871         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 872
 873         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 874                         " nvic_icsr = 0x%" PRIx32,
 875                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 876
 877         return ERROR_OK;
 878 }
 879
 880 static int cortex_m3_assert_reset(struct target *target)
 881 {
 882         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 883         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 884         int assert_srst = 1;
 885
 886         LOG_DEBUG("target->state: %s",
 887                 target_state_name(target));
 888
 889         enum reset_types jtag_reset_config = jtag_get_reset_config();
 890
 891         /*
 892          * We can reset Cortex-M3 targets using just the NVIC without
 893          * requiring SRST, getting a SoC reset (or a core-only reset)
 894          * instead of a system reset.
 895          */
 896         if (!(jtag_reset_config & RESET_HAS_SRST))
 897                 assert_srst = 0;
 898
 899         /* Enable debug requests */
 900         int retval;
 901         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 902         if (retval != ERROR_OK)
 903                 return retval;
 904         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 905                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 906
 907         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 908
 909         if (!target->reset_halt)
 910         {
 911                 /* Set/Clear C_MASKINTS in a separate operation */
 912                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 913                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 914                                         DBGKEY | C_DEBUGEN | C_HALT);
 915
 916                 /* clear any debug flags before resuming */
 917                 cortex_m3_clear_halt(target);
 918
 919                 /* clear C_HALT in dhcsr reg */
 920                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 921         }
 922         else
 923         {
 924                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 925                  *
 926                  * REVISIT catching BUSERR presumably helps to defend against
 927                  * bad vector table entries.  Should this include MMERR or
 928                  * other flags too?
 929                  */
 930                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 931                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 932         }
 933
 934         /*
 935          * When nRST is asserted on most Stellaris devices, it clears some of
 936          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 937          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 938          * chips.  (Only power-on reset should affect debug state, beyond a
 939          * few specified bits; not the chip's nRST input, wired to SRST.)
 940          *
 941          * REVISIT current errata specs don't seem to cover this issue.
 942          * Do we have more details than this email?
 943          *   https://lists.berlios.de/pipermail
 944          *      /openocd-development/2008-August/003065.html
 945          */
 946         if (strcmp(target->variant, "lm3s") == 0)
 947         {
 948                 /* Check for silicon revisions with the issue. */
 949                 uint32_t did0;
 950
 951                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 952                 {
 953                         switch ((did0 >> 16) & 0xff)
 954                         {
 955                                 case 0:
 956                                         /* all Sandstorm suffer issue */
 957                                         assert_srst = 0;
 958                                         break;
 959
 960                                 case 1:
 961                                 case 3:
 962                                         /* Fury and DustDevil rev A have
 963                                          * this nRST problem.  It should
 964                                          * be fixed in rev B silicon.
 965                                          */
 966                                         if (((did0 >> 8) & 0xff) == 0)
 967                                                 assert_srst = 0;
 968                                         break;
 969                                 case 4:
 970                                         /* Tempest should be fine. */
 971                                         break;
 972                         }
 973                 }
 974         }
 975
 976         if (assert_srst)
 977         {
 978                 /* default to asserting srst */
 979                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 980                 {
 981                         jtag_add_reset(1, 1);
 982                 }
 983                 else
 984                 {
 985                         jtag_add_reset(0, 1);
 986                 }
 987         }
 988         else
 989         {
 990                 /* Use a standard Cortex-M3 software reset mechanism.
 991                  * SYSRESETREQ will reset SoC peripherals outside the
 992                  * core, like watchdog timers, if the SoC wires it up
 993                  * correctly.  Else VECRESET can reset just the core.
 994                  */
 995                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 996                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 997                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 998
 999                 {
1000                         /* I do not know why this is necessary, but it
1001                          * fixes strange effects (step/resume cause NMI
1002                          * after reset) on LM3S6918 -- Michael Schwingen
1003                          */
1004                         uint32_t tmp;
1005                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1006                         if (retval != ERROR_OK)
1007                                 return retval;
1008                 }
1009         }
1010
1011         target->state = TARGET_RESET;
1012         jtag_add_sleep(50000);
1013
1014         register_cache_invalidate(cortex_m3->armv7m.core_cache);
1015
1016         if (target->reset_halt)
1017         {
1018                 if ((retval = target_halt(target)) != ERROR_OK)
1019                         return retval;
1020         }
1021
1022         return ERROR_OK;
1023 }
1024
1025 static int cortex_m3_deassert_reset(struct target *target)
1026 {
1027         LOG_DEBUG("target->state: %s",
1028                 target_state_name(target));
1029
1030         /* deassert reset lines */
1031         jtag_add_reset(0, 0);
1032
1033         return ERROR_OK;
1034 }
1035
1036 static int
1037 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1038 {
1039         int retval;
1040         int fp_num = 0;
1041         uint32_t hilo;
1042         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1043         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1044
1045         if (breakpoint->set)
1046         {
1047                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1048                 return ERROR_OK;
1049         }
1050
1051         if (cortex_m3->auto_bp_type)
1052         {
1053                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1054         }
1055
1056         if (breakpoint->type == BKPT_HARD)
1057         {
1058                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1059                         fp_num++;
1060                 if (fp_num >= cortex_m3->fp_num_code)
1061                 {
1062                         LOG_ERROR("Can not find free FPB Comparator!");
1063                         return ERROR_FAIL;
1064                 }
1065                 breakpoint->set = fp_num + 1;
1066                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1067                 comparator_list[fp_num].used = 1;
1068                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1069                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1070                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1071                 if (!cortex_m3->fpb_enabled)
1072                 {
1073                         LOG_DEBUG("FPB wasn't enabled, do it now");
1074                         target_write_u32(target, FP_CTRL, 3);
1075                 }
1076         }
1077         else if (breakpoint->type == BKPT_SOFT)
1078         {
1079                 uint8_t code[4];
1080
1081                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1082                  * semihosting; don't use that.  Otherwise the BKPT
1083                  * parameter is arbitrary.
1084                  */
1085                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1086                 retval = target_read_memory(target,
1087                                 breakpoint->address & 0xFFFFFFFE,
1088                                 breakpoint->length, 1,
1089                                 breakpoint->orig_instr);
1090                 if (retval != ERROR_OK)
1091                         return retval;
1092                 retval = target_write_memory(target,
1093                                 breakpoint->address & 0xFFFFFFFE,
1094                                 breakpoint->length, 1,
1095                                 code);
1096                 if (retval != ERROR_OK)
1097                         return retval;
1098                 breakpoint->set = true;
1099         }
1100
1101         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1102                           breakpoint->unique_id,
1103                           (int)(breakpoint->type),
1104                           breakpoint->address,
1105                           breakpoint->length,
1106                           breakpoint->set);
1107
1108         return ERROR_OK;
1109 }
1110
1111 static int
1112 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1113 {
1114         int retval;
1115         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1116         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1117
1118         if (!breakpoint->set)
1119         {
1120                 LOG_WARNING("breakpoint not set");
1121                 return ERROR_OK;
1122         }
1123
1124         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1125                           breakpoint->unique_id,
1126                           (int)(breakpoint->type),
1127                           breakpoint->address,
1128                           breakpoint->length,
1129                           breakpoint->set);
1130
1131         if (breakpoint->type == BKPT_HARD)
1132         {
1133                 int fp_num = breakpoint->set - 1;
1134                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1135                 {
1136                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1137                         return ERROR_OK;
1138                 }
1139                 comparator_list[fp_num].used = 0;
1140                 comparator_list[fp_num].fpcr_value = 0;
1141                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1142         }
1143         else
1144         {
1145                 /* restore original instruction (kept in target endianness) */
1146                 if (breakpoint->length == 4)
1147                 {
1148                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1149                         {
1150                                 return retval;
1151                         }
1152                 }
1153                 else
1154                 {
1155                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1156                         {
1157                                 return retval;
1158                         }
1159                 }
1160         }
1161         breakpoint->set = false;
1162
1163         return ERROR_OK;
1164 }
1165
1166 static int
1167 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1168 {
1169         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1170
1171         if (cortex_m3->auto_bp_type)
1172         {
1173                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1174 #ifdef ARMV7_GDB_HACKS
1175                 if (breakpoint->length != 2) {
1176                         /* XXX Hack: Replace all breakpoints with length != 2 with
1177                          * a hardware breakpoint. */
1178                         breakpoint->type = BKPT_HARD;
1179                         breakpoint->length = 2;
1180                 }
1181 #endif
1182         }
1183
1184         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1185         {
1186                 LOG_INFO("flash patch comparator requested outside code memory region");
1187                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1188         }
1189
1190         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1191         {
1192                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1193                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1194         }
1195
1196         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1197         {
1198                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1199                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1200         }
1201
1202         if ((breakpoint->length != 2))
1203         {
1204                 LOG_INFO("only breakpoints of two bytes length supported");
1205                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1206         }
1207
1208         if (breakpoint->type == BKPT_HARD)
1209                 cortex_m3->fp_code_available--;
1210         cortex_m3_set_breakpoint(target, breakpoint);
1211
1212         return ERROR_OK;
1213 }
1214
1215 static int
1216 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1217 {
1218         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1219
1220         /* REVISIT why check? FBP can be updated with core running ... */
1221         if (target->state != TARGET_HALTED)
1222         {
1223                 LOG_WARNING("target not halted");
1224                 return ERROR_TARGET_NOT_HALTED;
1225         }
1226
1227         if (cortex_m3->auto_bp_type)
1228         {
1229                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1230         }
1231
1232         if (breakpoint->set)
1233         {
1234                 cortex_m3_unset_breakpoint(target, breakpoint);
1235         }
1236
1237         if (breakpoint->type == BKPT_HARD)
1238                 cortex_m3->fp_code_available++;
1239
1240         return ERROR_OK;
1241 }
1242
1243 static int
1244 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1245 {
1246         int dwt_num = 0;
1247         uint32_t mask, temp;
1248         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1249
1250         /* watchpoint params were validated earlier */
1251         mask = 0;
1252         temp = watchpoint->length;
1253         while (temp) {
1254                 temp >>= 1;
1255                 mask++;
1256         }
1257         mask--;
1258
1259         /* REVISIT Don't fully trust these "not used" records ... users
1260          * may set up breakpoints by hand, e.g. dual-address data value
1261          * watchpoint using comparator #1; comparator #0 matching cycle
1262          * count; send data trace info through ITM and TPIU; etc
1263          */
1264         struct cortex_m3_dwt_comparator *comparator;
1265
1266         for (comparator = cortex_m3->dwt_comparator_list;
1267                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1268                         comparator++, dwt_num++)
1269                 continue;
1270         if (dwt_num >= cortex_m3->dwt_num_comp)
1271         {
1272                 LOG_ERROR("Can not find free DWT Comparator");
1273                 return ERROR_FAIL;
1274         }
1275         comparator->used = 1;
1276         watchpoint->set = dwt_num + 1;
1277
1278         comparator->comp = watchpoint->address;
1279         target_write_u32(target, comparator->dwt_comparator_address + 0,
1280                         comparator->comp);
1281
1282         comparator->mask = mask;
1283         target_write_u32(target, comparator->dwt_comparator_address + 4,
1284                         comparator->mask);
1285
1286         switch (watchpoint->rw) {
1287         case WPT_READ:
1288                 comparator->function = 5;
1289                 break;
1290         case WPT_WRITE:
1291                 comparator->function = 6;
1292                 break;
1293         case WPT_ACCESS:
1294                 comparator->function = 7;
1295                 break;
1296         }
1297         target_write_u32(target, comparator->dwt_comparator_address + 8,
1298                         comparator->function);
1299
1300         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1301                         watchpoint->unique_id, dwt_num,
1302                         (unsigned) comparator->comp,
1303                         (unsigned) comparator->mask,
1304                         (unsigned) comparator->function);
1305         return ERROR_OK;
1306 }
1307
1308 static int
1309 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1310 {
1311         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1312         struct cortex_m3_dwt_comparator *comparator;
1313         int dwt_num;
1314
1315         if (!watchpoint->set)
1316         {
1317                 LOG_WARNING("watchpoint (wpid: %d) not set",
1318                                 watchpoint->unique_id);
1319                 return ERROR_OK;
1320         }
1321
1322         dwt_num = watchpoint->set - 1;
1323
1324         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1325                         watchpoint->unique_id, dwt_num,
1326                         (unsigned) watchpoint->address);
1327
1328         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1329         {
1330                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1331                 return ERROR_OK;
1332         }
1333
1334         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1335         comparator->used = 0;
1336         comparator->function = 0;
1337         target_write_u32(target, comparator->dwt_comparator_address + 8,
1338                         comparator->function);
1339
1340         watchpoint->set = false;
1341
1342         return ERROR_OK;
1343 }
1344
1345 static int
1346 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1347 {
1348         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1349
1350         if (cortex_m3->dwt_comp_available < 1)
1351         {
1352                 LOG_DEBUG("no comparators?");
1353                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1354         }
1355
1356         /* hardware doesn't support data value masking */
1357         if (watchpoint->mask != ~(uint32_t)0) {
1358                 LOG_DEBUG("watchpoint value masks not supported");
1359                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1360         }
1361
1362         /* hardware allows address masks of up to 32K */
1363         unsigned mask;
1364
1365         for (mask = 0; mask < 16; mask++) {
1366                 if ((1u << mask) == watchpoint->length)
1367                         break;
1368         }
1369         if (mask == 16) {
1370                 LOG_DEBUG("unsupported watchpoint length");
1371                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1372         }
1373         if (watchpoint->address & ((1 << mask) - 1)) {
1374                 LOG_DEBUG("watchpoint address is unaligned");
1375                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1376         }
1377
1378         /* Caller doesn't seem to be able to describe watching for data
1379          * values of zero; that flags "no value".
1380          *
1381          * REVISIT This DWT may well be able to watch for specific data
1382          * values.  Requires comparator #1 to set DATAVMATCH and match
1383          * the data, and another comparator (DATAVADDR0) matching addr.
1384          */
1385         if (watchpoint->value) {
1386                 LOG_DEBUG("data value watchpoint not YET supported");
1387                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1388         }
1389
1390         cortex_m3->dwt_comp_available--;
1391         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1392
1393         return ERROR_OK;
1394 }
1395
1396 static int
1397 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1398 {
1399         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1400
1401         /* REVISIT why check? DWT can be updated with core running ... */
1402         if (target->state != TARGET_HALTED)
1403         {
1404                 LOG_WARNING("target not halted");
1405                 return ERROR_TARGET_NOT_HALTED;
1406         }
1407
1408         if (watchpoint->set)
1409         {
1410                 cortex_m3_unset_watchpoint(target, watchpoint);
1411         }
1412
1413         cortex_m3->dwt_comp_available++;
1414         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1415
1416         return ERROR_OK;
1417 }
1418
1419 static void cortex_m3_enable_watchpoints(struct target *target)
1420 {
1421         struct watchpoint *watchpoint = target->watchpoints;
1422
1423         /* set any pending watchpoints */
1424         while (watchpoint)
1425         {
1426                 if (!watchpoint->set)
1427                         cortex_m3_set_watchpoint(target, watchpoint);
1428                 watchpoint = watchpoint->next;
1429         }
1430 }
1431
1432 static int cortex_m3_load_core_reg_u32(struct target *target,
1433                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1434 {
1435         int retval;
1436         struct armv7m_common *armv7m = target_to_armv7m(target);
1437         struct adiv5_dap *swjdp = &armv7m->dap;
1438
1439         /* NOTE:  we "know" here that the register identifiers used
1440          * in the v7m header match the Cortex-M3 Debug Core Register
1441          * Selector values for R0..R15, xPSR, MSP, and PSP.
1442          */
1443         switch (num) {
1444         case 0 ... 18:
1445                 /* read a normal core register */
1446                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1447
1448                 if (retval != ERROR_OK)
1449                 {
1450                         LOG_ERROR("JTAG failure %i",retval);
1451                         return ERROR_JTAG_DEVICE_ERROR;
1452                 }
1453                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1454                 break;
1455
1456         case ARMV7M_PRIMASK:
1457         case ARMV7M_BASEPRI:
1458         case ARMV7M_FAULTMASK:
1459         case ARMV7M_CONTROL:
1460                 /* Cortex-M3 packages these four registers as bitfields
1461                  * in one Debug Core register.  So say r0 and r2 docs;
1462                  * it was removed from r1 docs, but still works.
1463                  */
1464                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1465
1466                 switch (num)
1467                 {
1468                         case ARMV7M_PRIMASK:
1469                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1470                                 break;
1471
1472                         case ARMV7M_BASEPRI:
1473                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1474                                 break;
1475
1476                         case ARMV7M_FAULTMASK:
1477                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1478                                 break;
1479
1480                         case ARMV7M_CONTROL:
1481                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1482                                 break;
1483                 }
1484
1485                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1486                 break;
1487
1488         default:
1489                 return ERROR_INVALID_ARGUMENTS;
1490         }
1491
1492         return ERROR_OK;
1493 }
1494
1495 static int cortex_m3_store_core_reg_u32(struct target *target,
1496                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1497 {
1498         int retval;
1499         uint32_t reg;
1500         struct armv7m_common *armv7m = target_to_armv7m(target);
1501         struct adiv5_dap *swjdp = &armv7m->dap;
1502
1503 #ifdef ARMV7_GDB_HACKS
1504         /* If the LR register is being modified, make sure it will put us
1505          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1506          * hack to deal with the fact that gdb will sometimes "forge"
1507          * return addresses, and doesn't set the LSB correctly (i.e., when
1508          * printing expressions containing function calls, it sets LR = 0.)
1509          * Valid exception return codes have bit 0 set too.
1510          */
1511         if (num == ARMV7M_R14)
1512                 value |= 0x01;
1513 #endif
1514
1515         /* NOTE:  we "know" here that the register identifiers used
1516          * in the v7m header match the Cortex-M3 Debug Core Register
1517          * Selector values for R0..R15, xPSR, MSP, and PSP.
1518          */
1519         switch (num) {
1520         case 0 ... 18:
1521                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1522                 if (retval != ERROR_OK)
1523                 {
1524                         struct reg *r;
1525
1526                         LOG_ERROR("JTAG failure %i", retval);
1527                         r = armv7m->core_cache->reg_list + num;
1528                         r->dirty = r->valid;
1529                         return ERROR_JTAG_DEVICE_ERROR;
1530                 }
1531                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1532                 break;
1533
1534         case ARMV7M_PRIMASK:
1535         case ARMV7M_BASEPRI:
1536         case ARMV7M_FAULTMASK:
1537         case ARMV7M_CONTROL:
1538                 /* Cortex-M3 packages these four registers as bitfields
1539                  * in one Debug Core register.  So say r0 and r2 docs;
1540                  * it was removed from r1 docs, but still works.
1541                  */
1542                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1543
1544                 switch (num)
1545                 {
1546                         case ARMV7M_PRIMASK:
1547                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1548                                 break;
1549
1550                         case ARMV7M_BASEPRI:
1551                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1552                                 break;
1553
1554                         case ARMV7M_FAULTMASK:
1555                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1556                                 break;
1557
1558                         case ARMV7M_CONTROL:
1559                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1560                                 break;
1561                 }
1562
1563                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1564
1565                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1566                 break;
1567
1568         default:
1569                 return ERROR_INVALID_ARGUMENTS;
1570         }
1571
1572         return ERROR_OK;
1573 }
1574
1575 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1576                 uint32_t size, uint32_t count, uint8_t *buffer)
1577 {
1578         struct armv7m_common *armv7m = target_to_armv7m(target);
1579         struct adiv5_dap *swjdp = &armv7m->dap;
1580         int retval = ERROR_INVALID_ARGUMENTS;
1581
1582         /* cortex_m3 handles unaligned memory access */
1583         if (count && buffer) {
1584                 switch (size) {
1585                 case 4:
1586                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1587                         break;
1588                 case 2:
1589                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1590                         break;
1591                 case 1:
1592                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1593                         break;
1594                 }
1595         }
1596
1597         return retval;
1598 }
1599
1600 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1601                 uint32_t size, uint32_t count, uint8_t *buffer)
1602 {
1603         struct armv7m_common *armv7m = target_to_armv7m(target);
1604         struct adiv5_dap *swjdp = &armv7m->dap;
1605         int retval = ERROR_INVALID_ARGUMENTS;
1606
1607         if (count && buffer) {
1608                 switch (size) {
1609                 case 4:
1610                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1611                         break;
1612                 case 2:
1613                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1614                         break;
1615                 case 1:
1616                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1617                         break;
1618                 }
1619         }
1620
1621         return retval;
1622 }
1623
1624 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1625                 uint32_t count, uint8_t *buffer)
1626 {
1627         return cortex_m3_write_memory(target, address, 4, count, buffer);
1628 }
1629
1630 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1631                 struct target *target)
1632 {
1633         armv7m_build_reg_cache(target);
1634         return ERROR_OK;
1635 }
1636
1637 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1638  * on r/w if the core is not running, and clear on resume or reset ... or
1639  * at least, in a post_restore_context() method.
1640  */
1641
1642 struct dwt_reg_state {
1643         struct target   *target;
1644         uint32_t        addr;
1645         uint32_t        value;  /* scratch/cache */
1646 };
1647
1648 static int cortex_m3_dwt_get_reg(struct reg *reg)
1649 {
1650         struct dwt_reg_state *state = reg->arch_info;
1651
1652         return target_read_u32(state->target, state->addr, &state->value);
1653 }
1654
1655 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1656 {
1657         struct dwt_reg_state *state = reg->arch_info;
1658
1659         return target_write_u32(state->target, state->addr,
1660                         buf_get_u32(buf, 0, reg->size));
1661 }
1662
1663 struct dwt_reg {
1664         uint32_t        addr;
1665         char            *name;
1666         unsigned        size;
1667 };
1668
1669 static struct dwt_reg dwt_base_regs[] = {
1670         { DWT_CTRL, "dwt_ctrl", 32, },
1671         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1672          * increments while the core is asleep.
1673          */
1674         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1675         /* plus some 8 bit counters, useful for profiling with TPIU */
1676 };
1677
1678 static struct dwt_reg dwt_comp[] = {
1679 #define DWT_COMPARATOR(i) \
1680                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1681                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1682                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1683         DWT_COMPARATOR(0),
1684         DWT_COMPARATOR(1),
1685         DWT_COMPARATOR(2),
1686         DWT_COMPARATOR(3),
1687 #undef DWT_COMPARATOR
1688 };
1689
1690 static const struct reg_arch_type dwt_reg_type = {
1691         .get = cortex_m3_dwt_get_reg,
1692         .set = cortex_m3_dwt_set_reg,
1693 };
1694
1695 static void
1696 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1697 {
1698         struct dwt_reg_state *state;
1699
1700         state = calloc(1, sizeof *state);
1701         if (!state)
1702                 return;
1703         state->addr = d->addr;
1704         state->target = t;
1705
1706         r->name = d->name;
1707         r->size = d->size;
1708         r->value = &state->value;
1709         r->arch_info = state;
1710         r->type = &dwt_reg_type;
1711 }
1712
1713 static void
1714 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1715 {
1716         uint32_t dwtcr;
1717         struct reg_cache *cache;
1718         struct cortex_m3_dwt_comparator *comparator;
1719         int reg, i;
1720
1721         target_read_u32(target, DWT_CTRL, &dwtcr);
1722         if (!dwtcr) {
1723                 LOG_DEBUG("no DWT");
1724                 return;
1725         }
1726
1727         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1728         cm3->dwt_comp_available = cm3->dwt_num_comp;
1729         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1730                         sizeof(struct cortex_m3_dwt_comparator));
1731         if (!cm3->dwt_comparator_list) {
1732 fail0:
1733                 cm3->dwt_num_comp = 0;
1734                 LOG_ERROR("out of mem");
1735                 return;
1736         }
1737
1738         cache = calloc(1, sizeof *cache);
1739         if (!cache) {
1740 fail1:
1741                 free(cm3->dwt_comparator_list);
1742                 goto fail0;
1743         }
1744         cache->name = "cortex-m3 dwt registers";
1745         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1746         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1747         if (!cache->reg_list) {
1748                 free(cache);
1749                 goto fail1;
1750         }
1751
1752         for (reg = 0; reg < 2; reg++)
1753                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1754                                 dwt_base_regs + reg);
1755
1756         comparator = cm3->dwt_comparator_list;
1757         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1758                 int j;
1759
1760                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1761                 for (j = 0; j < 3; j++, reg++)
1762                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1763                                         dwt_comp + 3 * i + j);
1764         }
1765
1766         *register_get_last_cache_p(&target->reg_cache) = cache;
1767         cm3->dwt_cache = cache;
1768
1769         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1770                         dwtcr, cm3->dwt_num_comp,
1771                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1772
1773         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1774          * implement single-address data value watchpoints ... so we
1775          * won't need to check it later, when asked to set one up.
1776          */
1777 }
1778
1779 static int cortex_m3_examine(struct target *target)
1780 {
1781         int retval;
1782         uint32_t cpuid, fpcr;
1783         int i;
1784         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1785         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1786
1787         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1788                 return retval;
1789
1790         if (!target_was_examined(target))
1791         {
1792                 target_set_examined(target);
1793
1794                 /* Read from Device Identification Registers */
1795                 retval = target_read_u32(target, CPUID, &cpuid);
1796                 if (retval != ERROR_OK)
1797                         return retval;
1798
1799                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1800                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1801                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1802                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1803
1804                 /* NOTE: FPB and DWT are both optional. */
1805
1806                 /* Setup FPB */
1807                 target_read_u32(target, FP_CTRL, &fpcr);
1808                 cortex_m3->auto_bp_type = 1;
1809                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1810                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1811                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1812                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1813                 cortex_m3->fpb_enabled = fpcr & 1;
1814                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1815                 {
1816                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1817                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1818                 }
1819                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1820
1821                 /* Setup DWT */
1822                 cortex_m3_dwt_setup(cortex_m3, target);
1823
1824                 /* These hardware breakpoints only work for code in flash! */
1825                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1826                                 target_name(target),
1827                                 cortex_m3->fp_num_code,
1828                                 cortex_m3->dwt_num_comp);
1829         }
1830
1831         return ERROR_OK;
1832 }
1833
1834 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1835 {
1836         uint16_t dcrdr;
1837
1838         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1839         *ctrl = (uint8_t)dcrdr;
1840         *value = (uint8_t)(dcrdr >> 8);
1841
1842         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1843
1844         /* write ack back to software dcc register
1845          * signify we have read data */
1846         if (dcrdr & (1 << 0))
1847         {
1848                 dcrdr = 0;
1849                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1850         }
1851
1852         return ERROR_OK;
1853 }
1854
1855 static int cortex_m3_target_request_data(struct target *target,
1856                 uint32_t size, uint8_t *buffer)
1857 {
1858         struct armv7m_common *armv7m = target_to_armv7m(target);
1859         struct adiv5_dap *swjdp = &armv7m->dap;
1860         uint8_t data;
1861         uint8_t ctrl;
1862         uint32_t i;
1863
1864         for (i = 0; i < (size * 4); i++)
1865         {
1866                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1867                 buffer[i] = data;
1868         }
1869
1870         return ERROR_OK;
1871 }
1872
1873 static int cortex_m3_handle_target_request(void *priv)
1874 {
1875         struct target *target = priv;
1876         if (!target_was_examined(target))
1877                 return ERROR_OK;
1878         struct armv7m_common *armv7m = target_to_armv7m(target);
1879         struct adiv5_dap *swjdp = &armv7m->dap;
1880
1881         if (!target->dbg_msg_enabled)
1882                 return ERROR_OK;
1883
1884         if (target->state == TARGET_RUNNING)
1885         {
1886                 uint8_t data;
1887                 uint8_t ctrl;
1888
1889                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1890
1891                 /* check if we have data */
1892                 if (ctrl & (1 << 0))
1893                 {
1894                         uint32_t request;
1895
1896                         /* we assume target is quick enough */
1897                         request = data;
1898                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1899                         request |= (data << 8);
1900                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1901                         request |= (data << 16);
1902                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1903                         request |= (data << 24);
1904                         target_request(target, request);
1905                 }
1906         }
1907
1908         return ERROR_OK;
1909 }
1910
1911 static int cortex_m3_init_arch_info(struct target *target,
1912                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1913 {
1914         int retval;
1915         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1916
1917         armv7m_init_arch_info(target, armv7m);
1918
1919         /* prepare JTAG information for the new target */
1920         cortex_m3->jtag_info.tap = tap;
1921         cortex_m3->jtag_info.scann_size = 4;
1922
1923         armv7m->arm.dap = &armv7m->dap;
1924
1925         /* Leave (only) generic DAP stuff for debugport_init(); */
1926         armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1927         armv7m->dap.memaccess_tck = 8;
1928         /* Cortex-M3 has 4096 bytes autoincrement range */
1929         armv7m->dap.tar_autoincr_block = (1 << 12);
1930
1931         /* register arch-specific functions */
1932         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1933
1934         armv7m->post_debug_entry = NULL;
1935
1936         armv7m->pre_restore_context = NULL;
1937
1938         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1939         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1940
1941         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1942
1943         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1944         {
1945                 return retval;
1946         }
1947
1948         return ERROR_OK;
1949 }
1950
1951 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1952 {
1953         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1954
1955         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1956         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1957
1958         return ERROR_OK;
1959 }
1960
1961 /*--------------------------------------------------------------------------*/
1962
1963 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1964                 struct cortex_m3_common *cm3)
1965 {
1966         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1967                 command_print(cmd_ctx, "target is not a Cortex-M3");
1968                 return ERROR_TARGET_INVALID;
1969         }
1970         return ERROR_OK;
1971 }
1972
1973 /*
1974  * Only stuff below this line should need to verify that its target
1975  * is a Cortex-M3.  Everything else should have indirected through the
1976  * cortexm3_target structure, which is only used with CM3 targets.
1977  */
1978
1979 static const struct {
1980         char name[10];
1981         unsigned mask;
1982 } vec_ids[] = {
1983         { "hard_err",   VC_HARDERR, },
1984         { "int_err",    VC_INTERR, },
1985         { "bus_err",    VC_BUSERR, },
1986         { "state_err",  VC_STATERR, },
1987         { "chk_err",    VC_CHKERR, },
1988         { "nocp_err",   VC_NOCPERR, },
1989         { "mm_err",     VC_MMERR, },
1990         { "reset",      VC_CORERESET, },
1991 };
1992
1993 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1994 {
1995         struct target *target = get_current_target(CMD_CTX);
1996         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1997         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1998         struct adiv5_dap *swjdp = &armv7m->dap;
1999         uint32_t demcr = 0;
2000         int retval;
2001
2002         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2003         if (retval != ERROR_OK)
2004                 return retval;
2005
2006         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2007         if (retval != ERROR_OK)
2008                 return retval;
2009
2010         if (CMD_ARGC > 0) {
2011                 unsigned catch = 0;
2012
2013                 if (CMD_ARGC == 1) {
2014                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2015                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2016                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2017                                         | VC_MMERR | VC_CORERESET;
2018                                 goto write;
2019                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2020                                 goto write;
2021                         }
2022                 }
2023                 while (CMD_ARGC-- > 0) {
2024                         unsigned i;
2025                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2026                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2027                                         continue;
2028                                 catch |= vec_ids[i].mask;
2029                                 break;
2030                         }
2031                         if (i == ARRAY_SIZE(vec_ids)) {
2032                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2033                                 return ERROR_INVALID_ARGUMENTS;
2034                         }
2035                 }
2036 write:
2037                 /* For now, armv7m->demcr only stores vector catch flags. */
2038                 armv7m->demcr = catch;
2039
2040                 demcr &= ~0xffff;
2041                 demcr |= catch;
2042
2043                 /* write, but don't assume it stuck (why not??) */
2044                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2045                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2046                 if (retval != ERROR_OK)
2047                         return retval;
2048
2049                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2050                  * Otherwise the vector catch hardware could fire when there's
2051                  * no debugger hooked up, causing much confusion...
2052                  */
2053         }
2054
2055         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2056         {
2057                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2058                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2059         }
2060
2061         return ERROR_OK;
2062 }
2063
2064 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2065 {
2066         struct target *target = get_current_target(CMD_CTX);
2067         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2068         int retval;
2069
2070         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2071         if (retval != ERROR_OK)
2072                 return retval;
2073
2074         if (target->state != TARGET_HALTED)
2075         {
2076                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2077                 return ERROR_OK;
2078         }
2079
2080         if (CMD_ARGC > 0)
2081         {
2082                 bool enable;
2083                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2084                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2085                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2086                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2087         }
2088
2089         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2090                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2091
2092         return ERROR_OK;
2093 }
2094
2095 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2096         {
2097                 .name = "maskisr",
2098                 .handler = handle_cortex_m3_mask_interrupts_command,
2099                 .mode = COMMAND_EXEC,
2100                 .help = "mask cortex_m3 interrupts",
2101                 .usage = "['on'|'off']",
2102         },
2103         {
2104                 .name = "vector_catch",
2105                 .handler = handle_cortex_m3_vector_catch_command,
2106                 .mode = COMMAND_EXEC,
2107                 .help = "configure hardware vectors to trigger debug entry",
2108                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2109         },
2110         COMMAND_REGISTRATION_DONE
2111 };
2112 static const struct command_registration cortex_m3_command_handlers[] = {
2113         {
2114                 .chain = armv7m_command_handlers,
2115         },
2116         {
2117                 .name = "cortex_m3",
2118                 .mode = COMMAND_EXEC,
2119                 .help = "Cortex-M3 command group",
2120                 .chain = cortex_m3_exec_command_handlers,
2121         },
2122         COMMAND_REGISTRATION_DONE
2123 };
2124
2125 struct target_type cortexm3_target =
2126 {
2127         .name = "cortex_m3",
2128
2129         .poll = cortex_m3_poll,
2130         .arch_state = armv7m_arch_state,
2131
2132         .target_request_data = cortex_m3_target_request_data,
2133
2134         .halt = cortex_m3_halt,
2135         .resume = cortex_m3_resume,
2136         .step = cortex_m3_step,
2137
2138         .assert_reset = cortex_m3_assert_reset,
2139         .deassert_reset = cortex_m3_deassert_reset,
2140         .soft_reset_halt = cortex_m3_soft_reset_halt,
2141
2142         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2143
2144         .read_memory = cortex_m3_read_memory,
2145         .write_memory = cortex_m3_write_memory,
2146         .bulk_write_memory = cortex_m3_bulk_write_memory,
2147         .checksum_memory = armv7m_checksum_memory,
2148         .blank_check_memory = armv7m_blank_check_memory,
2149
2150         .run_algorithm = armv7m_run_algorithm,
2151
2152         .add_breakpoint = cortex_m3_add_breakpoint,
2153         .remove_breakpoint = cortex_m3_remove_breakpoint,
2154         .add_watchpoint = cortex_m3_add_watchpoint,
2155         .remove_watchpoint = cortex_m3_remove_watchpoint,
2156
2157         .commands = cortex_m3_command_handlers,
2158         .target_create = cortex_m3_target_create,
2159         .init_target = cortex_m3_init_target,
2160         .examine = cortex_m3_examine,
2161 };