1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 /***************************************************************************
22 * CoreSight (Light?) SerialWireJtagDebugPort *
24 * CoreSight™ DAP-Lite TRM, ARM DDI 0316A *
25 * Cortex-M3™ TRM, ARM DDI 0337C *
27 ***************************************************************************/
32 #include "replacements.h"
34 #include "cortex_m3.h"
35 #include "cortex_swjdp.h"
43 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
44 Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
45 result checking until swjdp_end_transaction()
46 This must be done before using or deallocating any return variables.
48 swjdp->trans_mode == TRANS_MODE_ATOMIC
49 All reads and writes to the AHB bus are checked for valid completion, and return values
50 are immediatley available.
54 /***************************************************************************
56 * DPACC and APACC scanchain access through JTAG-DR *
58 ***************************************************************************/
60 /* Scan out and in from target ordered u8 buffers */
61 int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
63 scan_field_t fields[2];
66 jtag_add_end_state(TAP_RTI);
67 arm_jtag_set_instr(jtag_info, instr, NULL);
69 fields[0].device = jtag_info->chain_pos;
70 fields[0].num_bits = 3;
71 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
72 fields[0].out_value = &out_addr_buf;
73 fields[0].out_mask = NULL;
74 fields[0].in_value = ack;
75 fields[0].in_check_value = NULL;
76 fields[0].in_check_mask = NULL;
77 fields[0].in_handler = NULL;
78 fields[0].in_handler_priv = NULL;
80 fields[1].device = jtag_info->chain_pos;
81 fields[1].num_bits = 32;
82 fields[1].out_value = outvalue;
83 fields[1].out_mask = NULL;
84 fields[1].in_value = invalue;
85 fields[1].in_handler = NULL;
86 fields[1].in_handler_priv = NULL;
87 fields[1].in_check_value = NULL;
88 fields[1].in_check_mask = NULL;
90 jtag_add_dr_scan(2, fields, -1, NULL);
95 /* Scan out and in from host ordered u32 variables */
96 int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
98 scan_field_t fields[2];
102 jtag_add_end_state(TAP_RTI);
103 arm_jtag_set_instr(jtag_info, instr, NULL);
105 fields[0].device = jtag_info->chain_pos;
106 fields[0].num_bits = 3;
107 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
108 fields[0].out_value = &out_addr_buf;
109 fields[0].out_mask = NULL;
110 fields[0].in_value = ack;
111 fields[0].in_check_value = NULL;
112 fields[0].in_check_mask = NULL;
113 fields[0].in_handler = NULL;
114 fields[0].in_handler_priv = NULL;
116 fields[1].device = jtag_info->chain_pos;
117 fields[1].num_bits = 32;
118 buf_set_u32(out_value_buf, 0, 32, outvalue);
119 fields[1].out_value = out_value_buf;
120 fields[1].out_mask = NULL;
121 fields[1].in_value = NULL;
124 fields[1].in_handler = arm_jtag_buf_to_u32;
125 fields[1].in_handler_priv = invalue;
129 fields[1].in_handler = NULL;
130 fields[1].in_handler_priv = NULL;
132 fields[1].in_check_value = NULL;
133 fields[1].in_check_mask = NULL;
135 jtag_add_dr_scan(2, fields, -1, NULL);
140 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
141 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
143 swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
144 if ((RnW == DPAP_READ) && (invalue != NULL))
146 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack);
149 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
150 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
152 return swjdp_transaction_endcheck(swjdp);
158 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
161 swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
162 if ((RnW==DPAP_READ) && (invalue != NULL))
164 swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack);
167 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
168 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
170 return swjdp_transaction_endcheck(swjdp);
176 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
181 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
182 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
183 jtag_execute_queue();
185 swjdp->ack = swjdp->ack & 0x7;
187 while (swjdp->ack != 2)
194 WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
196 return ERROR_JTAG_DEVICE_ERROR;
201 WARNING("Invalid ACK in SWJDP transaction");
202 return ERROR_JTAG_DEVICE_ERROR;
205 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
206 jtag_execute_queue();
207 swjdp->ack = swjdp->ack & 0x7;
210 /* Check for STICKYERR and STICKYORUN */
211 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
213 DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
214 /* Check power to debug regions */
215 if ((ctrlstat & 0xf0000000) != 0xf0000000)
217 ahbap_debugport_init(swjdp);
221 u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
223 if (ctrlstat & SSTICKYORUN)
224 ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
226 if (ctrlstat & SSTICKYERR)
227 ERROR("SWJ-DP STICKY ERROR");
229 /* Clear Sticky Error Bits */
230 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
231 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
232 jtag_execute_queue();
234 DEBUG("swjdp: status 0x%x", ctrlstat);
236 /* Can we find out the reason for the error ?? */
237 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
238 ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
239 ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
240 ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
241 ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
243 jtag_execute_queue();
244 return ERROR_JTAG_DEVICE_ERROR;
250 /***************************************************************************
252 * DP and AHB-AP register access through APACC and DPACC *
254 ***************************************************************************/
256 int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
260 buf_set_u32(out_value_buf, 0, 32, value);
261 return scan_inout_check(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
264 int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
266 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
271 int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
274 select = (reg_addr & 0xFF0000F0);
276 if (select != swjdp->dp_select_value)
278 swjdp_write_dpacc(swjdp, select, DP_SELECT);
279 swjdp->dp_select_value = select;
285 int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
287 swjdp_bankselect_apacc(swjdp, reg_addr);
288 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
293 int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
295 swjdp_bankselect_apacc(swjdp, reg_addr);
296 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
300 int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
304 buf_set_u32(out_value_buf, 0, 32, value);
305 swjdp_bankselect_apacc(swjdp, reg_addr);
306 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
311 int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
313 swjdp_bankselect_apacc(swjdp, reg_addr);
314 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
319 /***************************************************************************
321 * AHB-AP access to memory and system registers on AHB bus *
323 ***************************************************************************/
325 int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
327 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
328 if (csw != swjdp->ap_csw_value)
330 //DEBUG("swjdp : Set CSW %x",csw);
331 ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
332 swjdp->ap_csw_value = csw;
334 if (tar != swjdp->ap_tar_value)
336 //DEBUG("swjdp : Set TAR %x",tar);
337 ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
338 swjdp->ap_tar_value = tar;
340 if (csw & CSW_ADDRINC_MASK)
342 /* Do not cache TAR value when autoincrementing */
343 swjdp->ap_tar_value = -1;
348 /*****************************************************************************
350 * ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
352 * Read a u32 value from memory or system register *
353 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
354 * but with less overhead *
355 *****************************************************************************/
356 int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
358 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
360 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
361 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
366 int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
368 ahbap_read_system_u32(swjdp, address, value);
370 return swjdp_transaction_endcheck(swjdp);
373 /*****************************************************************************
375 * ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
377 * Write a u32 value to memory or system register *
379 *****************************************************************************/
380 int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
382 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
384 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
385 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
390 int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
392 ahbap_write_system_u32(swjdp, address, value);
394 return swjdp_transaction_endcheck(swjdp);
397 /*****************************************************************************
399 * ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
401 * Write a buffer in target order (little endian) *
403 *****************************************************************************/
404 int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
407 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
409 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
411 while ((address & 0x3) && (count > 0))
413 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
414 outvalue = (*buffer++) << 8 * (address & 0x3);
415 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
416 swjdp_transaction_endcheck(swjdp);
421 count = count - 4 * wcount;
424 /* Adjust to write blocks within 4K aligned boundaries */
425 blocksize = (0x1000 - (0xFFF & address)) >> 2;
426 if (wcount < blocksize)
428 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
429 for (writecount=0; writecount<blocksize; writecount++)
431 ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
433 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
435 wcount = wcount - blocksize;
436 address = address + 4 * blocksize;
437 buffer = buffer + 4 * blocksize;
445 WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
446 return ERROR_JTAG_DEVICE_ERROR;
452 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
453 outvalue = (*buffer++) << 8 * (address & 0x3);
454 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
455 retval = swjdp_transaction_endcheck(swjdp);
463 int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
466 int retval = ERROR_OK;
468 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
472 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
473 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
474 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
475 retval = swjdp_transaction_endcheck(swjdp);
484 /*****************************************************************************
486 * ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
488 * Read block fast in target order (little endian) into a buffer *
490 *****************************************************************************/
491 int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
494 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
496 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
498 while ((address & 0x3) && (count > 0))
500 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
501 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue);
502 swjdp_transaction_endcheck(swjdp);
503 *buffer++ = (invalue >> 8 * (address & 0x3)) & 0xFF;
508 count = count - 4 * wcount;
511 /* Adjust to read within 4K block boundaries */
512 blocksize = (0x1000 - (0xFFF & address)) >> 2;
513 if (wcount < blocksize)
515 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
516 /* Scan out first read */
517 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
518 for (readcount = 0; readcount < blocksize - 1; readcount++)
520 /* Scan out read instruction and scan in previous value */
521 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
523 /* Scan in last value */
524 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
525 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
527 wcount = wcount - blocksize;
528 address += 4 * blocksize;
529 buffer += 4 * blocksize;
537 WARNING("Block read error address 0x%x, count 0x%x", address, count);
538 return ERROR_JTAG_DEVICE_ERROR;
544 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
546 retval = swjdp_transaction_endcheck(swjdp);
547 *buffer++ = (invalue >> 8 * (address & 0x3)) & 0xFF;
555 int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
558 int retval = ERROR_OK;
560 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
564 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
565 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
566 retval = swjdp_transaction_endcheck(swjdp);
567 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
576 int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 address)
578 int readcount, errorcount = 0;
581 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
585 /* Adjust to read within 4K block boundaries */
586 blocksize = (0x1000 - (0xFFF & address)) >> 2;
587 if (count < blocksize)
589 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
590 for (readcount = 0; readcount < blocksize; readcount++)
592 ahbap_read_reg_u32(swjdp, AHBAP_DRW, buffer + readcount );
594 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
596 count = count - blocksize;
597 address = address + 4 * blocksize;
598 buffer = buffer + blocksize;
606 WARNING("Block read error address 0x%x, count 0x%x", address, count);
607 return ERROR_JTAG_DEVICE_ERROR;
614 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
619 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
621 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
623 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
624 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
625 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
627 /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
628 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
629 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
631 retval = swjdp_transaction_endcheck(swjdp);
632 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
636 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
641 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
643 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
645 /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
646 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
647 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
649 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
650 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
651 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
653 retval = swjdp_transaction_endcheck(swjdp);
654 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
658 int ahbap_debugport_init(swjdp_common_t *swjdp)
660 u32 idreg, romaddr, dummy;
666 swjdp->ap_csw_value = -1;
667 swjdp->ap_tar_value = -1;
668 swjdp->trans_mode = TRANS_MODE_ATOMIC;
669 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
670 swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
671 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
673 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
675 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
676 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
677 jtag_execute_queue();
679 /* Check that we have debug power domains activated */
680 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
682 DEBUG("swjdp: wait CDBGPWRUPACK");
683 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
684 jtag_execute_queue();
688 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
690 DEBUG("swjdp: wait CSYSPWRUPACK");
691 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
692 jtag_execute_queue();
696 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
697 /* With debug power on we can activate OVERRUN checking */
698 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
699 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat , DP_CTRL_STAT);
700 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
702 ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
703 ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
705 DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);