1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * CoreSight (Light?) SerialWireJtagDebugPort *
30 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
31 * Cortex-M3(tm) TRM, ARM DDI 0337C *
33 ***************************************************************************/
38 #include "replacements.h"
40 #include "cortex_m3.h"
41 #include "cortex_swjdp.h"
44 #include "time_support.h"
49 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
50 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
51 * result checking until swjdp_end_transaction()
52 * This must be done before using or deallocating any return variables.
53 * swjdp->trans_mode == TRANS_MODE_ATOMIC
54 * All reads and writes to the AHB bus are checked for valid completion, and return values
55 * are immediatley available.
58 /***************************************************************************
60 * DPACC and APACC scanchain access through JTAG-DR *
62 ***************************************************************************/
64 /* Scan out and in from target ordered u8 buffers */
65 int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
67 scan_field_t fields[2];
70 jtag_add_end_state(TAP_IDLE);
71 arm_jtag_set_instr(jtag_info, instr, NULL);
73 fields[0].tap = jtag_info->tap;
74 fields[0].num_bits = 3;
75 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
76 fields[0].out_value = &out_addr_buf;
77 fields[0].out_mask = NULL;
78 fields[0].in_value = ack;
79 fields[0].in_check_value = NULL;
80 fields[0].in_check_mask = NULL;
81 fields[0].in_handler = NULL;
82 fields[0].in_handler_priv = NULL;
84 fields[1].tap = jtag_info->tap;
85 fields[1].num_bits = 32;
86 fields[1].out_value = outvalue;
87 fields[1].out_mask = NULL;
88 fields[1].in_value = invalue;
89 fields[1].in_handler = NULL;
90 fields[1].in_handler_priv = NULL;
91 fields[1].in_check_value = NULL;
92 fields[1].in_check_mask = NULL;
94 jtag_add_dr_scan(2, fields, TAP_INVALID);
99 /* Scan out and in from host ordered u32 variables */
100 int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
102 scan_field_t fields[2];
106 jtag_add_end_state(TAP_IDLE);
107 arm_jtag_set_instr(jtag_info, instr, NULL);
109 fields[0].tap = jtag_info->tap;
110 fields[0].num_bits = 3;
111 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
112 fields[0].out_value = &out_addr_buf;
113 fields[0].out_mask = NULL;
114 fields[0].in_value = ack;
115 fields[0].in_check_value = NULL;
116 fields[0].in_check_mask = NULL;
117 fields[0].in_handler = NULL;
118 fields[0].in_handler_priv = NULL;
120 fields[1].tap = jtag_info->tap;
121 fields[1].num_bits = 32;
122 buf_set_u32(out_value_buf, 0, 32, outvalue);
123 fields[1].out_value = out_value_buf;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
128 fields[1].in_handler = arm_jtag_buf_to_u32;
129 fields[1].in_handler_priv = invalue;
133 fields[1].in_handler = NULL;
134 fields[1].in_handler_priv = NULL;
136 fields[1].in_check_value = NULL;
137 fields[1].in_check_mask = NULL;
139 jtag_add_dr_scan(2, fields, TAP_INVALID);
144 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
145 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
147 swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
148 if ((RnW == DPAP_READ) && (invalue != NULL))
150 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
153 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
154 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
156 return swjdp_transaction_endcheck(swjdp);
162 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
164 swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
165 if ((RnW==DPAP_READ) && (invalue != NULL))
167 swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
170 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
171 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
173 return swjdp_transaction_endcheck(swjdp);
179 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
184 /* too expensive to call keep_alive() here */
187 /* Danger!!!! BROKEN!!!! */
188 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
189 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
190 R956 introduced the check on return value here and now Michael Schwingen reports
191 that this code no longer works....
193 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
195 if ((retval=jtag_execute_queue())!=ERROR_OK)
197 LOG_ERROR("BUG: Why does this fail the first time????");
199 /* Why??? second time it works??? */
202 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
203 if ((retval=jtag_execute_queue())!=ERROR_OK)
206 swjdp->ack = swjdp->ack & 0x7;
210 long long then=timeval_ms();
211 while (swjdp->ack != 2)
215 if ((timeval_ms()-then) > 1000)
217 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
218 return ERROR_JTAG_DEVICE_ERROR;
223 LOG_WARNING("Invalid ACK in SWJDP transaction");
224 return ERROR_JTAG_DEVICE_ERROR;
227 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
228 if ((retval=jtag_execute_queue())!=ERROR_OK)
230 swjdp->ack = swjdp->ack & 0x7;
234 /* common code path avoids fn to timeval_ms() */
237 /* Check for STICKYERR and STICKYORUN */
238 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
240 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
241 /* Check power to debug regions */
242 if ((ctrlstat & 0xf0000000) != 0xf0000000)
244 ahbap_debugport_init(swjdp);
248 u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
250 /* Print information about last AHBAP access */
251 LOG_ERROR("AHBAP: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
252 if (ctrlstat & SSTICKYORUN)
253 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
255 if (ctrlstat & SSTICKYERR)
256 LOG_ERROR("SWJ-DP STICKY ERROR");
258 /* Clear Sticky Error Bits */
259 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
260 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
261 if ((retval=jtag_execute_queue())!=ERROR_OK)
264 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
266 /* Can we find out the reason for the error ?? */
267 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
268 ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
269 ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
270 ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
271 LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
273 if ((retval=jtag_execute_queue())!=ERROR_OK)
275 return ERROR_JTAG_DEVICE_ERROR;
281 /***************************************************************************
283 * DP and AHB-AP register access through APACC and DPACC *
285 ***************************************************************************/
287 int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
289 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
292 int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
294 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
297 int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
300 select = (reg_addr & 0xFF0000F0);
302 if (select != swjdp->dp_select_value)
304 swjdp_write_dpacc(swjdp, select, DP_SELECT);
305 swjdp->dp_select_value = select;
311 int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
313 swjdp_bankselect_apacc(swjdp, reg_addr);
314 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
319 int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
321 swjdp_bankselect_apacc(swjdp, reg_addr);
322 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
326 int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
330 buf_set_u32(out_value_buf, 0, 32, value);
331 swjdp_bankselect_apacc(swjdp, reg_addr);
332 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
337 int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
339 swjdp_bankselect_apacc(swjdp, reg_addr);
340 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
345 /***************************************************************************
347 * AHB-AP access to memory and system registers on AHB bus *
349 ***************************************************************************/
351 int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
353 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
354 if (csw != swjdp->ap_csw_value)
356 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
357 ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
358 swjdp->ap_csw_value = csw;
360 if (tar != swjdp->ap_tar_value)
362 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
363 ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
364 swjdp->ap_tar_value = tar;
366 if (csw & CSW_ADDRINC_MASK)
368 /* Do not cache TAR value when autoincrementing */
369 swjdp->ap_tar_value = -1;
374 /*****************************************************************************
376 * ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
378 * Read a u32 value from memory or system register *
379 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
380 * but with less overhead *
381 *****************************************************************************/
382 int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
384 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
386 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
387 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
392 int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
394 ahbap_read_system_u32(swjdp, address, value);
396 return swjdp_transaction_endcheck(swjdp);
399 /*****************************************************************************
401 * ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
403 * Write a u32 value to memory or system register *
405 *****************************************************************************/
406 int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
408 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
410 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
411 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
416 int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
418 ahbap_write_system_u32(swjdp, address, value);
420 return swjdp_transaction_endcheck(swjdp);
423 /*****************************************************************************
425 * ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
427 * Write a buffer in target order (little endian) *
429 *****************************************************************************/
430 int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
433 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
435 u8* pBuffer = buffer;
437 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
442 /* if we have an unaligned access - reorder data */
445 for (writecount = 0; writecount < count; writecount++)
448 outvalue = *((u32*)pBuffer);
450 for (i = 0; i < 4; i++ )
452 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
462 /* Adjust to write blocks within 4K aligned boundaries */
463 blocksize = (0x1000 - (0xFFF & address)) >> 2;
464 if (wcount < blocksize)
467 /* handle unaligned data at 4k boundary */
471 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
473 for (writecount = 0; writecount < blocksize; writecount++)
475 ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
478 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
480 wcount = wcount - blocksize;
481 address = address + 4 * blocksize;
482 buffer = buffer + 4 * blocksize;
491 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
492 return ERROR_JTAG_DEVICE_ERROR;
499 int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
502 int retval = ERROR_OK;
503 int wcount, blocksize, writecount, i;
505 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
513 /* Adjust to read within 4K block boundaries */
514 blocksize = (0x1000 - (0xFFF & address)) >> 1;
516 if (wcount < blocksize)
519 /* handle unaligned data at 4k boundary */
523 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
524 writecount = blocksize;
528 nbytes = MIN((writecount << 1), 4);
532 if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
534 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
535 return ERROR_JTAG_DEVICE_ERROR;
538 address += nbytes >> 1;
542 outvalue = *((u32*)buffer);
544 for (i = 0; i < nbytes; i++ )
546 *((u8*)buffer + (address & 0x3)) = outvalue;
551 outvalue = *((u32*)buffer);
552 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
553 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
555 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
556 return ERROR_JTAG_DEVICE_ERROR;
560 buffer += nbytes >> 1;
561 writecount -= nbytes >> 1;
563 } while (writecount);
570 int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
573 int retval = ERROR_OK;
576 return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
578 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
582 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
583 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
584 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
585 retval = swjdp_transaction_endcheck(swjdp);
594 int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
597 int retval = ERROR_OK;
598 int wcount, blocksize, writecount, i;
600 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
608 /* Adjust to read within 4K block boundaries */
609 blocksize = (0x1000 - (0xFFF & address));
611 if (wcount < blocksize)
614 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
615 writecount = blocksize;
619 nbytes = MIN(writecount, 4);
623 if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
625 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
626 return ERROR_JTAG_DEVICE_ERROR;
633 outvalue = *((u32*)buffer);
635 for (i = 0; i < nbytes; i++ )
637 *((u8*)buffer + (address & 0x3)) = outvalue;
642 outvalue = *((u32*)buffer);
643 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
644 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
646 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
647 return ERROR_JTAG_DEVICE_ERROR;
652 writecount -= nbytes;
654 } while (writecount);
661 int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
664 int retval = ERROR_OK;
667 return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
669 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
673 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
674 outvalue = *((u8*)buffer) << 8 * (address & 0x3);
675 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
676 retval = swjdp_transaction_endcheck(swjdp);
685 /*********************************************************************************
687 * ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
689 * Read block fast in target order (little endian) into a buffer *
691 **********************************************************************************/
692 int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
694 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
696 u8* pBuffer = buffer;
698 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
705 /* Adjust to read within 4K block boundaries */
706 blocksize = (0x1000 - (0xFFF & address)) >> 2;
707 if (wcount < blocksize)
710 /* handle unaligned data at 4k boundary */
714 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
716 /* Scan out first read */
717 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
718 for (readcount = 0; readcount < blocksize - 1; readcount++)
720 /* Scan out read instruction and scan in previous value */
721 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
724 /* Scan in last value */
725 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
726 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
728 wcount = wcount - blocksize;
729 address += 4 * blocksize;
730 buffer += 4 * blocksize;
739 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
740 return ERROR_JTAG_DEVICE_ERROR;
744 /* if we have an unaligned access - reorder data */
747 for (readcount = 0; readcount < count; readcount++)
750 u32 data = *((u32*)pBuffer);
752 for (i = 0; i < 4; i++ )
754 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
764 int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
767 int retval = ERROR_OK;
768 int wcount, blocksize, readcount, i;
770 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
778 /* Adjust to read within 4K block boundaries */
779 blocksize = (0x1000 - (0xFFF & address)) >> 1;
780 if (wcount < blocksize)
783 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
785 /* handle unaligned data at 4k boundary */
788 readcount = blocksize;
792 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
793 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
795 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
796 return ERROR_JTAG_DEVICE_ERROR;
799 nbytes = MIN((readcount << 1), 4);
801 for (i = 0; i < nbytes; i++ )
803 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
808 readcount -= (nbytes >> 1);
816 int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
819 int retval = ERROR_OK;
822 return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
824 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
828 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
829 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
830 retval = swjdp_transaction_endcheck(swjdp);
833 for (i = 0; i < 2; i++ )
835 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
842 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
852 int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
855 int retval = ERROR_OK;
856 int wcount, blocksize, readcount, i;
858 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
866 /* Adjust to read within 4K block boundaries */
867 blocksize = (0x1000 - (0xFFF & address));
869 if (wcount < blocksize)
872 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
873 readcount = blocksize;
877 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
878 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
880 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
881 return ERROR_JTAG_DEVICE_ERROR;
884 nbytes = MIN(readcount, 4);
886 for (i = 0; i < nbytes; i++ )
888 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
901 int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
904 int retval = ERROR_OK;
907 return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
909 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
913 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
914 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
915 retval = swjdp_transaction_endcheck(swjdp);
916 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
925 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
930 /* because the DCB_DCRDR is used for the emulated dcc channel
931 * we gave to save/restore the DCB_DCRDR when used */
933 ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
935 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
937 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
938 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
939 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
941 /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
942 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
943 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
945 ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
946 retval = swjdp_transaction_endcheck(swjdp);
950 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
955 /* because the DCB_DCRDR is used for the emulated dcc channel
956 * we gave to save/restore the DCB_DCRDR when used */
958 ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
960 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
962 /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
963 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
964 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
966 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
967 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
968 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
970 ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
971 retval = swjdp_transaction_endcheck(swjdp);
975 int ahbap_debugport_init(swjdp_common_t *swjdp)
977 u32 idreg, romaddr, dummy;
984 swjdp->ap_csw_value = -1;
985 swjdp->ap_tar_value = -1;
986 swjdp->trans_mode = TRANS_MODE_ATOMIC;
987 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
988 swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
989 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
991 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
993 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
994 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
995 if ((retval=jtag_execute_queue())!=ERROR_OK)
998 /* Check that we have debug power domains activated */
999 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1001 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1002 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
1003 if ((retval=jtag_execute_queue())!=ERROR_OK)
1008 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1010 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1011 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
1012 if ((retval=jtag_execute_queue())!=ERROR_OK)
1017 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1018 /* With debug power on we can activate OVERRUN checking */
1019 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1020 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1021 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1023 ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
1024 ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
1026 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);