1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 /***************************************************************************
22 * CoreSight (Light?) SerialWireJtagDebugPort *
24 * CoreSightâ„¢ DAP-Lite TRM, ARM DDI 0316A *
25 * Cortex-M3â„¢ TRM, ARM DDI 0337C *
27 ***************************************************************************/
32 #include "replacements.h"
34 #include "cortex_m3.h"
35 #include "cortex_swjdp.h"
42 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
43 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
44 * result checking until swjdp_end_transaction()
45 * This must be done before using or deallocating any return variables.
46 * swjdp->trans_mode == TRANS_MODE_ATOMIC
47 * All reads and writes to the AHB bus are checked for valid completion, and return values
48 * are immediatley available.
51 /***************************************************************************
53 * DPACC and APACC scanchain access through JTAG-DR *
55 ***************************************************************************/
57 /* Scan out and in from target ordered u8 buffers */
58 int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
60 scan_field_t fields[2];
63 jtag_add_end_state(TAP_RTI);
64 arm_jtag_set_instr(jtag_info, instr, NULL);
66 fields[0].device = jtag_info->chain_pos;
67 fields[0].num_bits = 3;
68 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
69 fields[0].out_value = &out_addr_buf;
70 fields[0].out_mask = NULL;
71 fields[0].in_value = ack;
72 fields[0].in_check_value = NULL;
73 fields[0].in_check_mask = NULL;
74 fields[0].in_handler = NULL;
75 fields[0].in_handler_priv = NULL;
77 fields[1].device = jtag_info->chain_pos;
78 fields[1].num_bits = 32;
79 fields[1].out_value = outvalue;
80 fields[1].out_mask = NULL;
81 fields[1].in_value = invalue;
82 fields[1].in_handler = NULL;
83 fields[1].in_handler_priv = NULL;
84 fields[1].in_check_value = NULL;
85 fields[1].in_check_mask = NULL;
87 jtag_add_dr_scan(2, fields, -1);
92 /* Scan out and in from host ordered u32 variables */
93 int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
95 scan_field_t fields[2];
99 jtag_add_end_state(TAP_RTI);
100 arm_jtag_set_instr(jtag_info, instr, NULL);
102 fields[0].device = jtag_info->chain_pos;
103 fields[0].num_bits = 3;
104 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
105 fields[0].out_value = &out_addr_buf;
106 fields[0].out_mask = NULL;
107 fields[0].in_value = ack;
108 fields[0].in_check_value = NULL;
109 fields[0].in_check_mask = NULL;
110 fields[0].in_handler = NULL;
111 fields[0].in_handler_priv = NULL;
113 fields[1].device = jtag_info->chain_pos;
114 fields[1].num_bits = 32;
115 buf_set_u32(out_value_buf, 0, 32, outvalue);
116 fields[1].out_value = out_value_buf;
117 fields[1].out_mask = NULL;
118 fields[1].in_value = NULL;
121 fields[1].in_handler = arm_jtag_buf_to_u32;
122 fields[1].in_handler_priv = invalue;
126 fields[1].in_handler = NULL;
127 fields[1].in_handler_priv = NULL;
129 fields[1].in_check_value = NULL;
130 fields[1].in_check_mask = NULL;
132 jtag_add_dr_scan(2, fields, -1);
137 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
138 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
140 swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
141 if ((RnW == DPAP_READ) && (invalue != NULL))
143 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
146 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
147 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
149 return swjdp_transaction_endcheck(swjdp);
155 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
157 swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
158 if ((RnW==DPAP_READ) && (invalue != NULL))
160 swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
163 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
164 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
166 return swjdp_transaction_endcheck(swjdp);
172 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
180 /* Danger!!!! BROKEN!!!! */
181 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
182 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
183 R956 introduced the check on return value here and now Michael Schwingen reports
184 that this code no longer works....
186 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
188 if ((retval=jtag_execute_queue())!=ERROR_OK)
190 LOG_ERROR("BUG: Why does this fail the first time????");
192 /* Why??? second time it works??? */
193 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
194 if ((retval=jtag_execute_queue())!=ERROR_OK)
197 swjdp->ack = swjdp->ack & 0x7;
199 while (swjdp->ack != 2)
206 LOG_WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
207 return ERROR_JTAG_DEVICE_ERROR;
212 LOG_WARNING("Invalid ACK in SWJDP transaction");
213 return ERROR_JTAG_DEVICE_ERROR;
216 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
217 if ((retval=jtag_execute_queue())!=ERROR_OK)
219 swjdp->ack = swjdp->ack & 0x7;
222 /* Check for STICKYERR and STICKYORUN */
223 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
225 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
226 /* Check power to debug regions */
227 if ((ctrlstat & 0xf0000000) != 0xf0000000)
229 ahbap_debugport_init(swjdp);
233 u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
235 if (ctrlstat & SSTICKYORUN)
236 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
238 if (ctrlstat & SSTICKYERR)
239 LOG_ERROR("SWJ-DP STICKY ERROR");
241 /* Clear Sticky Error Bits */
242 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
243 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
244 if ((retval=jtag_execute_queue())!=ERROR_OK)
247 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
249 /* Can we find out the reason for the error ?? */
250 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
251 ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
252 ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
253 ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
254 LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
256 if ((retval=jtag_execute_queue())!=ERROR_OK)
258 return ERROR_JTAG_DEVICE_ERROR;
264 /***************************************************************************
266 * DP and AHB-AP register access through APACC and DPACC *
268 ***************************************************************************/
270 int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
272 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
275 int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
277 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
280 int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
283 select = (reg_addr & 0xFF0000F0);
285 if (select != swjdp->dp_select_value)
287 swjdp_write_dpacc(swjdp, select, DP_SELECT);
288 swjdp->dp_select_value = select;
294 int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
296 swjdp_bankselect_apacc(swjdp, reg_addr);
297 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
302 int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
304 swjdp_bankselect_apacc(swjdp, reg_addr);
305 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
309 int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
313 buf_set_u32(out_value_buf, 0, 32, value);
314 swjdp_bankselect_apacc(swjdp, reg_addr);
315 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
320 int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
322 swjdp_bankselect_apacc(swjdp, reg_addr);
323 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
328 /***************************************************************************
330 * AHB-AP access to memory and system registers on AHB bus *
332 ***************************************************************************/
334 int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
336 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
337 if (csw != swjdp->ap_csw_value)
339 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
340 ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
341 swjdp->ap_csw_value = csw;
343 if (tar != swjdp->ap_tar_value)
345 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
346 ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
347 swjdp->ap_tar_value = tar;
349 if (csw & CSW_ADDRINC_MASK)
351 /* Do not cache TAR value when autoincrementing */
352 swjdp->ap_tar_value = -1;
357 /*****************************************************************************
359 * ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
361 * Read a u32 value from memory or system register *
362 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
363 * but with less overhead *
364 *****************************************************************************/
365 int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
367 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
369 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
370 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
375 int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
377 ahbap_read_system_u32(swjdp, address, value);
379 return swjdp_transaction_endcheck(swjdp);
382 /*****************************************************************************
384 * ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
386 * Write a u32 value to memory or system register *
388 *****************************************************************************/
389 int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
391 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
393 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
394 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
399 int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
401 ahbap_write_system_u32(swjdp, address, value);
403 return swjdp_transaction_endcheck(swjdp);
406 /*****************************************************************************
408 * ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
410 * Write a buffer in target order (little endian) *
412 *****************************************************************************/
413 int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
416 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
418 u8* pBuffer = buffer;
420 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
425 /* if we have an unaligned access - reorder data */
428 for (writecount = 0; writecount < count; writecount++)
431 outvalue = *((u32*)pBuffer);
433 for (i = 0; i < 4; i++ )
435 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
445 /* Adjust to write blocks within 4K aligned boundaries */
446 blocksize = (0x1000 - (0xFFF & address)) >> 2;
447 if (wcount < blocksize)
450 /* handle unaligned data at 4k boundary */
454 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
456 for (writecount = 0; writecount < blocksize; writecount++)
458 ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
461 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
463 wcount = wcount - blocksize;
464 address = address + 4 * blocksize;
465 buffer = buffer + 4 * blocksize;
474 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
475 return ERROR_JTAG_DEVICE_ERROR;
482 int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
485 int retval = ERROR_OK;
486 int wcount, blocksize, writecount, i;
488 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
496 /* Adjust to read within 4K block boundaries */
497 blocksize = (0x1000 - (0xFFF & address)) >> 1;
499 if (wcount < blocksize)
502 /* handle unaligned data at 4k boundary */
506 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
507 writecount = blocksize;
511 nbytes = MIN((writecount << 1), 4);
515 if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
517 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
518 return ERROR_JTAG_DEVICE_ERROR;
521 address += nbytes >> 1;
525 outvalue = *((u32*)buffer);
527 for (i = 0; i < nbytes; i++ )
529 *((u8*)buffer + (address & 0x3)) = outvalue;
534 outvalue = *((u32*)buffer);
535 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
536 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
538 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
539 return ERROR_JTAG_DEVICE_ERROR;
543 buffer += nbytes >> 1;
544 writecount -= nbytes >> 1;
546 } while (writecount);
553 int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
556 int retval = ERROR_OK;
559 return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
561 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
565 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
566 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
567 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
568 retval = swjdp_transaction_endcheck(swjdp);
577 int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
580 int retval = ERROR_OK;
581 int wcount, blocksize, writecount, i;
583 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
591 /* Adjust to read within 4K block boundaries */
592 blocksize = (0x1000 - (0xFFF & address));
594 if (wcount < blocksize)
597 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
598 writecount = blocksize;
602 nbytes = MIN(writecount, 4);
606 if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
608 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
609 return ERROR_JTAG_DEVICE_ERROR;
616 outvalue = *((u32*)buffer);
618 for (i = 0; i < nbytes; i++ )
620 *((u8*)buffer + (address & 0x3)) = outvalue;
625 outvalue = *((u32*)buffer);
626 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
627 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
629 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
630 return ERROR_JTAG_DEVICE_ERROR;
635 writecount -= nbytes;
637 } while (writecount);
644 int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
647 int retval = ERROR_OK;
650 return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
652 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
656 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
657 outvalue = *((u8*)buffer) << 8 * (address & 0x3);
658 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
659 retval = swjdp_transaction_endcheck(swjdp);
668 /*********************************************************************************
670 * ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
672 * Read block fast in target order (little endian) into a buffer *
674 **********************************************************************************/
675 int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
677 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
679 u8* pBuffer = buffer;
681 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
688 /* Adjust to read within 4K block boundaries */
689 blocksize = (0x1000 - (0xFFF & address)) >> 2;
690 if (wcount < blocksize)
693 /* handle unaligned data at 4k boundary */
697 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
699 /* Scan out first read */
700 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
701 for (readcount = 0; readcount < blocksize - 1; readcount++)
703 /* Scan out read instruction and scan in previous value */
704 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
707 /* Scan in last value */
708 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
709 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
711 wcount = wcount - blocksize;
712 address += 4 * blocksize;
713 buffer += 4 * blocksize;
722 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
723 return ERROR_JTAG_DEVICE_ERROR;
727 /* if we have an unaligned access - reorder data */
730 for (readcount = 0; readcount < count; readcount++)
733 u32 data = *((u32*)pBuffer);
735 for (i = 0; i < 4; i++ )
737 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
747 int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
750 int retval = ERROR_OK;
751 int wcount, blocksize, readcount, i;
753 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
761 /* Adjust to read within 4K block boundaries */
762 blocksize = (0x1000 - (0xFFF & address)) >> 1;
763 if (wcount < blocksize)
766 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
768 /* handle unaligned data at 4k boundary */
771 readcount = blocksize;
775 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
776 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
778 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
779 return ERROR_JTAG_DEVICE_ERROR;
782 nbytes = MIN((readcount << 1), 4);
784 for (i = 0; i < nbytes; i++ )
786 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
791 readcount -= (nbytes >> 1);
799 int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
802 int retval = ERROR_OK;
805 return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
807 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
811 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
812 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
813 retval = swjdp_transaction_endcheck(swjdp);
816 for (i = 0; i < 2; i++ )
818 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
825 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
835 int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
838 int retval = ERROR_OK;
839 int wcount, blocksize, readcount, i;
841 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
849 /* Adjust to read within 4K block boundaries */
850 blocksize = (0x1000 - (0xFFF & address));
852 if (wcount < blocksize)
855 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
856 readcount = blocksize;
860 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
861 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
863 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
864 return ERROR_JTAG_DEVICE_ERROR;
867 nbytes = MIN(readcount, 4);
869 for (i = 0; i < nbytes; i++ )
871 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
884 int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
887 int retval = ERROR_OK;
890 return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
892 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
896 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
897 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
898 retval = swjdp_transaction_endcheck(swjdp);
899 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
908 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
913 /* because the DCB_DCRDR is used for the emulated dcc channel
914 * we gave to save/restore the DCB_DCRDR when used */
916 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
918 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
920 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
921 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
922 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
924 /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
925 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
926 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
928 retval = swjdp_transaction_endcheck(swjdp);
929 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
933 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
938 /* because the DCB_DCRDR is used for the emulated dcc channel
939 * we gave to save/restore the DCB_DCRDR when used */
941 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
943 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
945 /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
946 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
947 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
949 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
950 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
951 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
953 retval = swjdp_transaction_endcheck(swjdp);
954 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
958 int ahbap_debugport_init(swjdp_common_t *swjdp)
960 u32 idreg, romaddr, dummy;
967 swjdp->ap_csw_value = -1;
968 swjdp->ap_tar_value = -1;
969 swjdp->trans_mode = TRANS_MODE_ATOMIC;
970 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
971 swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
972 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
974 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
976 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
977 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
978 if ((retval=jtag_execute_queue())!=ERROR_OK)
981 /* Check that we have debug power domains activated */
982 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
984 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
985 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
986 if ((retval=jtag_execute_queue())!=ERROR_OK)
991 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
993 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
994 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
995 if ((retval=jtag_execute_queue())!=ERROR_OK)
1000 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1001 /* With debug power on we can activate OVERRUN checking */
1002 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1003 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1004 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1006 ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
1007 ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
1009 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);