1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "embeddedice.h"
27 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
47 int embeddedice_reg_arch_info[] =
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
55 char* embeddedice_reg_list[] =
67 "watch 0 control value",
68 "watch 0 control mask",
74 "watch 1 control value",
75 "watch 1 control mask",
80 int embeddedice_reg_arch_type = -1;
82 int embeddedice_get_reg(reg_t *reg);
83 int embeddedice_set_reg(reg_t *reg, u32 value);
84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
86 int embeddedice_write_reg(reg_t *reg, u32 value);
87 int embeddedice_read_reg(reg_t *reg);
89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
91 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
92 reg_t *reg_list = NULL;
93 embeddedice_reg_t *arch_info = NULL;
94 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
99 /* register a register arch-type for EmbeddedICE registers only once */
100 if (embeddedice_reg_arch_type == -1)
101 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
103 if (arm7_9->has_vector_catch)
108 /* the actual registers are kept in two arrays */
109 reg_list = calloc(num_regs, sizeof(reg_t));
110 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
112 /* fill in values for the reg cache */
113 reg_cache->name = "EmbeddedICE registers";
114 reg_cache->next = NULL;
115 reg_cache->reg_list = reg_list;
116 reg_cache->num_regs = num_regs;
118 /* set up registers */
119 for (i = 0; i < num_regs; i++)
121 reg_list[i].name = embeddedice_reg_list[i];
122 reg_list[i].size = 32;
123 reg_list[i].dirty = 0;
124 reg_list[i].valid = 0;
125 reg_list[i].bitfield_desc = NULL;
126 reg_list[i].num_bitfields = 0;
127 reg_list[i].value = calloc(1, 4);
128 reg_list[i].arch_info = &arch_info[i];
129 reg_list[i].arch_type = embeddedice_reg_arch_type;
130 arch_info[i].addr = embeddedice_reg_arch_info[i];
131 arch_info[i].jtag_info = jtag_info;
134 /* identify EmbeddedICE version by reading DCC control register */
135 embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
136 jtag_execute_queue();
138 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
140 switch (eice_version)
143 reg_list[EICE_DBG_CTRL].size = 3;
144 reg_list[EICE_DBG_STAT].size = 5;
147 reg_list[EICE_DBG_CTRL].size = 4;
148 reg_list[EICE_DBG_STAT].size = 5;
149 arm7_9->has_single_step = 1;
152 ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
153 reg_list[EICE_DBG_CTRL].size = 6;
154 reg_list[EICE_DBG_STAT].size = 5;
155 arm7_9->has_single_step = 1;
156 arm7_9->has_monitor_mode = 1;
159 reg_list[EICE_DBG_CTRL].size = 6;
160 reg_list[EICE_DBG_STAT].size = 5;
161 arm7_9->has_monitor_mode = 1;
164 reg_list[EICE_DBG_CTRL].size = 6;
165 reg_list[EICE_DBG_STAT].size = 5;
166 arm7_9->has_single_step = 1;
167 arm7_9->has_monitor_mode = 1;
170 reg_list[EICE_DBG_CTRL].size = 6;
171 reg_list[EICE_DBG_STAT].size = 10;
172 arm7_9->has_monitor_mode = 1;
175 WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
176 reg_list[EICE_DBG_CTRL].size = 6;
177 reg_list[EICE_DBG_STAT].size = 5;
178 arm7_9->has_monitor_mode = 1;
181 ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
184 /* explicitly disable monitor mode */
185 if (arm7_9->has_monitor_mode)
187 embeddedice_read_reg(®_list[EICE_DBG_CTRL]);
188 jtag_execute_queue();
189 buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
190 embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
196 int embeddedice_get_reg(reg_t *reg)
198 if (embeddedice_read_reg(reg) != ERROR_OK)
200 ERROR("BUG: error scheduling EmbeddedICE register read");
204 if (jtag_execute_queue() != ERROR_OK)
206 ERROR("register read failed");
212 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
214 embeddedice_reg_t *ice_reg = reg->arch_info;
215 u8 reg_addr = ice_reg->addr & 0x1f;
216 scan_field_t fields[3];
220 jtag_add_end_state(TAP_RTI);
221 arm_jtag_scann(ice_reg->jtag_info, 0x2);
223 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
225 fields[0].device = ice_reg->jtag_info->chain_pos;
226 fields[0].num_bits = 32;
227 fields[0].out_value = reg->value;
228 fields[0].out_mask = NULL;
229 fields[0].in_value = NULL;
230 fields[0].in_check_value = NULL;
231 fields[0].in_check_mask = NULL;
232 fields[0].in_handler = NULL;
233 fields[0].in_handler_priv = NULL;
235 fields[1].device = ice_reg->jtag_info->chain_pos;
236 fields[1].num_bits = 5;
237 fields[1].out_value = field1_out;
238 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
239 fields[1].out_mask = NULL;
240 fields[1].in_value = NULL;
241 fields[1].in_check_value = NULL;
242 fields[1].in_check_mask = NULL;
243 fields[1].in_handler = NULL;
244 fields[1].in_handler_priv = NULL;
246 fields[2].device = ice_reg->jtag_info->chain_pos;
247 fields[2].num_bits = 1;
248 fields[2].out_value = field2_out;
249 buf_set_u32(fields[2].out_value, 0, 1, 0);
250 fields[2].out_mask = NULL;
251 fields[2].in_value = NULL;
252 fields[2].in_check_value = NULL;
253 fields[2].in_check_mask = NULL;
254 fields[2].in_handler = NULL;
255 fields[2].in_handler_priv = NULL;
257 jtag_add_dr_scan(3, fields, -1);
259 fields[0].in_value = reg->value;
260 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
262 /* when reading the DCC data register, leaving the address field set to
263 * EICE_COMMS_DATA would read the register twice
264 * reading the control register is safe
266 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
268 jtag_add_dr_scan(3, fields, -1);
273 /* receive <size> words of 32 bit from the DCC
274 * we pretend the target is always going to be fast enough
275 * (relative to the JTAG clock), so we don't need to handshake
277 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
279 scan_field_t fields[3];
283 jtag_add_end_state(TAP_RTI);
284 arm_jtag_scann(jtag_info, 0x2);
285 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
287 fields[0].device = jtag_info->chain_pos;
288 fields[0].num_bits = 32;
289 fields[0].out_value = NULL;
290 fields[0].out_mask = NULL;
291 fields[0].in_value = NULL;
292 fields[0].in_check_value = NULL;
293 fields[0].in_check_mask = NULL;
294 fields[0].in_handler = NULL;
295 fields[0].in_handler_priv = NULL;
297 fields[1].device = jtag_info->chain_pos;
298 fields[1].num_bits = 5;
299 fields[1].out_value = field1_out;
300 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
301 fields[1].out_mask = NULL;
302 fields[1].in_value = NULL;
303 fields[1].in_check_value = NULL;
304 fields[1].in_check_mask = NULL;
305 fields[1].in_handler = NULL;
306 fields[1].in_handler_priv = NULL;
308 fields[2].device = jtag_info->chain_pos;
309 fields[2].num_bits = 1;
310 fields[2].out_value = field2_out;
311 buf_set_u32(fields[2].out_value, 0, 1, 0);
312 fields[2].out_mask = NULL;
313 fields[2].in_value = NULL;
314 fields[2].in_check_value = NULL;
315 fields[2].in_check_mask = NULL;
316 fields[2].in_handler = NULL;
317 fields[2].in_handler_priv = NULL;
319 jtag_add_dr_scan(3, fields, -1);
323 /* when reading the last item, set the register address to the DCC control reg,
324 * to avoid reading additional data from the DCC data reg
327 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
329 fields[0].in_handler = arm_jtag_buf_to_u32;
330 fields[0].in_handler_priv = data;
331 jtag_add_dr_scan(3, fields, -1);
337 return jtag_execute_queue();
340 int embeddedice_read_reg(reg_t *reg)
342 return embeddedice_read_reg_w_check(reg, NULL, NULL);
345 int embeddedice_set_reg(reg_t *reg, u32 value)
347 if (embeddedice_write_reg(reg, value) != ERROR_OK)
349 ERROR("BUG: error scheduling EmbeddedICE register write");
353 buf_set_u32(reg->value, 0, reg->size, value);
360 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
362 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
364 if (jtag_execute_queue() != ERROR_OK)
366 ERROR("register write failed");
372 int embeddedice_write_reg(reg_t *reg, u32 value)
374 embeddedice_reg_t *ice_reg = reg->arch_info;
376 DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
378 jtag_add_end_state(TAP_RTI);
379 arm_jtag_scann(ice_reg->jtag_info, 0x2);
381 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
383 u8 reg_addr = ice_reg->addr & 0x1f;
384 embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
389 int embeddedice_store_reg(reg_t *reg)
391 return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
394 /* send <size> words of 32 bit to the DCC
395 * we pretend the target is always going to be fast enough
396 * (relative to the JTAG clock), so we don't need to handshake
398 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
400 scan_field_t fields[3];
405 jtag_add_end_state(TAP_RTI);
406 arm_jtag_scann(jtag_info, 0x2);
407 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
409 fields[0].device = jtag_info->chain_pos;
410 fields[0].num_bits = 32;
411 fields[0].out_value = field0_out;
412 fields[0].out_mask = NULL;
413 fields[0].in_value = NULL;
414 fields[0].in_check_value = NULL;
415 fields[0].in_check_mask = NULL;
416 fields[0].in_handler = NULL;
417 fields[0].in_handler_priv = NULL;
419 fields[1].device = jtag_info->chain_pos;
420 fields[1].num_bits = 5;
421 fields[1].out_value = field1_out;
422 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
423 fields[1].out_mask = NULL;
424 fields[1].in_value = NULL;
425 fields[1].in_check_value = NULL;
426 fields[1].in_check_mask = NULL;
427 fields[1].in_handler = NULL;
428 fields[1].in_handler_priv = NULL;
430 fields[2].device = jtag_info->chain_pos;
431 fields[2].num_bits = 1;
432 fields[2].out_value = field2_out;
433 buf_set_u32(fields[2].out_value, 0, 1, 1);
434 fields[2].out_mask = NULL;
435 fields[2].in_value = NULL;
436 fields[2].in_check_value = NULL;
437 fields[2].in_check_mask = NULL;
438 fields[2].in_handler = NULL;
439 fields[2].in_handler_priv = NULL;
443 buf_set_u32(fields[0].out_value, 0, 32, *data);
444 jtag_add_dr_scan(3, fields, -1);
450 /* call to jtag_execute_queue() intentionally omitted */
454 /* wait for DCC control register R/W handshake bit to become active
456 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
458 scan_field_t fields[3];
467 if (hsbit == EICE_COMM_CTRL_WBIT)
469 else if (hsbit == EICE_COMM_CTRL_RBIT)
472 return ERROR_INVALID_ARGUMENTS;
474 jtag_add_end_state(TAP_RTI);
475 arm_jtag_scann(jtag_info, 0x2);
476 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
478 fields[0].device = jtag_info->chain_pos;
479 fields[0].num_bits = 32;
480 fields[0].out_value = NULL;
481 fields[0].out_mask = NULL;
482 fields[0].in_value = field0_in;
483 fields[0].in_check_value = NULL;
484 fields[0].in_check_mask = NULL;
485 fields[0].in_handler = NULL;
486 fields[0].in_handler_priv = NULL;
488 fields[1].device = jtag_info->chain_pos;
489 fields[1].num_bits = 5;
490 fields[1].out_value = field1_out;
491 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
492 fields[1].out_mask = NULL;
493 fields[1].in_value = NULL;
494 fields[1].in_check_value = NULL;
495 fields[1].in_check_mask = NULL;
496 fields[1].in_handler = NULL;
497 fields[1].in_handler_priv = NULL;
499 fields[2].device = jtag_info->chain_pos;
500 fields[2].num_bits = 1;
501 fields[2].out_value = field2_out;
502 buf_set_u32(fields[2].out_value, 0, 1, 0);
503 fields[2].out_mask = NULL;
504 fields[2].in_value = NULL;
505 fields[2].in_check_value = NULL;
506 fields[2].in_check_mask = NULL;
507 fields[2].in_handler = NULL;
508 fields[2].in_handler_priv = NULL;
510 jtag_add_dr_scan(3, fields, -1);
511 gettimeofday(&lap, NULL);
514 jtag_add_dr_scan(3, fields, -1);
515 if ((retval = jtag_execute_queue()) != ERROR_OK)
518 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
521 gettimeofday(&now, NULL);
523 while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
525 return ERROR_TARGET_TIMEOUT;