1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "embeddedice.h"
27 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
47 int embeddedice_reg_arch_info[] =
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
55 char* embeddedice_reg_list[] =
67 "watch 0 control value",
68 "watch 0 control mask",
74 "watch 1 control value",
75 "watch 1 control mask",
80 int embeddedice_reg_arch_type = -1;
82 int embeddedice_get_reg(reg_t *reg);
83 int embeddedice_set_reg(reg_t *reg, u32 value);
84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
86 int embeddedice_write_reg(reg_t *reg, u32 value);
87 int embeddedice_read_reg(reg_t *reg);
89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
92 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
93 reg_t *reg_list = NULL;
94 embeddedice_reg_t *arch_info = NULL;
95 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
100 /* register a register arch-type for EmbeddedICE registers only once */
101 if (embeddedice_reg_arch_type == -1)
102 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
104 if (arm7_9->has_vector_catch)
109 /* the actual registers are kept in two arrays */
110 reg_list = calloc(num_regs, sizeof(reg_t));
111 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
113 /* fill in values for the reg cache */
114 reg_cache->name = "EmbeddedICE registers";
115 reg_cache->next = NULL;
116 reg_cache->reg_list = reg_list;
117 reg_cache->num_regs = num_regs;
119 /* set up registers */
120 for (i = 0; i < num_regs; i++)
122 reg_list[i].name = embeddedice_reg_list[i];
123 reg_list[i].size = 32;
124 reg_list[i].dirty = 0;
125 reg_list[i].valid = 0;
126 reg_list[i].bitfield_desc = NULL;
127 reg_list[i].num_bitfields = 0;
128 reg_list[i].value = calloc(1, 4);
129 reg_list[i].arch_info = &arch_info[i];
130 reg_list[i].arch_type = embeddedice_reg_arch_type;
131 arch_info[i].addr = embeddedice_reg_arch_info[i];
132 arch_info[i].jtag_info = jtag_info;
135 /* identify EmbeddedICE version by reading DCC control register */
136 embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
137 if ((retval=jtag_execute_queue())!=ERROR_OK)
139 for (i = 0; i < num_regs; i++)
141 free(reg_list[i].value);
148 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
150 switch (eice_version)
153 reg_list[EICE_DBG_CTRL].size = 3;
154 reg_list[EICE_DBG_STAT].size = 5;
157 reg_list[EICE_DBG_CTRL].size = 4;
158 reg_list[EICE_DBG_STAT].size = 5;
159 arm7_9->has_single_step = 1;
162 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
163 reg_list[EICE_DBG_CTRL].size = 6;
164 reg_list[EICE_DBG_STAT].size = 5;
165 arm7_9->has_single_step = 1;
166 arm7_9->has_monitor_mode = 1;
169 reg_list[EICE_DBG_CTRL].size = 6;
170 reg_list[EICE_DBG_STAT].size = 5;
171 arm7_9->has_monitor_mode = 1;
174 reg_list[EICE_DBG_CTRL].size = 6;
175 reg_list[EICE_DBG_STAT].size = 5;
176 arm7_9->has_single_step = 1;
177 arm7_9->has_monitor_mode = 1;
180 reg_list[EICE_DBG_CTRL].size = 6;
181 reg_list[EICE_DBG_STAT].size = 10;
182 arm7_9->has_monitor_mode = 1;
185 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
186 reg_list[EICE_DBG_CTRL].size = 6;
187 reg_list[EICE_DBG_STAT].size = 5;
188 arm7_9->has_monitor_mode = 1;
191 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
197 int embeddedice_setup(target_t *target)
200 armv4_5_common_t *armv4_5 = target->arch_info;
201 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
203 /* explicitly disable monitor mode */
204 if (arm7_9->has_monitor_mode)
206 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
208 embeddedice_read_reg(dbg_ctrl);
209 if ((retval=jtag_execute_queue())!=ERROR_OK)
211 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
212 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
214 return jtag_execute_queue();
217 int embeddedice_get_reg(reg_t *reg)
219 if (embeddedice_read_reg(reg) != ERROR_OK)
221 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
225 if (jtag_execute_queue() != ERROR_OK)
227 LOG_ERROR("register read failed");
233 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
235 embeddedice_reg_t *ice_reg = reg->arch_info;
236 u8 reg_addr = ice_reg->addr & 0x1f;
237 scan_field_t fields[3];
241 jtag_add_end_state(TAP_RTI);
242 arm_jtag_scann(ice_reg->jtag_info, 0x2);
244 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
246 fields[0].device = ice_reg->jtag_info->chain_pos;
247 fields[0].num_bits = 32;
248 fields[0].out_value = reg->value;
249 fields[0].out_mask = NULL;
250 fields[0].in_value = NULL;
251 fields[0].in_check_value = NULL;
252 fields[0].in_check_mask = NULL;
253 fields[0].in_handler = NULL;
254 fields[0].in_handler_priv = NULL;
256 fields[1].device = ice_reg->jtag_info->chain_pos;
257 fields[1].num_bits = 5;
258 fields[1].out_value = field1_out;
259 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
260 fields[1].out_mask = NULL;
261 fields[1].in_value = NULL;
262 fields[1].in_check_value = NULL;
263 fields[1].in_check_mask = NULL;
264 fields[1].in_handler = NULL;
265 fields[1].in_handler_priv = NULL;
267 fields[2].device = ice_reg->jtag_info->chain_pos;
268 fields[2].num_bits = 1;
269 fields[2].out_value = field2_out;
270 buf_set_u32(fields[2].out_value, 0, 1, 0);
271 fields[2].out_mask = NULL;
272 fields[2].in_value = NULL;
273 fields[2].in_check_value = NULL;
274 fields[2].in_check_mask = NULL;
275 fields[2].in_handler = NULL;
276 fields[2].in_handler_priv = NULL;
278 jtag_add_dr_scan(3, fields, -1);
280 fields[0].in_value = reg->value;
281 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
283 /* when reading the DCC data register, leaving the address field set to
284 * EICE_COMMS_DATA would read the register twice
285 * reading the control register is safe
287 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
289 jtag_add_dr_scan(3, fields, -1);
294 /* receive <size> words of 32 bit from the DCC
295 * we pretend the target is always going to be fast enough
296 * (relative to the JTAG clock), so we don't need to handshake
298 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
300 scan_field_t fields[3];
304 jtag_add_end_state(TAP_RTI);
305 arm_jtag_scann(jtag_info, 0x2);
306 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
308 fields[0].device = jtag_info->chain_pos;
309 fields[0].num_bits = 32;
310 fields[0].out_value = NULL;
311 fields[0].out_mask = NULL;
312 fields[0].in_value = NULL;
313 fields[0].in_check_value = NULL;
314 fields[0].in_check_mask = NULL;
315 fields[0].in_handler = NULL;
316 fields[0].in_handler_priv = NULL;
318 fields[1].device = jtag_info->chain_pos;
319 fields[1].num_bits = 5;
320 fields[1].out_value = field1_out;
321 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
322 fields[1].out_mask = NULL;
323 fields[1].in_value = NULL;
324 fields[1].in_check_value = NULL;
325 fields[1].in_check_mask = NULL;
326 fields[1].in_handler = NULL;
327 fields[1].in_handler_priv = NULL;
329 fields[2].device = jtag_info->chain_pos;
330 fields[2].num_bits = 1;
331 fields[2].out_value = field2_out;
332 buf_set_u32(fields[2].out_value, 0, 1, 0);
333 fields[2].out_mask = NULL;
334 fields[2].in_value = NULL;
335 fields[2].in_check_value = NULL;
336 fields[2].in_check_mask = NULL;
337 fields[2].in_handler = NULL;
338 fields[2].in_handler_priv = NULL;
340 jtag_add_dr_scan(3, fields, -1);
344 /* when reading the last item, set the register address to the DCC control reg,
345 * to avoid reading additional data from the DCC data reg
348 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
350 fields[0].in_handler = arm_jtag_buf_to_u32;
351 fields[0].in_handler_priv = data;
352 jtag_add_dr_scan(3, fields, -1);
358 return jtag_execute_queue();
361 int embeddedice_read_reg(reg_t *reg)
363 return embeddedice_read_reg_w_check(reg, NULL, NULL);
366 int embeddedice_set_reg(reg_t *reg, u32 value)
368 if (embeddedice_write_reg(reg, value) != ERROR_OK)
370 LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
374 buf_set_u32(reg->value, 0, reg->size, value);
381 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
383 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
385 if (jtag_execute_queue() != ERROR_OK)
387 LOG_ERROR("register write failed");
393 int embeddedice_write_reg(reg_t *reg, u32 value)
395 embeddedice_reg_t *ice_reg = reg->arch_info;
397 LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
399 jtag_add_end_state(TAP_RTI);
400 arm_jtag_scann(ice_reg->jtag_info, 0x2);
402 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
404 u8 reg_addr = ice_reg->addr & 0x1f;
405 embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
410 int embeddedice_store_reg(reg_t *reg)
412 return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
415 /* send <size> words of 32 bit to the DCC
416 * we pretend the target is always going to be fast enough
417 * (relative to the JTAG clock), so we don't need to handshake
419 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
421 scan_field_t fields[3];
426 jtag_add_end_state(TAP_RTI);
427 arm_jtag_scann(jtag_info, 0x2);
428 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
430 fields[0].device = jtag_info->chain_pos;
431 fields[0].num_bits = 32;
432 fields[0].out_value = field0_out;
433 fields[0].out_mask = NULL;
434 fields[0].in_value = NULL;
435 fields[0].in_check_value = NULL;
436 fields[0].in_check_mask = NULL;
437 fields[0].in_handler = NULL;
438 fields[0].in_handler_priv = NULL;
440 fields[1].device = jtag_info->chain_pos;
441 fields[1].num_bits = 5;
442 fields[1].out_value = field1_out;
443 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
444 fields[1].out_mask = NULL;
445 fields[1].in_value = NULL;
446 fields[1].in_check_value = NULL;
447 fields[1].in_check_mask = NULL;
448 fields[1].in_handler = NULL;
449 fields[1].in_handler_priv = NULL;
451 fields[2].device = jtag_info->chain_pos;
452 fields[2].num_bits = 1;
453 fields[2].out_value = field2_out;
454 buf_set_u32(fields[2].out_value, 0, 1, 1);
455 fields[2].out_mask = NULL;
456 fields[2].in_value = NULL;
457 fields[2].in_check_value = NULL;
458 fields[2].in_check_mask = NULL;
459 fields[2].in_handler = NULL;
460 fields[2].in_handler_priv = NULL;
464 buf_set_u32(fields[0].out_value, 0, 32, *data);
465 jtag_add_dr_scan(3, fields, -1);
471 /* call to jtag_execute_queue() intentionally omitted */
475 /* wait for DCC control register R/W handshake bit to become active
477 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
479 scan_field_t fields[3];
488 if (hsbit == EICE_COMM_CTRL_WBIT)
490 else if (hsbit == EICE_COMM_CTRL_RBIT)
493 return ERROR_INVALID_ARGUMENTS;
495 jtag_add_end_state(TAP_RTI);
496 arm_jtag_scann(jtag_info, 0x2);
497 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
499 fields[0].device = jtag_info->chain_pos;
500 fields[0].num_bits = 32;
501 fields[0].out_value = NULL;
502 fields[0].out_mask = NULL;
503 fields[0].in_value = field0_in;
504 fields[0].in_check_value = NULL;
505 fields[0].in_check_mask = NULL;
506 fields[0].in_handler = NULL;
507 fields[0].in_handler_priv = NULL;
509 fields[1].device = jtag_info->chain_pos;
510 fields[1].num_bits = 5;
511 fields[1].out_value = field1_out;
512 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
513 fields[1].out_mask = NULL;
514 fields[1].in_value = NULL;
515 fields[1].in_check_value = NULL;
516 fields[1].in_check_mask = NULL;
517 fields[1].in_handler = NULL;
518 fields[1].in_handler_priv = NULL;
520 fields[2].device = jtag_info->chain_pos;
521 fields[2].num_bits = 1;
522 fields[2].out_value = field2_out;
523 buf_set_u32(fields[2].out_value, 0, 1, 0);
524 fields[2].out_mask = NULL;
525 fields[2].in_value = NULL;
526 fields[2].in_check_value = NULL;
527 fields[2].in_check_mask = NULL;
528 fields[2].in_handler = NULL;
529 fields[2].in_handler_priv = NULL;
531 jtag_add_dr_scan(3, fields, -1);
532 gettimeofday(&lap, NULL);
535 jtag_add_dr_scan(3, fields, -1);
536 if ((retval = jtag_execute_queue()) != ERROR_OK)
539 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
542 gettimeofday(&now, NULL);
544 while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
546 return ERROR_TARGET_TIMEOUT;