1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007-2010 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "embeddedice.h"
36 * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
37 * module found on scan chain 2 in ARM7, ARM9, and some other families
38 * of ARM cores. The module is called "EmbeddedICE-RT" if it has
39 * monitor mode support.
41 * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
42 * Communications Channel (DCC) used to read or write 32-bit words to
43 * OpenOCD-aware code running on the target CPU.
44 * Newer modules also include vector catch hardware. Some versions
45 * support hardware single-stepping, "monitor mode" debug (which is not
46 * currently supported by OpenOCD), or extended reporting on why the
47 * core entered debug mode.
51 * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
61 /* width is assigned based on EICE version */
64 .name = "debug_status",
66 /* width is assigned based on EICE version */
78 [EICE_W0_ADDR_VALUE] = {
79 .name = "watch_0_addr_value",
83 [EICE_W0_ADDR_MASK] = {
84 .name = "watch_0_addr_mask",
88 [EICE_W0_DATA_VALUE ] = {
89 .name = "watch_0_data_value",
93 [EICE_W0_DATA_MASK] = {
94 .name = "watch_0_data_mask",
98 [EICE_W0_CONTROL_VALUE] = {
99 .name = "watch_0_control_value",
103 [EICE_W0_CONTROL_MASK] = {
104 .name = "watch_0_control_mask",
108 [EICE_W1_ADDR_VALUE] = {
109 .name = "watch_1_addr_value",
113 [EICE_W1_ADDR_MASK] = {
114 .name = "watch_1_addr_mask",
118 [EICE_W1_DATA_VALUE] = {
119 .name = "watch_1_data_value",
123 [EICE_W1_DATA_MASK] = {
124 .name = "watch_1_data_mask",
128 [EICE_W1_CONTROL_VALUE] = {
129 .name = "watch_1_control_value",
133 [EICE_W1_CONTROL_MASK] = {
134 .name = "watch_1_control_mask",
138 /* vector_catch isn't always present */
140 .name = "vector_catch",
147 static int embeddedice_get_reg(struct reg *reg)
151 if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
152 LOG_ERROR("error queueing EmbeddedICE register read");
153 else if ((retval = jtag_execute_queue()) != ERROR_OK)
154 LOG_ERROR("EmbeddedICE register read failed");
159 static const struct reg_arch_type eice_reg_type = {
160 .get = embeddedice_get_reg,
161 .set = embeddedice_set_reg_w_exec,
165 * Probe EmbeddedICE module and set up local records of its registers.
166 * Different versions of the modules have different capabilities, such as
167 * hardware support for vector_catch, single stepping, and monitor mode.
170 embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
173 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
174 struct reg *reg_list = NULL;
175 struct embeddedice_reg *arch_info = NULL;
176 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
177 int num_regs = ARRAY_SIZE(eice_regs);
179 int eice_version = 0;
181 /* vector_catch isn't always present */
182 if (!arm7_9->has_vector_catch)
185 /* the actual registers are kept in two arrays */
186 reg_list = calloc(num_regs, sizeof(struct reg));
187 arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
189 /* fill in values for the reg cache */
190 reg_cache->name = "EmbeddedICE registers";
191 reg_cache->next = NULL;
192 reg_cache->reg_list = reg_list;
193 reg_cache->num_regs = num_regs;
195 /* FIXME the second watchpoint unit on Feroceon and Dragonite
196 * seems not to work ... we should have a way to not set up
197 * its four registers here!
200 /* set up registers */
201 for (i = 0; i < num_regs; i++)
203 reg_list[i].name = eice_regs[i].name;
204 reg_list[i].size = eice_regs[i].width;
205 reg_list[i].dirty = 0;
206 reg_list[i].valid = 0;
207 reg_list[i].value = calloc(1, 4);
208 reg_list[i].arch_info = &arch_info[i];
209 reg_list[i].type = &eice_reg_type;
210 arch_info[i].addr = eice_regs[i].addr;
211 arch_info[i].jtag_info = jtag_info;
214 /* identify EmbeddedICE version by reading DCC control register */
215 embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
216 if ((retval = jtag_execute_queue()) != ERROR_OK)
218 for (i = 0; i < num_regs; i++)
220 free(reg_list[i].value);
228 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
229 LOG_INFO("Embedded ICE version %d", eice_version);
231 switch (eice_version)
234 /* ARM7TDMI r3, ARM7TDMI-S r3
236 * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
237 * that it has 6-bit CTRL and 5-bit STAT... doc bug?
238 * ARM7TDMI r4 docs say EICE v4.
240 reg_list[EICE_DBG_CTRL].size = 3;
241 reg_list[EICE_DBG_STAT].size = 5;
245 reg_list[EICE_DBG_CTRL].size = 4;
246 reg_list[EICE_DBG_STAT].size = 5;
247 arm7_9->has_single_step = 1;
250 LOG_ERROR("EmbeddedICE v%d handling might be broken",
252 reg_list[EICE_DBG_CTRL].size = 6;
253 reg_list[EICE_DBG_STAT].size = 5;
254 arm7_9->has_single_step = 1;
255 arm7_9->has_monitor_mode = 1;
259 reg_list[EICE_DBG_CTRL].size = 6;
260 reg_list[EICE_DBG_STAT].size = 5;
261 arm7_9->has_monitor_mode = 1;
265 reg_list[EICE_DBG_CTRL].size = 6;
266 reg_list[EICE_DBG_STAT].size = 5;
267 arm7_9->has_single_step = 1;
268 arm7_9->has_monitor_mode = 1;
271 /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
272 reg_list[EICE_DBG_CTRL].size = 6;
273 reg_list[EICE_DBG_STAT].size = 10;
274 /* DBG_STAT has MOE bits */
275 arm7_9->has_monitor_mode = 1;
278 LOG_ERROR("EmbeddedICE v%d handling might be broken",
280 reg_list[EICE_DBG_CTRL].size = 6;
281 reg_list[EICE_DBG_STAT].size = 5;
282 arm7_9->has_monitor_mode = 1;
286 * The Feroceon implementation has the version number
287 * in some unusual bits. Let feroceon.c validate it
288 * and do the appropriate setup itself.
290 if (strcmp(target_type_name(target), "feroceon") == 0 ||
291 strcmp(target_type_name(target), "dragonite") == 0)
293 LOG_ERROR("unknown EmbeddedICE version "
294 "(comms ctrl: 0x%8.8" PRIx32 ")",
295 buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
298 /* On Feroceon and Dragonite the second unit is seemingly missing. */
299 LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
300 target_name(target), arm7_9->wp_available_max,
301 (arm7_9->wp_available_max != 1) ? "s" : "");
307 * Initialize EmbeddedICE module, if needed.
309 int embeddedice_setup(struct target *target)
312 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
314 /* Explicitly disable monitor mode. For now we only support halting
315 * debug ... we don't know how to talk with a resident debug monitor
316 * that manages break requests. ARM's "Angel Debug Monitor" is one
317 * common example of such code.
319 if (arm7_9->has_monitor_mode)
321 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
323 embeddedice_read_reg(dbg_ctrl);
324 if ((retval = jtag_execute_queue()) != ERROR_OK)
326 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
327 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
329 return jtag_execute_queue();
333 * Queue a read for an EmbeddedICE register into the register cache,
334 * optionally checking the value read.
335 * Note that at this level, all registers are 32 bits wide.
337 int embeddedice_read_reg_w_check(struct reg *reg,
338 uint8_t *check_value, uint8_t *check_mask)
340 struct embeddedice_reg *ice_reg = reg->arch_info;
341 uint8_t reg_addr = ice_reg->addr & 0x1f;
342 struct scan_field fields[3];
343 uint8_t field1_out[1];
344 uint8_t field2_out[1];
346 arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
348 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
350 /* bits 31:0 -- data (ignored here) */
351 fields[0].num_bits = 32;
352 fields[0].out_value = reg->value;
353 fields[0].in_value = NULL;
354 fields[0].check_value = NULL;
355 fields[0].check_mask = NULL;
357 /* bits 36:32 -- register */
358 fields[1].num_bits = 5;
359 fields[1].out_value = field1_out;
360 field1_out[0] = reg_addr;
361 fields[1].in_value = NULL;
362 fields[1].check_value = NULL;
363 fields[1].check_mask = NULL;
365 /* bit 37 -- 0/read */
366 fields[2].num_bits = 1;
367 fields[2].out_value = field2_out;
369 fields[2].in_value = NULL;
370 fields[2].check_value = NULL;
371 fields[2].check_mask = NULL;
373 /* traverse Update-DR, setting address for the next read */
374 jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
376 /* bits 31:0 -- the data we're reading (and maybe checking) */
377 fields[0].in_value = reg->value;
378 fields[0].check_value = check_value;
379 fields[0].check_mask = check_mask;
381 /* when reading the DCC data register, leaving the address field set to
382 * EICE_COMMS_DATA would read the register twice
383 * reading the control register is safe
385 field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
387 /* traverse Update-DR, reading but with no other side effects */
388 jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
394 * Receive a block of size 32-bit words from the DCC.
395 * We assume the target is always going to be fast enough (relative to
396 * the JTAG clock) that the debugger won't need to poll the handshake
397 * bit. The JTAG clock is usually at least six times slower than the
398 * functional clock, so the 50+ JTAG clocks needed to receive the word
399 * allow hundreds of instruction cycles (per word) in the target.
401 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
403 struct scan_field fields[3];
404 uint8_t field1_out[1];
405 uint8_t field2_out[1];
407 arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
408 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
410 fields[0].num_bits = 32;
411 fields[0].out_value = NULL;
412 fields[0].in_value = NULL;
414 fields[1].num_bits = 5;
415 fields[1].out_value = field1_out;
416 field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
417 fields[1].in_value = NULL;
419 fields[2].num_bits = 1;
420 fields[2].out_value = field2_out;
422 fields[2].in_value = NULL;
424 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
428 /* when reading the last item, set the register address to the DCC control reg,
429 * to avoid reading additional data from the DCC data reg
432 field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
434 fields[0].in_value = (uint8_t *)data;
435 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
436 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
442 return jtag_execute_queue();
446 * Queue a read for an EmbeddedICE register into the register cache,
447 * not checking the value read.
449 int embeddedice_read_reg(struct reg *reg)
451 return embeddedice_read_reg_w_check(reg, NULL, NULL);
455 * Queue a write for an EmbeddedICE register, updating the register cache.
456 * Uses embeddedice_write_reg().
458 void embeddedice_set_reg(struct reg *reg, uint32_t value)
460 embeddedice_write_reg(reg, value);
462 buf_set_u32(reg->value, 0, reg->size, value);
469 * Write an EmbeddedICE register, updating the register cache.
470 * Uses embeddedice_set_reg(); not queued.
472 int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
476 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
477 if ((retval = jtag_execute_queue()) != ERROR_OK)
478 LOG_ERROR("register write failed");
483 * Queue a write for an EmbeddedICE register, bypassing the register cache.
485 void embeddedice_write_reg(struct reg *reg, uint32_t value)
487 struct embeddedice_reg *ice_reg = reg->arch_info;
489 LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
491 arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
493 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
495 uint8_t reg_addr = ice_reg->addr & 0x1f;
496 embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
500 * Queue a write for an EmbeddedICE register, using cached value.
501 * Uses embeddedice_write_reg().
503 void embeddedice_store_reg(struct reg *reg)
505 embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
509 * Send a block of size 32-bit words to the DCC.
510 * We assume the target is always going to be fast enough (relative to
511 * the JTAG clock) that the debugger won't need to poll the handshake
512 * bit. The JTAG clock is usually at least six times slower than the
513 * functional clock, so the 50+ JTAG clocks needed to receive the word
514 * allow hundreds of instruction cycles (per word) in the target.
516 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
518 struct scan_field fields[3];
519 uint8_t field0_out[4];
520 uint8_t field1_out[1];
521 uint8_t field2_out[1];
523 arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
524 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
526 fields[0].num_bits = 32;
527 fields[0].out_value = field0_out;
528 fields[0].in_value = NULL;
530 fields[1].num_bits = 5;
531 fields[1].out_value = field1_out;
532 field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
533 fields[1].in_value = NULL;
535 fields[2].num_bits = 1;
536 fields[2].out_value = field2_out;
539 fields[2].in_value = NULL;
543 buf_set_u32(field0_out, 0, 32, *data);
544 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
550 /* call to jtag_execute_queue() intentionally omitted */
555 * Poll DCC control register until read or write handshake completes.
557 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
559 struct scan_field fields[3];
560 uint8_t field0_in[4];
561 uint8_t field1_out[1];
562 uint8_t field2_out[1];
568 if (hsbit == EICE_COMM_CTRL_WBIT)
570 else if (hsbit == EICE_COMM_CTRL_RBIT)
573 return ERROR_INVALID_ARGUMENTS;
575 arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
576 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
578 fields[0].num_bits = 32;
579 fields[0].out_value = NULL;
580 fields[0].in_value = field0_in;
582 fields[1].num_bits = 5;
583 fields[1].out_value = field1_out;
584 field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
585 fields[1].in_value = NULL;
587 fields[2].num_bits = 1;
588 fields[2].out_value = field2_out;
590 fields[2].in_value = NULL;
592 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
593 gettimeofday(&lap, NULL);
595 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
596 if ((retval = jtag_execute_queue()) != ERROR_OK)
599 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
602 gettimeofday(&now, NULL);
603 } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
604 + (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
606 return ERROR_TARGET_TIMEOUT;
609 #ifndef HAVE_JTAG_MINIDRIVER_H
611 * This is an inner loop of the open loop DCC write of data to target
613 void embeddedice_write_dcc(struct jtag_tap *tap,
614 int reg_addr, uint8_t *buffer, int little, int count)
618 for (i = 0; i < count; i++)
620 embeddedice_write_reg_inner(tap, reg_addr,
621 fast_target_buffer_get_u32(buffer, little));
626 /* provided by minidriver */