git.sur5r.net Git - openocd/blob - src/target/embeddedice.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "embeddedice.h"
  30 #include "register.h"
  31 #include <helper/time_support.h>
  32
  33 /**
  34  * @file
  35  *
  36  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  37  * module found on scan chain 2 in ARM7, ARM9, and some other families
  38  * of ARM cores.  The module is called "EmbeddedICE-RT" if it has
  39  * monitor mode support.
  40  *
  41  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  42  * Communications Channel (DCC) used to read or write 32-bit words to
  43  * OpenOCD-aware code running on the target CPU.
  44  * Newer modules also include vector catch hardware.  Some versions
  45  * support hardware single-stepping, "monitor mode" debug (which is not
  46  * currently supported by OpenOCD), or extended reporting on why the
  47  * core entered debug mode.
  48  */
  49
  50 static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
  51
  52 /*
  53  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  54  */
  55 static const struct {
  56         const char     *name;
  57         unsigned short addr;
  58         unsigned short width;
  59 } eice_regs[] = {
  60         [EICE_DBG_CTRL] = {
  61                 .name =         "debug_ctrl",
  62                 .addr =         0,
  63                 /* width is assigned based on EICE version */
  64         },
  65         [EICE_DBG_STAT] = {
  66                 .name =         "debug_status",
  67                 .addr =         1,
  68                 /* width is assigned based on EICE version */
  69         },
  70         [EICE_COMMS_CTRL] = {
  71                 .name =         "comms_ctrl",
  72                 .addr =         4,
  73                 .width =        6,
  74         },
  75         [EICE_COMMS_DATA] = {
  76                 .name =         "comms_data",
  77                 .addr =         5,
  78                 .width =        32,
  79         },
  80         [EICE_W0_ADDR_VALUE] = {
  81                 .name =         "watch_0_addr_value",
  82                 .addr =         8,
  83                 .width =        32,
  84         },
  85         [EICE_W0_ADDR_MASK] = {
  86                 .name =         "watch_0_addr_mask",
  87                 .addr =         9,
  88                 .width =        32,
  89         },
  90         [EICE_W0_DATA_VALUE] = {
  91                 .name =         "watch_0_data_value",
  92                 .addr =         10,
  93                 .width =        32,
  94         },
  95         [EICE_W0_DATA_MASK] = {
  96                 .name =         "watch_0_data_mask",
  97                 .addr =         11,
  98                 .width =        32,
  99         },
 100         [EICE_W0_CONTROL_VALUE] = {
 101                 .name =         "watch_0_control_value",
 102                 .addr =         12,
 103                 .width =        9,
 104         },
 105         [EICE_W0_CONTROL_MASK] = {
 106                 .name =         "watch_0_control_mask",
 107                 .addr =         13,
 108                 .width =        8,
 109         },
 110         [EICE_W1_ADDR_VALUE] = {
 111                 .name =         "watch_1_addr_value",
 112                 .addr =         16,
 113                 .width =        32,
 114         },
 115         [EICE_W1_ADDR_MASK] = {
 116                 .name =         "watch_1_addr_mask",
 117                 .addr =         17,
 118                 .width =        32,
 119         },
 120         [EICE_W1_DATA_VALUE] = {
 121                 .name =         "watch_1_data_value",
 122                 .addr =         18,
 123                 .width =        32,
 124         },
 125         [EICE_W1_DATA_MASK] = {
 126                 .name =         "watch_1_data_mask",
 127                 .addr =         19,
 128                 .width =        32,
 129         },
 130         [EICE_W1_CONTROL_VALUE] = {
 131                 .name =         "watch_1_control_value",
 132                 .addr =         20,
 133                 .width =        9,
 134         },
 135         [EICE_W1_CONTROL_MASK] = {
 136                 .name =         "watch_1_control_mask",
 137                 .addr =         21,
 138                 .width =        8,
 139         },
 140         /* vector_catch isn't always present */
 141         [EICE_VEC_CATCH] = {
 142                 .name =         "vector_catch",
 143                 .addr =         2,
 144                 .width =        8,
 145         },
 146 };
 147
 148 static int embeddedice_get_reg(struct reg *reg)
 149 {
 150         int retval = embeddedice_read_reg(reg);
 151         if (retval != ERROR_OK) {
 152                 LOG_ERROR("error queueing EmbeddedICE register read");
 153                 return retval;
 154         }
 155
 156         retval = jtag_execute_queue();
 157         if (retval != ERROR_OK)
 158                 LOG_ERROR("EmbeddedICE register read failed");
 159
 160         return retval;
 161 }
 162
 163 static const struct reg_arch_type eice_reg_type = {
 164         .get = embeddedice_get_reg,
 165         .set = embeddedice_set_reg_w_exec,
 166 };
 167
 168 /**
 169  * Probe EmbeddedICE module and set up local records of its registers.
 170  * Different versions of the modules have different capabilities, such as
 171  * hardware support for vector_catch, single stepping, and monitor mode.
 172  */
 173 struct reg_cache *embeddedice_build_reg_cache(struct target *target,
 174                 struct arm7_9_common *arm7_9)
 175 {
 176         int retval;
 177         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 178         struct reg *reg_list = NULL;
 179         struct embeddedice_reg *arch_info = NULL;
 180         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 181         int num_regs = ARRAY_SIZE(eice_regs);
 182         int i;
 183         int eice_version = 0;
 184
 185         /* vector_catch isn't always present */
 186         if (!arm7_9->has_vector_catch)
 187                 num_regs--;
 188
 189         /* the actual registers are kept in two arrays */
 190         reg_list = calloc(num_regs, sizeof(struct reg));
 191         arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
 192
 193         /* fill in values for the reg cache */
 194         reg_cache->name = "EmbeddedICE registers";
 195         reg_cache->next = NULL;
 196         reg_cache->reg_list = reg_list;
 197         reg_cache->num_regs = num_regs;
 198
 199         /* FIXME the second watchpoint unit on Feroceon and Dragonite
 200          * seems not to work ... we should have a way to not set up
 201          * its four registers here!
 202          */
 203
 204         /* set up registers */
 205         for (i = 0; i < num_regs; i++) {
 206                 reg_list[i].name = eice_regs[i].name;
 207                 reg_list[i].size = eice_regs[i].width;
 208                 reg_list[i].dirty = 0;
 209                 reg_list[i].valid = 0;
 210                 reg_list[i].value = calloc(1, 4);
 211                 reg_list[i].arch_info = &arch_info[i];
 212                 reg_list[i].type = &eice_reg_type;
 213                 arch_info[i].addr = eice_regs[i].addr;
 214                 arch_info[i].jtag_info = jtag_info;
 215         }
 216
 217         /* identify EmbeddedICE version by reading DCC control register */
 218         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 219         retval = jtag_execute_queue();
 220         if (retval != ERROR_OK) {
 221                 for (i = 0; i < num_regs; i++)
 222                         free(reg_list[i].value);
 223                 free(reg_list);
 224                 free(reg_cache);
 225                 free(arch_info);
 226                 return NULL;
 227         }
 228
 229         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 230         LOG_INFO("Embedded ICE version %d", eice_version);
 231
 232         switch (eice_version) {
 233                 case 1:
 234                         /* ARM7TDMI r3, ARM7TDMI-S r3
 235                          *
 236                          * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
 237                          * that it has 6-bit CTRL and 5-bit STAT... doc bug?
 238                          * ARM7TDMI r4 docs say EICE v4.
 239                          */
 240                         reg_list[EICE_DBG_CTRL].size = 3;
 241                         reg_list[EICE_DBG_STAT].size = 5;
 242                         break;
 243                 case 2:
 244                         /* ARM9TDMI */
 245                         reg_list[EICE_DBG_CTRL].size = 4;
 246                         reg_list[EICE_DBG_STAT].size = 5;
 247                         arm7_9->has_single_step = 1;
 248                         break;
 249                 case 3:
 250                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 251                                         eice_version);
 252                         reg_list[EICE_DBG_CTRL].size = 6;
 253                         reg_list[EICE_DBG_STAT].size = 5;
 254                         arm7_9->has_single_step = 1;
 255                         arm7_9->has_monitor_mode = 1;
 256                         break;
 257                 case 4:
 258                         /* ARM7TDMI r4 */
 259                         reg_list[EICE_DBG_CTRL].size = 6;
 260                         reg_list[EICE_DBG_STAT].size = 5;
 261                         arm7_9->has_monitor_mode = 1;
 262                         break;
 263                 case 5:
 264                         /* ARM9E-S rev 1 */
 265                         reg_list[EICE_DBG_CTRL].size = 6;
 266                         reg_list[EICE_DBG_STAT].size = 5;
 267                         arm7_9->has_single_step = 1;
 268                         arm7_9->has_monitor_mode = 1;
 269                         break;
 270                 case 6:
 271                         /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
 272                         reg_list[EICE_DBG_CTRL].size = 6;
 273                         reg_list[EICE_DBG_STAT].size = 10;
 274                         /* DBG_STAT has MOE bits */
 275                         arm7_9->has_monitor_mode = 1;
 276                         break;
 277                 case 7:
 278                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 279                                         eice_version);
 280                         reg_list[EICE_DBG_CTRL].size = 6;
 281                         reg_list[EICE_DBG_STAT].size = 5;
 282                         arm7_9->has_monitor_mode = 1;
 283                         break;
 284                 default:
 285                         /*
 286                          * The Feroceon implementation has the version number
 287                          * in some unusual bits.  Let feroceon.c validate it
 288                          * and do the appropriate setup itself.
 289                          */
 290                         if (strcmp(target_type_name(target), "feroceon") == 0 ||
 291                                         strcmp(target_type_name(target), "dragonite") == 0)
 292                                 break;
 293                         LOG_ERROR("unknown EmbeddedICE version "
 294                                 "(comms ctrl: 0x%8.8" PRIx32 ")",
 295                                 buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 296         }
 297
 298         /* On Feroceon and Dragonite the second unit is seemingly missing. */
 299         LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
 300                         target_name(target), arm7_9->wp_available_max,
 301                         (arm7_9->wp_available_max != 1) ? "s" : "");
 302
 303         return reg_cache;
 304 }
 305
 306 /**
 307  * Initialize EmbeddedICE module, if needed.
 308  */
 309 int embeddedice_setup(struct target *target)
 310 {
 311         int retval;
 312         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 313
 314         /* Explicitly disable monitor mode.  For now we only support halting
 315          * debug ... we don't know how to talk with a resident debug monitor
 316          * that manages break requests.  ARM's "Angel Debug Monitor" is one
 317          * common example of such code.
 318          */
 319         if (arm7_9->has_monitor_mode) {
 320                 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 321
 322                 embeddedice_read_reg(dbg_ctrl);
 323                 retval = jtag_execute_queue();
 324                 if (retval != ERROR_OK)
 325                         return retval;
 326                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 327                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 328         }
 329         return jtag_execute_queue();
 330 }
 331
 332 /**
 333  * Queue a read for an EmbeddedICE register into the register cache,
 334  * optionally checking the value read.
 335  * Note that at this level, all registers are 32 bits wide.
 336  */
 337 int embeddedice_read_reg_w_check(struct reg *reg,
 338                 uint8_t *check_value, uint8_t *check_mask)
 339 {
 340         struct embeddedice_reg *ice_reg = reg->arch_info;
 341         uint8_t reg_addr = ice_reg->addr & 0x1f;
 342         struct scan_field fields[3];
 343         uint8_t field1_out[1];
 344         uint8_t field2_out[1];
 345         int retval;
 346
 347         retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         retval = arm_jtag_set_instr(ice_reg->jtag_info->tap,
 352                         ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 353         if (retval != ERROR_OK)
 354                 return retval;
 355
 356         /* bits 31:0 -- data (ignored here) */
 357         fields[0].num_bits = 32;
 358         fields[0].out_value = reg->value;
 359         fields[0].in_value = NULL;
 360         fields[0].check_value = NULL;
 361         fields[0].check_mask = NULL;
 362
 363         /* bits 36:32 -- register */
 364         fields[1].num_bits = 5;
 365         fields[1].out_value = field1_out;
 366         field1_out[0] = reg_addr;
 367         fields[1].in_value = NULL;
 368         fields[1].check_value = NULL;
 369         fields[1].check_mask = NULL;
 370
 371         /* bit 37 -- 0/read */
 372         fields[2].num_bits = 1;
 373         fields[2].out_value = field2_out;
 374         field2_out[0] = 0;
 375         fields[2].in_value = NULL;
 376         fields[2].check_value = NULL;
 377         fields[2].check_mask = NULL;
 378
 379         /* traverse Update-DR, setting address for the next read */
 380         jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 381
 382         /* bits 31:0 -- the data we're reading (and maybe checking) */
 383         fields[0].in_value = reg->value;
 384         fields[0].check_value = check_value;
 385         fields[0].check_mask = check_mask;
 386
 387         /* when reading the DCC data register, leaving the address field set to
 388          * EICE_COMMS_DATA would read the register twice
 389          * reading the control register is safe
 390          */
 391         field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 392
 393         /* traverse Update-DR, reading but with no other side effects */
 394         jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 395
 396         return ERROR_OK;
 397 }
 398
 399 /**
 400  * Receive a block of size 32-bit words from the DCC.
 401  * We assume the target is always going to be fast enough (relative to
 402  * the JTAG clock) that the debugger won't need to poll the handshake
 403  * bit.  The JTAG clock is usually at least six times slower than the
 404  * functional clock, so the 50+ JTAG clocks needed to receive the word
 405  * allow hundreds of instruction cycles (per word) in the target.
 406  */
 407 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 408 {
 409         struct scan_field fields[3];
 410         uint8_t field1_out[1];
 411         uint8_t field2_out[1];
 412         int retval;
 413
 414         retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 415         if (retval != ERROR_OK)
 416                 return retval;
 417         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
 418         if (retval != ERROR_OK)
 419                 return retval;
 420
 421         fields[0].num_bits = 32;
 422         fields[0].out_value = NULL;
 423         fields[0].in_value = NULL;
 424
 425         fields[1].num_bits = 5;
 426         fields[1].out_value = field1_out;
 427         field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 428         fields[1].in_value = NULL;
 429
 430         fields[2].num_bits = 1;
 431         fields[2].out_value = field2_out;
 432         field2_out[0] = 0;
 433         fields[2].in_value = NULL;
 434
 435         jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 436
 437         while (size > 0) {
 438                 /* when reading the last item, set the register address to the DCC control reg,
 439                  * to avoid reading additional data from the DCC data reg
 440                  */
 441                 if (size == 1)
 442                         field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 443
 444                 fields[0].in_value = (uint8_t *)data;
 445                 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 446                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 447
 448                 data++;
 449                 size--;
 450         }
 451
 452         return jtag_execute_queue();
 453 }
 454
 455 /**
 456  * Queue a read for an EmbeddedICE register into the register cache,
 457  * not checking the value read.
 458  */
 459 int embeddedice_read_reg(struct reg *reg)
 460 {
 461         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 462 }
 463
 464 /**
 465  * Queue a write for an EmbeddedICE register, updating the register cache.
 466  * Uses embeddedice_write_reg().
 467  */
 468 void embeddedice_set_reg(struct reg *reg, uint32_t value)
 469 {
 470         embeddedice_write_reg(reg, value);
 471
 472         buf_set_u32(reg->value, 0, reg->size, value);
 473         reg->valid = 1;
 474         reg->dirty = 0;
 475
 476 }
 477
 478 /**
 479  * Write an EmbeddedICE register, updating the register cache.
 480  * Uses embeddedice_set_reg(); not queued.
 481  */
 482 static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 483 {
 484         int retval;
 485
 486         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 487         retval = jtag_execute_queue();
 488         if (retval != ERROR_OK)
 489                 LOG_ERROR("register write failed");
 490         return retval;
 491 }
 492
 493 /**
 494  * Queue a write for an EmbeddedICE register, bypassing the register cache.
 495  */
 496 void embeddedice_write_reg(struct reg *reg, uint32_t value)
 497 {
 498         struct embeddedice_reg *ice_reg = reg->arch_info;
 499
 500         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 501
 502         arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 503
 504         arm_jtag_set_instr(ice_reg->jtag_info->tap, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 505
 506         uint8_t reg_addr = ice_reg->addr & 0x1f;
 507         embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 508 }
 509
 510 /**
 511  * Queue a write for an EmbeddedICE register, using cached value.
 512  * Uses embeddedice_write_reg().
 513  */
 514 void embeddedice_store_reg(struct reg *reg)
 515 {
 516         embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 517 }
 518
 519 /**
 520  * Send a block of size 32-bit words to the DCC.
 521  * We assume the target is always going to be fast enough (relative to
 522  * the JTAG clock) that the debugger won't need to poll the handshake
 523  * bit.  The JTAG clock is usually at least six times slower than the
 524  * functional clock, so the 50+ JTAG clocks needed to receive the word
 525  * allow hundreds of instruction cycles (per word) in the target.
 526  */
 527 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 528 {
 529         struct scan_field fields[3];
 530         uint8_t field0_out[4];
 531         uint8_t field1_out[1];
 532         uint8_t field2_out[1];
 533         int retval;
 534
 535         retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 536         if (retval != ERROR_OK)
 537                 return retval;
 538         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
 539         if (retval != ERROR_OK)
 540                 return retval;
 541
 542         fields[0].num_bits = 32;
 543         fields[0].out_value = field0_out;
 544         fields[0].in_value = NULL;
 545
 546         fields[1].num_bits = 5;
 547         fields[1].out_value = field1_out;
 548         field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 549         fields[1].in_value = NULL;
 550
 551         fields[2].num_bits = 1;
 552         fields[2].out_value = field2_out;
 553         field2_out[0] = 1;
 554
 555         fields[2].in_value = NULL;
 556
 557         while (size > 0) {
 558                 buf_set_u32(field0_out, 0, 32, *data);
 559                 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 560
 561                 data++;
 562                 size--;
 563         }
 564
 565         /* call to jtag_execute_queue() intentionally omitted */
 566         return ERROR_OK;
 567 }
 568
 569 /**
 570  * Poll DCC control register until read or write handshake completes.
 571  */
 572 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
 573 {
 574         struct scan_field fields[3];
 575         uint8_t field0_in[4];
 576         uint8_t field1_out[1];
 577         uint8_t field2_out[1];
 578         int retval;
 579         uint32_t hsact;
 580         struct timeval now;
 581         struct timeval timeout_end;
 582
 583         if (hsbit == EICE_COMM_CTRL_WBIT)
 584                 hsact = 1;
 585         else if (hsbit == EICE_COMM_CTRL_RBIT)
 586                 hsact = 0;
 587         else {
 588                 LOG_ERROR("Invalid arguments");
 589                 return ERROR_COMMAND_SYNTAX_ERROR;
 590         }
 591
 592         retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 593         if (retval != ERROR_OK)
 594                 return retval;
 595         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
 596         if (retval != ERROR_OK)
 597                 return retval;
 598
 599         fields[0].num_bits = 32;
 600         fields[0].out_value = NULL;
 601         fields[0].in_value = field0_in;
 602
 603         fields[1].num_bits = 5;
 604         fields[1].out_value = field1_out;
 605         field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 606         fields[1].in_value = NULL;
 607
 608         fields[2].num_bits = 1;
 609         fields[2].out_value = field2_out;
 610         field2_out[0] = 0;
 611         fields[2].in_value = NULL;
 612
 613         jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 614         gettimeofday(&timeout_end, NULL);
 615         timeval_add_time(&timeout_end, 0, timeout * 1000);
 616         do {
 617                 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 618                 retval = jtag_execute_queue();
 619                 if (retval != ERROR_OK)
 620                         return retval;
 621
 622                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 623                         return ERROR_OK;
 624
 625                 gettimeofday(&now, NULL);
 626         } while (timeval_compare(&now, &timeout_end) <= 0);
 627
 628         LOG_ERROR("embeddedice handshake timeout");
 629         return ERROR_TARGET_TIMEOUT;
 630 }
 631
 632 #ifndef HAVE_JTAG_MINIDRIVER_H
 633 /**
 634  * This is an inner loop of the open loop DCC write of data to target
 635  */
 636 void embeddedice_write_dcc(struct jtag_tap *tap,
 637                 int reg_addr, const uint8_t *buffer, int little, int count)
 638 {
 639         int i;
 640
 641         for (i = 0; i < count; i++) {
 642                 embeddedice_write_reg_inner(tap, reg_addr,
 643                                 fast_target_buffer_get_u32(buffer, little));
 644                 buffer += 4;
 645         }
 646 }
 647 #else
 648 /* provided by minidriver */
 649 #endif