1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "embeddedice.h"
33 #include "arm7_9_common.h"
38 #include "binarybuffer.h"
45 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
53 int embeddedice_reg_arch_info[] =
56 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
57 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
61 char* embeddedice_reg_list[] =
73 "watch 0 control value",
74 "watch 0 control mask",
80 "watch 1 control value",
81 "watch 1 control mask",
86 int embeddedice_reg_arch_type = -1;
88 int embeddedice_get_reg(reg_t *reg);
90 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
93 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
94 reg_t *reg_list = NULL;
95 embeddedice_reg_t *arch_info = NULL;
96 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
101 /* register a register arch-type for EmbeddedICE registers only once */
102 if (embeddedice_reg_arch_type == -1)
103 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
105 if (arm7_9->has_vector_catch)
110 /* the actual registers are kept in two arrays */
111 reg_list = calloc(num_regs, sizeof(reg_t));
112 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
114 /* fill in values for the reg cache */
115 reg_cache->name = "EmbeddedICE registers";
116 reg_cache->next = NULL;
117 reg_cache->reg_list = reg_list;
118 reg_cache->num_regs = num_regs;
120 /* set up registers */
121 for (i = 0; i < num_regs; i++)
123 reg_list[i].name = embeddedice_reg_list[i];
124 reg_list[i].size = 32;
125 reg_list[i].dirty = 0;
126 reg_list[i].valid = 0;
127 reg_list[i].bitfield_desc = NULL;
128 reg_list[i].num_bitfields = 0;
129 reg_list[i].value = calloc(1, 4);
130 reg_list[i].arch_info = &arch_info[i];
131 reg_list[i].arch_type = embeddedice_reg_arch_type;
132 arch_info[i].addr = embeddedice_reg_arch_info[i];
133 arch_info[i].jtag_info = jtag_info;
136 /* identify EmbeddedICE version by reading DCC control register */
137 embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
138 if ((retval=jtag_execute_queue())!=ERROR_OK)
140 for (i = 0; i < num_regs; i++)
142 free(reg_list[i].value);
149 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
151 switch (eice_version)
154 reg_list[EICE_DBG_CTRL].size = 3;
155 reg_list[EICE_DBG_STAT].size = 5;
158 reg_list[EICE_DBG_CTRL].size = 4;
159 reg_list[EICE_DBG_STAT].size = 5;
160 arm7_9->has_single_step = 1;
163 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
164 reg_list[EICE_DBG_CTRL].size = 6;
165 reg_list[EICE_DBG_STAT].size = 5;
166 arm7_9->has_single_step = 1;
167 arm7_9->has_monitor_mode = 1;
170 reg_list[EICE_DBG_CTRL].size = 6;
171 reg_list[EICE_DBG_STAT].size = 5;
172 arm7_9->has_monitor_mode = 1;
175 reg_list[EICE_DBG_CTRL].size = 6;
176 reg_list[EICE_DBG_STAT].size = 5;
177 arm7_9->has_single_step = 1;
178 arm7_9->has_monitor_mode = 1;
181 reg_list[EICE_DBG_CTRL].size = 6;
182 reg_list[EICE_DBG_STAT].size = 10;
183 arm7_9->has_monitor_mode = 1;
186 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
187 reg_list[EICE_DBG_CTRL].size = 6;
188 reg_list[EICE_DBG_STAT].size = 5;
189 arm7_9->has_monitor_mode = 1;
192 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
198 int embeddedice_setup(target_t *target)
201 armv4_5_common_t *armv4_5 = target->arch_info;
202 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
204 /* explicitly disable monitor mode */
205 if (arm7_9->has_monitor_mode)
207 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
209 embeddedice_read_reg(dbg_ctrl);
210 if ((retval=jtag_execute_queue())!=ERROR_OK)
212 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
213 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
215 return jtag_execute_queue();
218 int embeddedice_get_reg(reg_t *reg)
221 if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
223 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
227 if ((retval = jtag_execute_queue()) != ERROR_OK)
229 LOG_ERROR("register read failed");
236 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
238 embeddedice_reg_t *ice_reg = reg->arch_info;
239 u8 reg_addr = ice_reg->addr & 0x1f;
240 scan_field_t fields[3];
244 jtag_add_end_state(TAP_IDLE);
245 arm_jtag_scann(ice_reg->jtag_info, 0x2);
247 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
249 fields[0].tap = ice_reg->jtag_info->tap;
250 fields[0].num_bits = 32;
251 fields[0].out_value = reg->value;
252 fields[0].out_mask = NULL;
253 fields[0].in_value = NULL;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
256 fields[0].in_handler = NULL;
257 fields[0].in_handler_priv = NULL;
259 fields[1].tap = ice_reg->jtag_info->tap;
260 fields[1].num_bits = 5;
261 fields[1].out_value = field1_out;
262 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
263 fields[1].out_mask = NULL;
264 fields[1].in_value = NULL;
265 fields[1].in_check_value = NULL;
266 fields[1].in_check_mask = NULL;
267 fields[1].in_handler = NULL;
268 fields[1].in_handler_priv = NULL;
270 fields[2].tap = ice_reg->jtag_info->tap;
271 fields[2].num_bits = 1;
272 fields[2].out_value = field2_out;
273 buf_set_u32(fields[2].out_value, 0, 1, 0);
274 fields[2].out_mask = NULL;
275 fields[2].in_value = NULL;
276 fields[2].in_check_value = NULL;
277 fields[2].in_check_mask = NULL;
278 fields[2].in_handler = NULL;
279 fields[2].in_handler_priv = NULL;
281 jtag_add_dr_scan(3, fields, TAP_INVALID);
283 fields[0].in_value = reg->value;
284 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
286 /* when reading the DCC data register, leaving the address field set to
287 * EICE_COMMS_DATA would read the register twice
288 * reading the control register is safe
290 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
292 jtag_add_dr_scan(3, fields, TAP_INVALID);
297 /* receive <size> words of 32 bit from the DCC
298 * we pretend the target is always going to be fast enough
299 * (relative to the JTAG clock), so we don't need to handshake
301 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
303 scan_field_t fields[3];
307 jtag_add_end_state(TAP_IDLE);
308 arm_jtag_scann(jtag_info, 0x2);
309 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
311 fields[0].tap = jtag_info->tap;
312 fields[0].num_bits = 32;
313 fields[0].out_value = NULL;
314 fields[0].out_mask = NULL;
315 fields[0].in_value = NULL;
316 fields[0].in_check_value = NULL;
317 fields[0].in_check_mask = NULL;
318 fields[0].in_handler = NULL;
319 fields[0].in_handler_priv = NULL;
321 fields[1].tap = jtag_info->tap;
322 fields[1].num_bits = 5;
323 fields[1].out_value = field1_out;
324 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
325 fields[1].out_mask = NULL;
326 fields[1].in_value = NULL;
327 fields[1].in_check_value = NULL;
328 fields[1].in_check_mask = NULL;
329 fields[1].in_handler = NULL;
330 fields[1].in_handler_priv = NULL;
332 fields[2].tap = jtag_info->tap;
333 fields[2].num_bits = 1;
334 fields[2].out_value = field2_out;
335 buf_set_u32(fields[2].out_value, 0, 1, 0);
336 fields[2].out_mask = NULL;
337 fields[2].in_value = NULL;
338 fields[2].in_check_value = NULL;
339 fields[2].in_check_mask = NULL;
340 fields[2].in_handler = NULL;
341 fields[2].in_handler_priv = NULL;
343 jtag_add_dr_scan(3, fields, TAP_INVALID);
347 /* when reading the last item, set the register address to the DCC control reg,
348 * to avoid reading additional data from the DCC data reg
351 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
353 fields[0].in_handler = arm_jtag_buf_to_u32;
354 fields[0].in_handler_priv = data;
355 jtag_add_dr_scan(3, fields, TAP_INVALID);
361 return jtag_execute_queue();
364 int embeddedice_read_reg(reg_t *reg)
366 return embeddedice_read_reg_w_check(reg, NULL, NULL);
369 void embeddedice_set_reg(reg_t *reg, u32 value)
371 embeddedice_write_reg(reg, value);
373 buf_set_u32(reg->value, 0, reg->size, value);
379 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
382 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
384 if ((retval = jtag_execute_queue()) != ERROR_OK)
386 LOG_ERROR("register write failed");
392 void embeddedice_write_reg(reg_t *reg, u32 value)
394 embeddedice_reg_t *ice_reg = reg->arch_info;
396 LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
398 jtag_add_end_state(TAP_IDLE);
399 arm_jtag_scann(ice_reg->jtag_info, 0x2);
401 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
403 u8 reg_addr = ice_reg->addr & 0x1f;
404 embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
408 void embeddedice_store_reg(reg_t *reg)
410 embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
413 /* send <size> words of 32 bit to the DCC
414 * we pretend the target is always going to be fast enough
415 * (relative to the JTAG clock), so we don't need to handshake
417 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
419 scan_field_t fields[3];
424 jtag_add_end_state(TAP_IDLE);
425 arm_jtag_scann(jtag_info, 0x2);
426 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
428 fields[0].tap = jtag_info->tap;
429 fields[0].num_bits = 32;
430 fields[0].out_value = field0_out;
431 fields[0].out_mask = NULL;
432 fields[0].in_value = NULL;
433 fields[0].in_check_value = NULL;
434 fields[0].in_check_mask = NULL;
435 fields[0].in_handler = NULL;
436 fields[0].in_handler_priv = NULL;
438 fields[1].tap = jtag_info->tap;
439 fields[1].num_bits = 5;
440 fields[1].out_value = field1_out;
441 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
442 fields[1].out_mask = NULL;
443 fields[1].in_value = NULL;
444 fields[1].in_check_value = NULL;
445 fields[1].in_check_mask = NULL;
446 fields[1].in_handler = NULL;
447 fields[1].in_handler_priv = NULL;
449 fields[2].tap = jtag_info->tap;
450 fields[2].num_bits = 1;
451 fields[2].out_value = field2_out;
452 buf_set_u32(fields[2].out_value, 0, 1, 1);
453 fields[2].out_mask = NULL;
454 fields[2].in_value = NULL;
455 fields[2].in_check_value = NULL;
456 fields[2].in_check_mask = NULL;
457 fields[2].in_handler = NULL;
458 fields[2].in_handler_priv = NULL;
462 buf_set_u32(fields[0].out_value, 0, 32, *data);
463 jtag_add_dr_scan(3, fields, TAP_INVALID);
469 /* call to jtag_execute_queue() intentionally omitted */
473 /* wait for DCC control register R/W handshake bit to become active
475 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
477 scan_field_t fields[3];
486 if (hsbit == EICE_COMM_CTRL_WBIT)
488 else if (hsbit == EICE_COMM_CTRL_RBIT)
491 return ERROR_INVALID_ARGUMENTS;
493 jtag_add_end_state(TAP_IDLE);
494 arm_jtag_scann(jtag_info, 0x2);
495 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
497 fields[0].tap = jtag_info->tap;
498 fields[0].num_bits = 32;
499 fields[0].out_value = NULL;
500 fields[0].out_mask = NULL;
501 fields[0].in_value = field0_in;
502 fields[0].in_check_value = NULL;
503 fields[0].in_check_mask = NULL;
504 fields[0].in_handler = NULL;
505 fields[0].in_handler_priv = NULL;
507 fields[1].tap = jtag_info->tap;
508 fields[1].num_bits = 5;
509 fields[1].out_value = field1_out;
510 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
511 fields[1].out_mask = NULL;
512 fields[1].in_value = NULL;
513 fields[1].in_check_value = NULL;
514 fields[1].in_check_mask = NULL;
515 fields[1].in_handler = NULL;
516 fields[1].in_handler_priv = NULL;
518 fields[2].tap = jtag_info->tap;
519 fields[2].num_bits = 1;
520 fields[2].out_value = field2_out;
521 buf_set_u32(fields[2].out_value, 0, 1, 0);
522 fields[2].out_mask = NULL;
523 fields[2].in_value = NULL;
524 fields[2].in_check_value = NULL;
525 fields[2].in_check_mask = NULL;
526 fields[2].in_handler = NULL;
527 fields[2].in_handler_priv = NULL;
529 jtag_add_dr_scan(3, fields, TAP_INVALID);
530 gettimeofday(&lap, NULL);
533 jtag_add_dr_scan(3, fields, TAP_INVALID);
534 if ((retval = jtag_execute_queue()) != ERROR_OK)
537 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
540 gettimeofday(&now, NULL);
542 while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
544 return ERROR_TARGET_TIMEOUT;
547 /* this is the inner loop of the open loop DCC write of data to target */
548 void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
551 for (i = 0; i < count; i++)
553 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));