1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "embeddedice.h"
33 #include "arm7_9_common.h"
38 #include "binarybuffer.h"
46 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
55 static int embeddedice_reg_arch_info[] =
58 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
59 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
63 static char* embeddedice_reg_list[] =
75 "watch 0 control value",
76 "watch 0 control mask",
82 "watch 1 control value",
83 "watch 1 control mask",
88 static int embeddedice_reg_arch_type = -1;
90 static int embeddedice_get_reg(reg_t *reg);
92 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
95 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
96 reg_t *reg_list = NULL;
97 embeddedice_reg_t *arch_info = NULL;
98 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
101 int eice_version = 0;
103 /* register a register arch-type for EmbeddedICE registers only once */
104 if (embeddedice_reg_arch_type == -1)
105 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
107 if (arm7_9->has_vector_catch)
112 /* the actual registers are kept in two arrays */
113 reg_list = calloc(num_regs, sizeof(reg_t));
114 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
116 /* fill in values for the reg cache */
117 reg_cache->name = "EmbeddedICE registers";
118 reg_cache->next = NULL;
119 reg_cache->reg_list = reg_list;
120 reg_cache->num_regs = num_regs;
122 /* set up registers */
123 for (i = 0; i < num_regs; i++)
125 reg_list[i].name = embeddedice_reg_list[i];
126 reg_list[i].size = 32;
127 reg_list[i].dirty = 0;
128 reg_list[i].valid = 0;
129 reg_list[i].bitfield_desc = NULL;
130 reg_list[i].num_bitfields = 0;
131 reg_list[i].value = calloc(1, 4);
132 reg_list[i].arch_info = &arch_info[i];
133 reg_list[i].arch_type = embeddedice_reg_arch_type;
134 arch_info[i].addr = embeddedice_reg_arch_info[i];
135 arch_info[i].jtag_info = jtag_info;
138 /* identify EmbeddedICE version by reading DCC control register */
139 embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
140 if ((retval=jtag_execute_queue())!=ERROR_OK)
142 for (i = 0; i < num_regs; i++)
144 free(reg_list[i].value);
151 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
153 switch (eice_version)
156 reg_list[EICE_DBG_CTRL].size = 3;
157 reg_list[EICE_DBG_STAT].size = 5;
160 reg_list[EICE_DBG_CTRL].size = 4;
161 reg_list[EICE_DBG_STAT].size = 5;
162 arm7_9->has_single_step = 1;
165 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
166 reg_list[EICE_DBG_CTRL].size = 6;
167 reg_list[EICE_DBG_STAT].size = 5;
168 arm7_9->has_single_step = 1;
169 arm7_9->has_monitor_mode = 1;
172 reg_list[EICE_DBG_CTRL].size = 6;
173 reg_list[EICE_DBG_STAT].size = 5;
174 arm7_9->has_monitor_mode = 1;
177 reg_list[EICE_DBG_CTRL].size = 6;
178 reg_list[EICE_DBG_STAT].size = 5;
179 arm7_9->has_single_step = 1;
180 arm7_9->has_monitor_mode = 1;
183 reg_list[EICE_DBG_CTRL].size = 6;
184 reg_list[EICE_DBG_STAT].size = 10;
185 arm7_9->has_monitor_mode = 1;
188 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
189 reg_list[EICE_DBG_CTRL].size = 6;
190 reg_list[EICE_DBG_STAT].size = 5;
191 arm7_9->has_monitor_mode = 1;
194 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
200 int embeddedice_setup(target_t *target)
203 armv4_5_common_t *armv4_5 = target->arch_info;
204 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
206 /* explicitly disable monitor mode */
207 if (arm7_9->has_monitor_mode)
209 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
211 embeddedice_read_reg(dbg_ctrl);
212 if ((retval=jtag_execute_queue())!=ERROR_OK)
214 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
215 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
217 return jtag_execute_queue();
220 static int embeddedice_get_reg(reg_t *reg)
223 if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
225 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
229 if ((retval = jtag_execute_queue()) != ERROR_OK)
231 LOG_ERROR("register read failed");
238 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
240 embeddedice_reg_t *ice_reg = reg->arch_info;
241 u8 reg_addr = ice_reg->addr & 0x1f;
242 scan_field_t fields[3];
246 jtag_add_end_state(TAP_IDLE);
247 arm_jtag_scann(ice_reg->jtag_info, 0x2);
249 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
251 fields[0].tap = ice_reg->jtag_info->tap;
252 fields[0].num_bits = 32;
253 fields[0].out_value = reg->value;
254 fields[0].in_value = NULL;
257 fields[1].tap = ice_reg->jtag_info->tap;
258 fields[1].num_bits = 5;
259 fields[1].out_value = field1_out;
260 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
261 fields[1].in_value = NULL;
264 fields[2].tap = ice_reg->jtag_info->tap;
265 fields[2].num_bits = 1;
266 fields[2].out_value = field2_out;
267 buf_set_u32(fields[2].out_value, 0, 1, 0);
268 fields[2].in_value = NULL;
271 jtag_add_dr_scan(3, fields, TAP_INVALID);
273 fields[0].in_value = reg->value;
275 /* when reading the DCC data register, leaving the address field set to
276 * EICE_COMMS_DATA would read the register twice
277 * reading the control register is safe
279 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
281 jtag_add_dr_scan(3, fields, TAP_INVALID);
283 jtag_check_value_mask(fields+0, check_value, check_mask);
288 /* receive <size> words of 32 bit from the DCC
289 * we pretend the target is always going to be fast enough
290 * (relative to the JTAG clock), so we don't need to handshake
292 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
294 scan_field_t fields[3];
298 jtag_add_end_state(TAP_IDLE);
299 arm_jtag_scann(jtag_info, 0x2);
300 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
302 fields[0].tap = jtag_info->tap;
303 fields[0].num_bits = 32;
304 fields[0].out_value = NULL;
306 fields[0].in_value = tmp;
309 fields[1].tap = jtag_info->tap;
310 fields[1].num_bits = 5;
311 fields[1].out_value = field1_out;
312 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
313 fields[1].in_value = NULL;
316 fields[2].tap = jtag_info->tap;
317 fields[2].num_bits = 1;
318 fields[2].out_value = field2_out;
319 buf_set_u32(fields[2].out_value, 0, 1, 0);
320 fields[2].in_value = NULL;
323 jtag_add_dr_scan(3, fields, TAP_INVALID);
327 /* when reading the last item, set the register address to the DCC control reg,
328 * to avoid reading additional data from the DCC data reg
331 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
333 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
335 *data = le_to_h_u32(tmp);
341 return jtag_execute_queue();
344 int embeddedice_read_reg(reg_t *reg)
346 return embeddedice_read_reg_w_check(reg, NULL, NULL);
349 void embeddedice_set_reg(reg_t *reg, u32 value)
351 embeddedice_write_reg(reg, value);
353 buf_set_u32(reg->value, 0, reg->size, value);
359 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
362 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
364 if ((retval = jtag_execute_queue()) != ERROR_OK)
366 LOG_ERROR("register write failed");
372 void embeddedice_write_reg(reg_t *reg, u32 value)
374 embeddedice_reg_t *ice_reg = reg->arch_info;
376 LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
378 jtag_add_end_state(TAP_IDLE);
379 arm_jtag_scann(ice_reg->jtag_info, 0x2);
381 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
383 u8 reg_addr = ice_reg->addr & 0x1f;
384 embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
388 void embeddedice_store_reg(reg_t *reg)
390 embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
393 /* send <size> words of 32 bit to the DCC
394 * we pretend the target is always going to be fast enough
395 * (relative to the JTAG clock), so we don't need to handshake
397 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
399 scan_field_t fields[3];
404 jtag_add_end_state(TAP_IDLE);
405 arm_jtag_scann(jtag_info, 0x2);
406 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
408 fields[0].tap = jtag_info->tap;
409 fields[0].num_bits = 32;
410 fields[0].out_value = field0_out;
412 fields[0].in_value = NULL;
418 fields[1].tap = jtag_info->tap;
419 fields[1].num_bits = 5;
420 fields[1].out_value = field1_out;
421 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
423 fields[1].in_value = NULL;
429 fields[2].tap = jtag_info->tap;
430 fields[2].num_bits = 1;
431 fields[2].out_value = field2_out;
432 buf_set_u32(fields[2].out_value, 0, 1, 1);
434 fields[2].in_value = NULL;
442 buf_set_u32(fields[0].out_value, 0, 32, *data);
443 jtag_add_dr_scan(3, fields, TAP_INVALID);
449 /* call to jtag_execute_queue() intentionally omitted */
453 /* wait for DCC control register R/W handshake bit to become active
455 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
457 scan_field_t fields[3];
466 if (hsbit == EICE_COMM_CTRL_WBIT)
468 else if (hsbit == EICE_COMM_CTRL_RBIT)
471 return ERROR_INVALID_ARGUMENTS;
473 jtag_add_end_state(TAP_IDLE);
474 arm_jtag_scann(jtag_info, 0x2);
475 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
477 fields[0].tap = jtag_info->tap;
478 fields[0].num_bits = 32;
479 fields[0].out_value = NULL;
481 fields[0].in_value = field0_in;
487 fields[1].tap = jtag_info->tap;
488 fields[1].num_bits = 5;
489 fields[1].out_value = field1_out;
490 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
492 fields[1].in_value = NULL;
498 fields[2].tap = jtag_info->tap;
499 fields[2].num_bits = 1;
500 fields[2].out_value = field2_out;
501 buf_set_u32(fields[2].out_value, 0, 1, 0);
503 fields[2].in_value = NULL;
509 jtag_add_dr_scan(3, fields, TAP_INVALID);
510 gettimeofday(&lap, NULL);
513 jtag_add_dr_scan(3, fields, TAP_INVALID);
514 if ((retval = jtag_execute_queue()) != ERROR_OK)
517 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
520 gettimeofday(&now, NULL);
522 while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
524 return ERROR_TARGET_TIMEOUT;
527 /* this is the inner loop of the open loop DCC write of data to target */
528 void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
531 for (i = 0; i < count; i++)
533 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));