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[openocd] / src / target / embeddedice.h
1 /***************************************************************************
2  *   Copyright (C) 2005, 2006 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifndef EMBEDDED_ICE_H
21 #define EMBEDDED_ICE_H
22
23 #include "target.h"
24 #include "register.h"
25 #include "arm_jtag.h"
26
27 enum
28 {
29         EICE_DBG_CTRL = 0,
30         EICE_DBG_STAT = 1,
31         EICE_COMMS_CTRL = 2,
32         EICE_COMMS_DATA = 3,
33         EICE_W0_ADDR_VALUE = 4,
34         EICE_W0_ADDR_MASK = 5,
35         EICE_W0_DATA_VALUE  = 6,
36         EICE_W0_DATA_MASK = 7,
37         EICE_W0_CONTROL_VALUE = 8,
38         EICE_W0_CONTROL_MASK = 9,
39         EICE_W1_ADDR_VALUE = 10,
40         EICE_W1_ADDR_MASK = 11,
41         EICE_W1_DATA_VALUE = 12,
42         EICE_W1_DATA_MASK = 13,
43         EICE_W1_CONTROL_VALUE = 14,
44         EICE_W1_CONTROL_MASK = 15,
45         EICE_ABT_STATUS = 16,
46         EICE_VEC_CATCH = 16
47 };
48
49 enum
50 {
51         EICE_DBG_CONTROL_ICEDIS = 5,
52         EICE_DBG_CONTROL_MONEN = 4,     
53         EICE_DBG_CONTROL_INTDIS = 2,
54         EICE_DBG_CONTROL_DBGRQ = 1,
55         EICE_DBG_CONTROL_DBGACK = 0,
56 };
57
58 enum
59 {
60         EICE_DBG_STATUS_ITBIT = 4,
61         EICE_DBG_STATUS_SYSCOMP = 3,
62         EICE_DBG_STATUS_IFEN = 2,
63         EICE_DBG_STATUS_DBGRQ = 1,
64         EICE_DBG_STATUS_DBGACK = 0
65 };
66
67 enum
68 {
69         EICE_W_CTRL_ENABLE = 0x100,
70         EICE_W_CTRL_RANGE = 0x80,
71         EICE_W_CTRL_CHAIN = 0x40,
72         EICE_W_CTRL_EXTERN = 0x20,
73         EICE_W_CTRL_nTRANS = 0x10,
74         EICE_W_CTRL_nOPC = 0x8,
75         EICE_W_CTRL_MAS = 0x6,
76         EICE_W_CTRL_ITBIT = 0x2,
77         EICE_W_CTRL_nRW = 0x1
78 };
79
80 enum
81 {
82         EICE_COMM_CTRL_WBIT = 1,
83         EICE_COMM_CTRL_RBIT = 0
84 };
85
86 typedef struct embeddedice_reg_s
87 {
88         int addr;
89         arm_jtag_t *jtag_info;
90 } embeddedice_reg_t;
91
92 extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);
93 extern int embeddedice_read_reg(reg_t *reg);
94 extern int embeddedice_write_reg(reg_t *reg, u32 value);
95 extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
96 extern int embeddedice_store_reg(reg_t *reg);
97 extern int embeddedice_set_reg(reg_t *reg, u32 value);
98 extern int embeddedice_set_reg_w_exec(reg_t *reg, u32 value);
99
100 #endif /* EMBEDDED_ICE_H */